pinctrl-at91.c (a2fcb1ce88409497b6e8b0f45a41052d5f07e508) pinctrl-at91.c (64e21add8cd9717f042b523f35ea831eab14261b)
1/*
2 * at91 pinctrl driver based on at91 pinmux core
3 *
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Under GPLv2 only
7 */
8

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54#define PULL_DOWN (1 << 3)
55#define DIS_SCHMIT (1 << 4)
56#define DRIVE_STRENGTH_SHIFT 5
57#define DRIVE_STRENGTH_MASK 0x3
58#define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
59#define OUTPUT (1 << 7)
60#define OUTPUT_VAL_SHIFT 8
61#define OUTPUT_VAL (0x1 << OUTPUT_VAL_SHIFT)
1/*
2 * at91 pinctrl driver based on at91 pinmux core
3 *
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Under GPLv2 only
7 */
8

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54#define PULL_DOWN (1 << 3)
55#define DIS_SCHMIT (1 << 4)
56#define DRIVE_STRENGTH_SHIFT 5
57#define DRIVE_STRENGTH_MASK 0x3
58#define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
59#define OUTPUT (1 << 7)
60#define OUTPUT_VAL_SHIFT 8
61#define OUTPUT_VAL (0x1 << OUTPUT_VAL_SHIFT)
62#define SLEWRATE_SHIFT 9
63#define SLEWRATE_MASK 0x1
64#define SLEWRATE (SLEWRATE_MASK << SLEWRATE_SHIFT)
62#define DEBOUNCE (1 << 16)
63#define DEBOUNCE_VAL_SHIFT 17
64#define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
65
66/**
67 * These defines will translated the dt binding settings to our internal
68 * settings. They are not necessarily the same value as the register setting.
69 * The actual drive strength current of low, medium and high must be looked up

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77 DRIVE_STRENGTH_BIT_LOW,
78 DRIVE_STRENGTH_BIT_MED,
79 DRIVE_STRENGTH_BIT_HI,
80};
81
82#define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
83 DRIVE_STRENGTH_SHIFT)
84
65#define DEBOUNCE (1 << 16)
66#define DEBOUNCE_VAL_SHIFT 17
67#define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
68
69/**
70 * These defines will translated the dt binding settings to our internal
71 * settings. They are not necessarily the same value as the register setting.
72 * The actual drive strength current of low, medium and high must be looked up

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80 DRIVE_STRENGTH_BIT_LOW,
81 DRIVE_STRENGTH_BIT_MED,
82 DRIVE_STRENGTH_BIT_HI,
83};
84
85#define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
86 DRIVE_STRENGTH_SHIFT)
87
88enum slewrate_bit {
89 SLEWRATE_BIT_DIS,
90 SLEWRATE_BIT_ENA,
91};
92
93#define SLEWRATE_BIT_MSK(name) (SLEWRATE_BIT_##name << SLEWRATE_SHIFT)
94
85/**
86 * struct at91_pmx_func - describes AT91 pinmux functions
87 * @name: the name of this specific function
88 * @groups: corresponding pin groups
89 * @ngroups: the number of groups
90 */
91struct at91_pmx_func {
92 const char *name;

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166 void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div);
167 bool (*get_pulldown)(void __iomem *pio, unsigned pin);
168 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
169 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
170 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
171 unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
172 void (*set_drivestrength)(void __iomem *pio, unsigned pin,
173 u32 strength);
95/**
96 * struct at91_pmx_func - describes AT91 pinmux functions
97 * @name: the name of this specific function
98 * @groups: corresponding pin groups
99 * @ngroups: the number of groups
100 */
101struct at91_pmx_func {
102 const char *name;

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176 void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div);
177 bool (*get_pulldown)(void __iomem *pio, unsigned pin);
178 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
179 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
180 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
181 unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
182 void (*set_drivestrength)(void __iomem *pio, unsigned pin,
183 u32 strength);
184 unsigned (*get_slewrate)(void __iomem *pio, unsigned pin);
185 void (*set_slewrate)(void __iomem *pio, unsigned pin, u32 slewrate);
174 /* irq */
175 int (*irq_type)(struct irq_data *d, unsigned type);
176};
177
178static int gpio_irq_type(struct irq_data *d, unsigned type);
179static int alt_gpio_irq_type(struct irq_data *d, unsigned type);
180
181struct at91_pinctrl {

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580 unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
581
582 if (tmp & BIT(pin))
583 return DRIVE_STRENGTH_BIT_HI;
584
585 return DRIVE_STRENGTH_BIT_LOW;
586}
587
186 /* irq */
187 int (*irq_type)(struct irq_data *d, unsigned type);
188};
189
190static int gpio_irq_type(struct irq_data *d, unsigned type);
191static int alt_gpio_irq_type(struct irq_data *d, unsigned type);
192
193struct at91_pinctrl {

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592 unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
593
594 if (tmp & BIT(pin))
595 return DRIVE_STRENGTH_BIT_HI;
596
597 return DRIVE_STRENGTH_BIT_LOW;
598}
599
600static unsigned at91_mux_sam9x60_get_slewrate(void __iomem *pio, unsigned pin)
601{
602 unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
603
604 if ((tmp & BIT(pin)))
605 return SLEWRATE_BIT_ENA;
606
607 return SLEWRATE_BIT_DIS;
608}
609
588static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
589{
590 unsigned tmp = readl_relaxed(reg);
591 unsigned shift = two_bit_pin_value_shift_amount(pin);
592
593 tmp &= ~(DRIVE_STRENGTH_MASK << shift);
594 tmp |= strength << shift;
595

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638 if (setting == DRIVE_STRENGTH_BIT_LOW)
639 tmp &= ~BIT(pin);
640 else
641 tmp |= BIT(pin);
642
643 writel_relaxed(tmp, pio + SAM9X60_PIO_DRIVER1);
644}
645
610static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
611{
612 unsigned tmp = readl_relaxed(reg);
613 unsigned shift = two_bit_pin_value_shift_amount(pin);
614
615 tmp &= ~(DRIVE_STRENGTH_MASK << shift);
616 tmp |= strength << shift;
617

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660 if (setting == DRIVE_STRENGTH_BIT_LOW)
661 tmp &= ~BIT(pin);
662 else
663 tmp |= BIT(pin);
664
665 writel_relaxed(tmp, pio + SAM9X60_PIO_DRIVER1);
666}
667
668static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin,
669 u32 setting)
670{
671 unsigned int tmp;
672
673 if (setting < SLEWRATE_BIT_DIS || setting > SLEWRATE_BIT_ENA)
674 return;
675
676 tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
677
678 if (setting == SLEWRATE_BIT_DIS)
679 tmp &= ~BIT(pin);
680 else
681 tmp |= BIT(pin);
682
683 writel_relaxed(tmp, pio + SAM9X60_PIO_SLEWR);
684}
685
646static struct at91_pinctrl_mux_ops at91rm9200_ops = {
647 .get_periph = at91_mux_get_periph,
648 .mux_A_periph = at91_mux_set_A_periph,
649 .mux_B_periph = at91_mux_set_B_periph,
650 .get_deglitch = at91_mux_get_deglitch,
651 .set_deglitch = at91_mux_set_deglitch,
652 .irq_type = gpio_irq_type,
653};

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682 .get_debounce = at91_mux_pio3_get_debounce,
683 .set_debounce = at91_mux_pio3_set_debounce,
684 .get_pulldown = at91_mux_pio3_get_pulldown,
685 .set_pulldown = at91_mux_pio3_set_pulldown,
686 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
687 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
688 .get_drivestrength = at91_mux_sam9x60_get_drivestrength,
689 .set_drivestrength = at91_mux_sam9x60_set_drivestrength,
686static struct at91_pinctrl_mux_ops at91rm9200_ops = {
687 .get_periph = at91_mux_get_periph,
688 .mux_A_periph = at91_mux_set_A_periph,
689 .mux_B_periph = at91_mux_set_B_periph,
690 .get_deglitch = at91_mux_get_deglitch,
691 .set_deglitch = at91_mux_set_deglitch,
692 .irq_type = gpio_irq_type,
693};

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722 .get_debounce = at91_mux_pio3_get_debounce,
723 .set_debounce = at91_mux_pio3_set_debounce,
724 .get_pulldown = at91_mux_pio3_get_pulldown,
725 .set_pulldown = at91_mux_pio3_set_pulldown,
726 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
727 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
728 .get_drivestrength = at91_mux_sam9x60_get_drivestrength,
729 .set_drivestrength = at91_mux_sam9x60_set_drivestrength,
730 .get_slewrate = at91_mux_sam9x60_get_slewrate,
731 .set_slewrate = at91_mux_sam9x60_set_slewrate,
690 .irq_type = alt_gpio_irq_type,
691
692};
693
694static struct at91_pinctrl_mux_ops sama5d3_ops = {
695 .get_periph = at91_mux_pio3_get_periph,
696 .mux_A_periph = at91_mux_pio3_set_A_periph,
697 .mux_B_periph = at91_mux_pio3_set_B_periph,

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945 *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT);
946 if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin))
947 *config |= PULL_DOWN;
948 if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
949 *config |= DIS_SCHMIT;
950 if (info->ops->get_drivestrength)
951 *config |= (info->ops->get_drivestrength(pio, pin)
952 << DRIVE_STRENGTH_SHIFT);
732 .irq_type = alt_gpio_irq_type,
733
734};
735
736static struct at91_pinctrl_mux_ops sama5d3_ops = {
737 .get_periph = at91_mux_pio3_get_periph,
738 .mux_A_periph = at91_mux_pio3_set_A_periph,
739 .mux_B_periph = at91_mux_pio3_set_B_periph,

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987 *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT);
988 if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin))
989 *config |= PULL_DOWN;
990 if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
991 *config |= DIS_SCHMIT;
992 if (info->ops->get_drivestrength)
993 *config |= (info->ops->get_drivestrength(pio, pin)
994 << DRIVE_STRENGTH_SHIFT);
995 if (info->ops->get_slewrate)
996 *config |= (info->ops->get_slewrate(pio, pin) << SLEWRATE_SHIFT);
953 if (at91_mux_get_output(pio, pin, &out))
954 *config |= OUTPUT | (out << OUTPUT_VAL_SHIFT);
955
956 return 0;
957}
958
959static int at91_pinconf_set(struct pinctrl_dev *pctldev,
960 unsigned pin_id, unsigned long *configs,

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996 if (info->ops->set_pulldown)
997 info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
998 if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
999 info->ops->disable_schmitt_trig(pio, mask);
1000 if (info->ops->set_drivestrength)
1001 info->ops->set_drivestrength(pio, pin,
1002 (config & DRIVE_STRENGTH)
1003 >> DRIVE_STRENGTH_SHIFT);
997 if (at91_mux_get_output(pio, pin, &out))
998 *config |= OUTPUT | (out << OUTPUT_VAL_SHIFT);
999
1000 return 0;
1001}
1002
1003static int at91_pinconf_set(struct pinctrl_dev *pctldev,
1004 unsigned pin_id, unsigned long *configs,

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1040 if (info->ops->set_pulldown)
1041 info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
1042 if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
1043 info->ops->disable_schmitt_trig(pio, mask);
1044 if (info->ops->set_drivestrength)
1045 info->ops->set_drivestrength(pio, pin,
1046 (config & DRIVE_STRENGTH)
1047 >> DRIVE_STRENGTH_SHIFT);
1048 if (info->ops->set_slewrate)
1049 info->ops->set_slewrate(pio, pin,
1050 (config & SLEWRATE) >> SLEWRATE_SHIFT);
1004
1005 } /* for each config */
1006
1007 return 0;
1008}
1009
1010#define DBG_SHOW_FLAG(flag) do { \
1011 if (config & flag) { \

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1039 DBG_SHOW_FLAG(DIS_SCHMIT);
1040 DBG_SHOW_FLAG(DEGLITCH);
1041 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW),
1042 DRIVE_STRENGTH_LOW);
1043 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED),
1044 DRIVE_STRENGTH_MED);
1045 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
1046 DRIVE_STRENGTH_HI);
1051
1052 } /* for each config */
1053
1054 return 0;
1055}
1056
1057#define DBG_SHOW_FLAG(flag) do { \
1058 if (config & flag) { \

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1086 DBG_SHOW_FLAG(DIS_SCHMIT);
1087 DBG_SHOW_FLAG(DEGLITCH);
1088 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW),
1089 DRIVE_STRENGTH_LOW);
1090 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED),
1091 DRIVE_STRENGTH_MED);
1092 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
1093 DRIVE_STRENGTH_HI);
1094 DBG_SHOW_FLAG(SLEWRATE);
1047 DBG_SHOW_FLAG(DEBOUNCE);
1048 if (config & DEBOUNCE) {
1049 val = config >> DEBOUNCE_VAL_SHIFT;
1050 seq_printf(s, "(%d)", val);
1051 }
1052
1053 return;
1054}

--- 856 unchanged lines hidden --- 		1095 DBG_SHOW_FLAG(DEBOUNCE);
1096 if (config & DEBOUNCE) {
1097 val = config >> DEBOUNCE_VAL_SHIFT;
1098 seq_printf(s, "(%d)", val);
1099 }
1100
1101 return;
1102}

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