pinctrl-intel.h (f25c3aa9085e9625f3dcc20152dd780d01a54c5a) pinctrl-intel.h (e57725eabf87c9c75bc73bd19ea00e887155e43f)
1/*
2 * Core pinctrl/GPIO driver for Intel GPIO controllers
3 *
4 * Copyright (C) 2015, Intel Corporation
5 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
6 * Mika Westerberg <mika.westerberg@linux.intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify

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53 * @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it
54 * is assumed that the host owns the pin (rather than
55 * ACPI).
56 * @ie_offset: Register offset of GPI_IE from @regs.
57 * @pin_base: Starting pin of pins in this community
58 * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
59 * HOSTSW_OWN, GPI_IS, GPI_IE, etc.
60 * @npins: Number of pins in this community
1/*
2 * Core pinctrl/GPIO driver for Intel GPIO controllers
3 *
4 * Copyright (C) 2015, Intel Corporation
5 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
6 * Mika Westerberg <mika.westerberg@linux.intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify

--- 44 unchanged lines hidden (view full) ---

53 * @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it
54 * is assumed that the host owns the pin (rather than
55 * ACPI).
56 * @ie_offset: Register offset of GPI_IE from @regs.
57 * @pin_base: Starting pin of pins in this community
58 * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
59 * HOSTSW_OWN, GPI_IS, GPI_IE, etc.
60 * @npins: Number of pins in this community
61 * @features: Additional features supported by the hardware
61 * @regs: Community specific common registers (reserved for core driver)
62 * @pad_regs: Community specific pad registers (reserved for core driver)
63 * @ngpps: Number of groups (hw groups) in this community (reserved for
64 * core driver)
65 */
66struct intel_community {
67 unsigned barno;
68 unsigned padown_offset;
69 unsigned padcfglock_offset;
70 unsigned hostown_offset;
71 unsigned ie_offset;
72 unsigned pin_base;
73 unsigned gpp_size;
74 size_t npins;
62 * @regs: Community specific common registers (reserved for core driver)
63 * @pad_regs: Community specific pad registers (reserved for core driver)
64 * @ngpps: Number of groups (hw groups) in this community (reserved for
65 * core driver)
66 */
67struct intel_community {
68 unsigned barno;
69 unsigned padown_offset;
70 unsigned padcfglock_offset;
71 unsigned hostown_offset;
72 unsigned ie_offset;
73 unsigned pin_base;
74 unsigned gpp_size;
75 size_t npins;
76 unsigned features;
75 void __iomem *regs;
76 void __iomem *pad_regs;
77 size_t ngpps;
78};
79
77 void __iomem *regs;
78 void __iomem *pad_regs;
79 size_t ngpps;
80};
81
82/* Additional features supported by the hardware */
83#define PINCTRL_FEATURE_DEBOUNCE BIT(0)
84
80#define PIN_GROUP(n, p, m) \
81 { \
82 .name = (n), \
83 .pins = (p), \
84 .npins = ARRAY_SIZE((p)), \
85 .mode = (m), \
86 }
87

--- 42 unchanged lines hidden --- 		85#define PIN_GROUP(n, p, m) \
86 { \
87 .name = (n), \
88 .pins = (p), \
89 .npins = ARRAY_SIZE((p)), \
90 .mode = (m), \
91 }
92

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