quirks.c (e98bdb3059cbf2b1cd4261e126b08429f64466c3) quirks.c (4091fb95b5f8dea37568d1a94c8227244bade891)
1/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>

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1629
1630static void quirk_pcie_mch(struct pci_dev *pdev)
1631{
1632 pdev->no_msi = 1;
1633}
1634DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1635DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1636DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>

--- 1620 unchanged lines hidden (view full) ---

1629
1630static void quirk_pcie_mch(struct pci_dev *pdev)
1631{
1632 pdev->no_msi = 1;
1633}
1634DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1635DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1636DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1637DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, quirk_pcie_mch);
1637
1638
1639/*
1640 * It's possible for the MSI to get corrupted if shpc and acpi
1641 * are used together on certain PXH-based systems.
1642 */
1643static void quirk_pcie_pxh(struct pci_dev *dev)
1644{

--- 589 unchanged lines hidden (view full) ---

2234 pcie_set_readrq(dev, 2048);
2235 }
2236}
2237
2238DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2239 PCI_DEVICE_ID_TIGON3_5719,
2240 quirk_brcm_5719_limit_mrrs);
2241
1638
1639
1640/*
1641 * It's possible for the MSI to get corrupted if shpc and acpi
1642 * are used together on certain PXH-based systems.
1643 */
1644static void quirk_pcie_pxh(struct pci_dev *dev)
1645{

--- 589 unchanged lines hidden (view full) ---

2235 pcie_set_readrq(dev, 2048);
2236 }
2237}
2238
2239DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2240 PCI_DEVICE_ID_TIGON3_5719,
2241 quirk_brcm_5719_limit_mrrs);
2242
2243#ifdef CONFIG_PCIE_IPROC_PLATFORM
2244static void quirk_paxc_bridge(struct pci_dev *pdev)
2245{
2246 /* The PCI config space is shared with the PAXC root port and the first
2247 * Ethernet device. So, we need to workaround this by telling the PCI
2248 * code that the bridge is not an Ethernet device.
2249 */
2250 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2251 pdev->class = PCI_CLASS_BRIDGE_PCI << 8;
2252
2253 /* MPSS is not being set properly (as it is currently 0). This is
2254 * because that area of the PCI config space is hard coded to zero, and
2255 * is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS)
2256 * so that the MPS can be set to the real max value.
2257 */
2258 pdev->pcie_mpss = 2;
2259}
2260DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge);
2261DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge);
2262#endif
2263
2242/* Originally in EDAC sources for i82875P:
2243 * Intel tells BIOS developers to hide device 6 which
2244 * configures the overflow device access containing
2245 * the DRBs - this is where we expose device 6.
2246 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2247 */
2248static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2249{

--- 858 unchanged lines hidden (view full) ---

3108/*
3109 * PCI devices which are on Intel chips can skip the 10ms delay
3110 * before entering D3 mode.
3111 */
3112static void quirk_remove_d3_delay(struct pci_dev *dev)
3113{
3114 dev->d3_delay = 0;
3115}
2264/* Originally in EDAC sources for i82875P:
2265 * Intel tells BIOS developers to hide device 6 which
2266 * configures the overflow device access containing
2267 * the DRBs - this is where we expose device 6.
2268 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2269 */
2270static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2271{

--- 858 unchanged lines hidden (view full) ---

3130/*
3131 * PCI devices which are on Intel chips can skip the 10ms delay
3132 * before entering D3 mode.
3133 */
3134static void quirk_remove_d3_delay(struct pci_dev *dev)
3135{
3136 dev->d3_delay = 0;
3137}
3116DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
3138/* C600 Series devices do not need 10ms d3_delay */
3117DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
3139DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
3140DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
3118DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
3141DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
3119DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
3120DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
3121DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
3122DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
3123DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
3142/* Lynxpoint-H PCH devices do not need 10ms d3_delay */
3143DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
3124DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
3125DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
3144DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
3145DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
3146DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
3147DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
3126DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
3148DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
3149DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
3150DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
3151DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
3152DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
3127DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
3153DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
3128DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
3129DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
3130/* Intel Cherrytrail devices do not need 10ms d3_delay */
3131DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
3154/* Intel Cherrytrail devices do not need 10ms d3_delay */
3155DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
3156DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
3157DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
3132DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
3158DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
3159DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
3160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
3133DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
3134DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
3135DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);
3161DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
3162DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
3163DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);
3136DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
3137DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
3138DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
3139DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
3140
3141/*
3142 * Some devices may pass our check in pci_intx_mask_supported() if
3143 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3144 * support this feature.
3145 */
3146static void quirk_broken_intx_masking(struct pci_dev *dev)
3147{

--- 453 unchanged lines hidden (view full) ---

3601 }
3602
3603 return 0;
3604}
3605
3606fs_initcall_sync(pci_apply_final_quirks);
3607
3608/*
3164
3165/*
3166 * Some devices may pass our check in pci_intx_mask_supported() if
3167 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3168 * support this feature.
3169 */
3170static void quirk_broken_intx_masking(struct pci_dev *dev)
3171{

--- 453 unchanged lines hidden (view full) ---

3625 }
3626
3627 return 0;
3628}
3629
3630fs_initcall_sync(pci_apply_final_quirks);
3631
3632/*
3609 * Followings are device-specific reset methods which can be used to
3633 * Following are device-specific reset methods which can be used to
3610 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3611 * not available.
3612 */
3613static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3614{
3615 /*
3616 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3617 *

--- 513 unchanged lines hidden (view full) ---

4131
4132 if (!pci_quirk_intel_pch_acs_match(dev))
4133 return -ENOTTY;
4134
4135 return acs_flags & ~flags ? 0 : 1;
4136}
4137
4138/*
3634 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3635 * not available.
3636 */
3637static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3638{
3639 /*
3640 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3641 *

--- 513 unchanged lines hidden (view full) ---

4155
4156 if (!pci_quirk_intel_pch_acs_match(dev))
4157 return -ENOTTY;
4158
4159 return acs_flags & ~flags ? 0 : 1;
4160}
4161
4162/*
4163 * These QCOM root ports do provide ACS-like features to disable peer
4164 * transactions and validate bus numbers in requests, but do not provide an
4165 * actual PCIe ACS capability. Hardware supports source validation but it
4166 * will report the issue as Completer Abort instead of ACS Violation.
4167 * Hardware doesn't support peer-to-peer and each root port is a root
4168 * complex with unique segment numbers. It is not possible for one root
4169 * port to pass traffic to another root port. All PCIe transactions are
4170 * terminated inside the root port.
4171 */
4172static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
4173{
4174 u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV);
4175 int ret = acs_flags & ~flags ? 0 : 1;
4176
4177 dev_info(&dev->dev, "Using QCOM ACS Quirk (%d)\n", ret);
4178
4179 return ret;
4180}
4181
4182/*
4139 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4140 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4141 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4142 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4143 * 7.16 ACS Extended Capability). The bit definitions are correct, but the
4144 * control register is at offset 8 instead of 6 and we should probably use
4145 * dword accesses to them. This applies to the following PCI Device IDs, as
4146 * found in volume 1 of the datasheet[2]:
4147 *
4148 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4149 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4150 *
4151 * N.B. This doesn't fix what lspci shows.
4152 *
4183 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4184 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4185 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4186 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4187 * 7.16 ACS Extended Capability). The bit definitions are correct, but the
4188 * control register is at offset 8 instead of 6 and we should probably use
4189 * dword accesses to them. This applies to the following PCI Device IDs, as
4190 * found in volume 1 of the datasheet[2]:
4191 *
4192 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4193 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4194 *
4195 * N.B. This doesn't fix what lspci shows.
4196 *
4197 * The 100 series chipset specification update includes this as errata #23[3].
4198 *
4199 * The 200 series chipset (Union Point) has the same bug according to the
4200 * specification update (Intel 200 Series Chipset Family Platform Controller
4201 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4202 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4203 * chipset include:
4204 *
4205 * 0xa290-0xa29f PCI Express Root port #{0-16}
4206 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4207 *
4153 * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4154 * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4208 * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4209 * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4210 * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4211 * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4212 * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4155 */
4156static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
4157{
4213 */
4214static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
4215{
4158 return pci_is_pcie(dev) &&
4159 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT &&
4160 ((dev->device & ~0xf) == 0xa110 ||
4161 (dev->device >= 0xa167 && dev->device <= 0xa16a));
4216 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4217 return false;
4218
4219 switch (dev->device) {
4220 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4221 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
4222 return true;
4223 }
4224
4225 return false;
4162}
4163
4164#define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4165
4166static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
4167{
4168 int pos;
4169 u32 cap, ctrl;

--- 96 unchanged lines hidden (view full) ---

4266 /* 82571 (Quads omitted due to non-ACS switch) */
4267 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
4268 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
4269 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
4270 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
4271 /* I219 */
4272 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
4273 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
4226}
4227
4228#define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4229
4230static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
4231{
4232 int pos;
4233 u32 cap, ctrl;

--- 96 unchanged lines hidden (view full) ---

4330 /* 82571 (Quads omitted due to non-ACS switch) */
4331 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
4332 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
4333 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
4334 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
4335 /* I219 */
4336 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
4337 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
4338 /* QCOM QDF2xxx root ports */
4339 { 0x17cb, 0x400, pci_quirk_qcom_rp_acs },
4340 { 0x17cb, 0x401, pci_quirk_qcom_rp_acs },
4274 /* Intel PCH root ports */
4275 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
4276 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
4277 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4278 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4279 /* Cavium ThunderX */
4280 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
4281 { 0 }

--- 287 unchanged lines hidden --- 		4341 /* Intel PCH root ports */
4342 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
4343 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
4344 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4345 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4346 /* Cavium ThunderX */
4347 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
4348 { 0 }

--- 287 unchanged lines hidden ---