pci.c (50e163d43ab123193a7f381528a7485881f730e9) pci.c (f6b6aefee70aa5261deec7feab80c249bf58397f)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 *
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
6 * David Mosberger-Tang
7 *
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>

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772 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
773}
774
775static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
776{
777 return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN;
778}
779
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 *
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
6 * David Mosberger-Tang
7 *
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>

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772 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
773}
774
775static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
776{
777 return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN;
778}
779
780static inline void platform_pci_refresh_power_state(struct pci_dev *dev)
781{
782 if (pci_platform_pm && pci_platform_pm->refresh_state)
783 pci_platform_pm->refresh_state(dev);
784}
785
786static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
787{
788 return pci_platform_pm ?
789 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
790}
791
792static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)
793{

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939 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
940 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
941 } else {
942 dev->current_state = state;
943 }
944}
945
946/**
780static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
781{
782 return pci_platform_pm ?
783 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
784}
785
786static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)
787{

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933 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
934 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
935 } else {
936 dev->current_state = state;
937 }
938}
939
940/**
947 * pci_refresh_power_state - Refresh the given device's power state data
948 * @dev: Target PCI device.
949 *
950 * Ask the platform to refresh the devices power state information and invoke
951 * pci_update_current_state() to update its current PCI power state.
952 */
953void pci_refresh_power_state(struct pci_dev *dev)
954{
955 if (platform_pci_power_manageable(dev))
956 platform_pci_refresh_power_state(dev);
957
958 pci_update_current_state(dev, dev->current_state);
959}
960
961/**
962 * pci_power_up - Put the given device into D0 forcibly
963 * @dev: PCI device to power up
964 */
965void pci_power_up(struct pci_dev *dev)
966{
967 if (platform_pci_power_manageable(dev))
968 platform_pci_set_power_state(dev, PCI_D0);
969

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1020 * @dev: PCI device to handle.
1021 * @state: State to put the device into.
1022 */
1023static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
1024{
1025 if (state == PCI_D0) {
1026 pci_platform_power_transition(dev, PCI_D0);
1027 /*
941 * pci_power_up - Put the given device into D0 forcibly
942 * @dev: PCI device to power up
943 */
944void pci_power_up(struct pci_dev *dev)
945{
946 if (platform_pci_power_manageable(dev))
947 platform_pci_set_power_state(dev, PCI_D0);
948

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999 * @dev: PCI device to handle.
1000 * @state: State to put the device into.
1001 */
1002static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
1003{
1004 if (state == PCI_D0) {
1005 pci_platform_power_transition(dev, PCI_D0);
1006 /*
1028 * Mandatory power management transition delays are
1029 * handled in the PCIe portdrv resume hooks.
1007 * Mandatory power management transition delays, see
1008 * PCI Express Base Specification Revision 2.0 Section
1009 * 6.6.1: Conventional Reset. Do not delay for
1010 * devices powered on/off by corresponding bridge,
1011 * because have already delayed for the bridge.
1030 */
1031 if (dev->runtime_d3cold) {
1012 */
1013 if (dev->runtime_d3cold) {
1014 if (dev->d3cold_delay && !dev->imm_ready)
1015 msleep(dev->d3cold_delay);
1032 /*
1033 * When powering on a bridge from D3cold, the
1034 * whole hierarchy may be powered on into
1035 * D0uninitialized state, resume them to give
1036 * them a chance to suspend again
1037 */
1038 pci_wakeup_bus(dev->subordinate);
1039 }

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2076 bridge = pme_dev->dev->bus->self;
2077 /*
2078 * If bridge is in low power state, the
2079 * configuration space of subordinate devices
2080 * may be not accessible
2081 */
2082 if (bridge && bridge->current_state != PCI_D0)
2083 continue;
1016 /*
1017 * When powering on a bridge from D3cold, the
1018 * whole hierarchy may be powered on into
1019 * D0uninitialized state, resume them to give
1020 * them a chance to suspend again
1021 */
1022 pci_wakeup_bus(dev->subordinate);
1023 }

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2060 bridge = pme_dev->dev->bus->self;
2061 /*
2062 * If bridge is in low power state, the
2063 * configuration space of subordinate devices
2064 * may be not accessible
2065 */
2066 if (bridge && bridge->current_state != PCI_D0)
2067 continue;
2084 /*
2085 * If the device is in D3cold it should not be
2086 * polled either.
2087 */
2088 if (pme_dev->dev->current_state == PCI_D3cold)
2089 continue;
2090
2091 pci_pme_wakeup(pme_dev->dev, NULL);
2092 } else {
2093 list_del(&pme_dev->list);
2094 kfree(pme_dev);
2095 }
2096 }
2097 if (!list_empty(&pci_pme_list))
2098 queue_delayed_work(system_freezable_wq, &pci_pme_work,

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2477 if (bus->bridge)
2478 return device_can_wakeup(bus->bridge);
2479
2480 return false;
2481}
2482EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2483
2484/**
2068 pci_pme_wakeup(pme_dev->dev, NULL);
2069 } else {
2070 list_del(&pme_dev->list);
2071 kfree(pme_dev);
2072 }
2073 }
2074 if (!list_empty(&pci_pme_list))
2075 queue_delayed_work(system_freezable_wq, &pci_pme_work,

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2454 if (bus->bridge)
2455 return device_can_wakeup(bus->bridge);
2456
2457 return false;
2458}
2459EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2460
2461/**
2485 * pci_dev_need_resume - Check if it is necessary to resume the device.
2462 * pci_dev_keep_suspended - Check if the device can stay in the suspended state.
2486 * @pci_dev: Device to check.
2487 *
2463 * @pci_dev: Device to check.
2464 *
2488 * Return 'true' if the device is not runtime-suspended or it has to be
2465 * Return 'true' if the device is runtime-suspended, it doesn't have to be
2489 * reconfigured due to wakeup settings difference between system and runtime
2466 * reconfigured due to wakeup settings difference between system and runtime
2490 * suspend, or the current power state of it is not suitable for the upcoming
2491 * (system-wide) transition.
2467 * suspend and the current power state of it is suitable for the upcoming
2468 * (system) transition.
2469 *
2470 * If the device is not configured for system wakeup, disable PME for it before
2471 * returning 'true' to prevent it from waking up the system unnecessarily.
2492 */
2472 */
2493bool pci_dev_need_resume(struct pci_dev *pci_dev)
2473bool pci_dev_keep_suspended(struct pci_dev *pci_dev)
2494{
2495 struct device *dev = &pci_dev->dev;
2474{
2475 struct device *dev = &pci_dev->dev;
2496 pci_power_t target_state;
2476 bool wakeup = device_may_wakeup(dev);
2497
2477
2498 if (!pm_runtime_suspended(dev) || platform_pci_need_resume(pci_dev))
2499 return true;
2478 if (!pm_runtime_suspended(dev)
2479 || pci_target_state(pci_dev, wakeup) != pci_dev->current_state
2480 || platform_pci_need_resume(pci_dev))
2481 return false;
2500
2482
2501 target_state = pci_target_state(pci_dev, device_may_wakeup(dev));
2502
2503 /*
2483 /*
2504 * If the earlier platform check has not triggered, D3cold is just power
2505 * removal on top of D3hot, so no need to resume the device in that
2506 * case.
2484 * At this point the device is good to go unless it's been configured
2485 * to generate PME at the runtime suspend time, but it is not supposed
2486 * to wake up the system. In that case, simply disable PME for it
2487 * (it will have to be re-enabled on exit from system resume).
2488 *
2489 * If the device's power state is D3cold and the platform check above
2490 * hasn't triggered, the device's configuration is suitable and we don't
2491 * need to manipulate it at all.
2507 */
2492 */
2508 return target_state != pci_dev->current_state &&
2509 target_state != PCI_D3cold &&
2510 pci_dev->current_state != PCI_D3hot;
2511}
2512
2513/**
2514 * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
2515 * @pci_dev: Device to check.
2516 *
2517 * If the device is suspended and it is not configured for system wakeup,
2518 * disable PME for it to prevent it from waking up the system unnecessarily.
2519 *
2520 * Note that if the device's power state is D3cold and the platform check in
2521 * pci_dev_need_resume() has not triggered, the device's configuration need not
2522 * be changed.
2523 */
2524void pci_dev_adjust_pme(struct pci_dev *pci_dev)
2525{
2526 struct device *dev = &pci_dev->dev;
2527
2528 spin_lock_irq(&dev->power.lock);
2529
2493 spin_lock_irq(&dev->power.lock);
2494
2530 if (pm_runtime_suspended(dev) && !device_may_wakeup(dev) &&
2531 pci_dev->current_state < PCI_D3cold)
2495 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold &&
2496 !wakeup)
2532 __pci_pme_active(pci_dev, false);
2533
2534 spin_unlock_irq(&dev->power.lock);
2497 __pci_pme_active(pci_dev, false);
2498
2499 spin_unlock_irq(&dev->power.lock);
2500 return true;
2535}
2536
2537/**
2538 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2539 * @pci_dev: Device to handle.
2540 *
2541 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2542 * it might have been disabled during the prepare phase of system suspend if

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4530 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
4531 return -ENOTTY;
4532
4533 if (probe)
4534 return 0;
4535
4536 /*
4537 * Wait for Transaction Pending bit to clear. A word-aligned test
2501}
2502
2503/**
2504 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2505 * @pci_dev: Device to handle.
2506 *
2507 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2508 * it might have been disabled during the prepare phase of system suspend if

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4496 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
4497 return -ENOTTY;
4498
4499 if (probe)
4500 return 0;
4501
4502 /*
4503 * Wait for Transaction Pending bit to clear. A word-aligned test
4538 * is used, so we use the conrol offset rather than status and shift
4504 * is used, so we use the control offset rather than status and shift
4539 * the test bit to match.
4540 */
4541 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
4542 PCI_AF_STATUS_TP << 8))
4543 pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4544
4545 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
4546

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4597
4598 csr &= ~PCI_PM_CTRL_STATE_MASK;
4599 csr |= PCI_D0;
4600 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4601 pci_dev_d3_sleep(dev);
4602
4603 return pci_dev_wait(dev, "PM D3->D0", PCIE_RESET_READY_POLL_MS);
4604}
4505 * the test bit to match.
4506 */
4507 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
4508 PCI_AF_STATUS_TP << 8))
4509 pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4510
4511 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
4512

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4563
4564 csr &= ~PCI_PM_CTRL_STATE_MASK;
4565 csr |= PCI_D0;
4566 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4567 pci_dev_d3_sleep(dev);
4568
4569 return pci_dev_wait(dev, "PM D3->D0", PCIE_RESET_READY_POLL_MS);
4570}
4605
4606/**
4571/**
4607 * pcie_wait_for_link_delay - Wait until link is active or inactive
4572 * pcie_wait_for_link - Wait until link is active or inactive
4608 * @pdev: Bridge device
4609 * @active: waiting for active or inactive?
4573 * @pdev: Bridge device
4574 * @active: waiting for active or inactive?
4610 * @delay: Delay to wait after link has become active (in ms)
4611 *
4612 * Use this to wait till link becomes active or inactive.
4613 */
4575 *
4576 * Use this to wait till link becomes active or inactive.
4577 */
4614bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active, int delay)
4578bool pcie_wait_for_link(struct pci_dev *pdev, bool active)
4615{
4616 int timeout = 1000;
4617 bool ret;
4618 u16 lnk_status;
4619
4620 /*
4621 * Some controllers might not implement link active reporting. In this
4622 * case, we wait for 1000 + 100 ms.

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4643 if (ret == active)
4644 break;
4645 if (timeout <= 0)
4646 break;
4647 msleep(10);
4648 timeout -= 10;
4649 }
4650 if (active && ret)
4579{
4580 int timeout = 1000;
4581 bool ret;
4582 u16 lnk_status;
4583
4584 /*
4585 * Some controllers might not implement link active reporting. In this
4586 * case, we wait for 1000 + 100 ms.

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4607 if (ret == active)
4608 break;
4609 if (timeout <= 0)
4610 break;
4611 msleep(10);
4612 timeout -= 10;
4613 }
4614 if (active && ret)
4651 msleep(delay);
4615 msleep(100);
4652 else if (ret != active)
4653 pci_info(pdev, "Data Link Layer Link Active not %s in 1000 msec\n",
4654 active ? "set" : "cleared");
4655 return ret == active;
4656}
4657
4616 else if (ret != active)
4617 pci_info(pdev, "Data Link Layer Link Active not %s in 1000 msec\n",
4618 active ? "set" : "cleared");
4619 return ret == active;
4620}
4621
4658/**
4659 * pcie_wait_for_link - Wait until link is active or inactive
4660 * @pdev: Bridge device
4661 * @active: waiting for active or inactive?
4662 *
4663 * Use this to wait till link becomes active or inactive.
4664 */
4665bool pcie_wait_for_link(struct pci_dev *pdev, bool active)
4666{
4667 return pcie_wait_for_link_delay(pdev, active, 100);
4668}
4669
4670void pci_reset_secondary_bus(struct pci_dev *dev)
4671{
4672 u16 ctrl;
4673
4674 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
4675 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
4676 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4677

--- 1648 unchanged lines hidden --- 		4622void pci_reset_secondary_bus(struct pci_dev *dev)
4623{
4624 u16 ctrl;
4625
4626 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
4627 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
4628 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4629

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