| pci-aardvark.c (355a47ae7ebcf9d605aa809b259d380422e81b8d) | pci-aardvark.c (f6b6aefee70aa5261deec7feab80c249bf58397f) |
|---|---|
| 1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Driver for the Aardvark PCIe controller, used on Marvell Armada 4 * 3700. 5 * 6 * Copyright (C) 2016 Marvell 7 * 8 * Author: Hezi Shahmoon <hezi.shahmoon@marvell.com> --- 294 unchanged lines hidden (view full) --- 303 304 /* Disable All ISR0/1 Sources */ 305 reg = PCIE_ISR0_ALL_MASK; 306 reg &= ~PCIE_ISR0_MSI_INT_PENDING; 307 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); 308 309 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); 310 | 1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Driver for the Aardvark PCIe controller, used on Marvell Armada 4 * 3700. 5 * 6 * Copyright (C) 2016 Marvell 7 * 8 * Author: Hezi Shahmoon <hezi.shahmoon@marvell.com> --- 294 unchanged lines hidden (view full) --- 303 304 /* Disable All ISR0/1 Sources */ 305 reg = PCIE_ISR0_ALL_MASK; 306 reg &= ~PCIE_ISR0_MSI_INT_PENDING; 307 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); 308 309 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); 310 |
| 311 /* Unmask all MSI's */ | 311 /* Unmask all MSIs */ |
| 312 advk_writel(pcie, 0, PCIE_MSI_MASK_REG); 313 314 /* Enable summary interrupt for GIC SPI source */ 315 reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK); 316 advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG); 317 318 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); 319 reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE; --- 730 unchanged lines hidden --- | 312 advk_writel(pcie, 0, PCIE_MSI_MASK_REG); 313 314 /* Enable summary interrupt for GIC SPI source */ 315 reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK); 316 advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG); 317 318 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); 319 reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE; --- 730 unchanged lines hidden --- |