reg.h (2fb822f82a59db899ba7b3a615cb0ddbc8c04f0f) reg.h (76599a8d0b7d23b990d03dc5a0ceb450afd18391)
1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5#ifndef __RTW89_REG_H__
6#define __RTW89_REG_H__
7
8#define R_AX_SYS_WL_EFUSE_CTRL 0x000A

--- 3470 unchanged lines hidden (view full) ---

3479#define R_NDP_BRK1 0xDA4
3480#define B_NDP_RU_BRK BIT(0)
3481#define R_BRK_ASYNC_RST_EN_1 0x0DC0
3482#define R_BRK_ASYNC_RST_EN_2 0x0DC4
3483#define R_BRK_ASYNC_RST_EN_3 0x0DC8
3484#define R_S0_HW_SI_DIS 0x1200
3485#define B_S0_HW_SI_DIS_W_R_TRIG GENMASK(30, 28)
3486#define R_P0_RXCK 0x12A0
1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5#ifndef __RTW89_REG_H__
6#define __RTW89_REG_H__
7
8#define R_AX_SYS_WL_EFUSE_CTRL 0x000A

--- 3470 unchanged lines hidden (view full) ---

3479#define R_NDP_BRK1 0xDA4
3480#define B_NDP_RU_BRK BIT(0)
3481#define R_BRK_ASYNC_RST_EN_1 0x0DC0
3482#define R_BRK_ASYNC_RST_EN_2 0x0DC4
3483#define R_BRK_ASYNC_RST_EN_3 0x0DC8
3484#define R_S0_HW_SI_DIS 0x1200
3485#define B_S0_HW_SI_DIS_W_R_TRIG GENMASK(30, 28)
3486#define R_P0_RXCK 0x12A0
3487#define B_P0_RXCK_VAL GENMASK(18, 16)
3488#define B_P0_RXCK_ON BIT(19)
3489#define B_P0_RXCK_BW3 BIT(30)
3487#define B_P0_RXCK_BW3 BIT(30)
3488#define B_P0_TXCK_ALL GENMASK(19, 12)
3489#define B_P0_RXCK_ON BIT(19)
3490#define B_P0_RXCK_VAL GENMASK(18, 16)
3491#define B_P0_TXCK_ON BIT(15)
3492#define B_P0_TXCK_VAL GENMASK(14, 12)
3490#define R_P0_NRBW 0x12B8
3491#define B_P0_NRBW_DBG BIT(30)
3492#define R_S0_RXDC 0x12D4
3493#define B_S0_RXDC_I GENMASK(25, 16)
3494#define B_S0_RXDC_Q GENMASK(31, 26)
3495#define R_S0_RXDC2 0x12D8
3496#define B_S0_RXDC2_SEL GENMASK(9, 8)
3497#define B_S0_RXDC2_AVG GENMASK(7, 6)

--- 532 unchanged lines hidden (view full) ---

4030#define B_IQKINF_FCOR BIT(0)
4031#define R_IQKCH 0x9FE4
4032#define B_IQKCH_CH GENMASK(15, 8)
4033#define B_IQKCH_BW GENMASK(7, 4)
4034#define B_IQKCH_BAND GENMASK(3, 0)
4035#define R_IQKINF2 0x9FE8
4036#define B_IQKINF2_FCNT GENMASK(23, 16)
4037#define B_IQKINF2_KCNT GENMASK(15, 8)
3493#define R_P0_NRBW 0x12B8
3494#define B_P0_NRBW_DBG BIT(30)
3495#define R_S0_RXDC 0x12D4
3496#define B_S0_RXDC_I GENMASK(25, 16)
3497#define B_S0_RXDC_Q GENMASK(31, 26)
3498#define R_S0_RXDC2 0x12D8
3499#define B_S0_RXDC2_SEL GENMASK(9, 8)
3500#define B_S0_RXDC2_AVG GENMASK(7, 6)

--- 532 unchanged lines hidden (view full) ---

4033#define B_IQKINF_FCOR BIT(0)
4034#define R_IQKCH 0x9FE4
4035#define B_IQKCH_CH GENMASK(15, 8)
4036#define B_IQKCH_BW GENMASK(7, 4)
4037#define B_IQKCH_BAND GENMASK(3, 0)
4038#define R_IQKINF2 0x9FE8
4039#define B_IQKINF2_FCNT GENMASK(23, 16)
4040#define B_IQKINF2_KCNT GENMASK(15, 8)
4038#define B_IQKINF2_NCTLV GENMAKS(7, 0)
4041#define B_IQKINF2_NCTLV GENMASK(7, 0)
4042#define R_DCOF0 0xC000
4043#define B_DCOF0_V GENMASK(4, 1)
4044#define R_DCOF1 0xC004
4045#define B_DCOF1_S BIT(0)
4046#define R_DCOF8 0xC020
4047#define B_DCOF8_V GENMASK(4, 1)
4048#define R_DACK_S0P0 0xC040
4049#define B_DACK_S0P0_OK BIT(31)
4050#define R_DACK_BIAS00 0xc048
4051#define B_DACK_BIAS00 GENMASK(11, 2)
4052#define R_DACK_S0P2 0xC05C
4053#define B_DACK_S0M0 GENMASK(31, 24)
4054#define B_DACK_S0P2_OK BIT(2)
4055#define R_DACK_DADCK00 0xC060
4056#define B_DACK_DADCK00 GENMASK(31, 24)
4057#define R_DACK_S0P1 0xC064
4058#define B_DACK_S0P1_OK BIT(31)
4059#define R_DACK_BIAS01 0xC06C
4060#define B_DACK_BIAS01 GENMASK(11, 2)
4061#define R_DACK_S0P3 0xC080
4062#define B_DACK_S0M1 GENMASK(31, 24)
4063#define B_DACK_S0P3_OK BIT(2)
4064#define R_DACK_DADCK01 0xC084
4065#define B_DACK_DADCK01 GENMASK(31, 24)
4066#define R_DRCK 0xC0C4
4067#define B_DRCK_IDLE BIT(9)
4068#define B_DRCK_EN BIT(6)
4069#define B_DRCK_VAL GENMASK(4, 0)
4070#define R_DRCK_RES 0xC0C8
4071#define B_DRCK_RES GENMASK(19, 15)
4072#define B_DRCK_POL BIT(3)
4039#define R_PATH0_SAMPL_DLY_T_V1 0xC0D4
4040#define B_PATH0_SAMPL_DLY_T_MSK_V1 GENMASK(27, 26)
4073#define R_PATH0_SAMPL_DLY_T_V1 0xC0D4
4074#define B_PATH0_SAMPL_DLY_T_MSK_V1 GENMASK(27, 26)
4075#define R_P0_CFCH_BW0 0xC0D4
4076#define B_P0_CFCH_BW0 GENMASK(27, 26)
4077#define R_P0_CFCH_BW1 0xC0D8
4078#define B_P0_CFCH_BW1 GENMASK(8, 5)
4079#define R_ADDCK0 0xC0F4
4080#define B_ADDCK0 GENMASK(9, 8)
4081#define B_ADDCK0_EN BIT(4)
4082#define B_ADDCK0_RST BIT(2)
4083#define R_ADDCK0_RL 0xC0F8
4084#define B_ADDCK0_RLS GENMASK(29, 28)
4085#define B_ADDCK0_RL1 GENMASK(27, 18)
4086#define B_ADDCK0_RL0 GENMASK(17, 8)
4087#define R_ADDCKR0 0xC0FC
4088#define B_ADDCKR0_A0 GENMASK(19, 10)
4089#define B_ADDCKR0_A1 GENMASK(9, 0)
4090#define R_DACK10 0xC100
4091#define B_DACK10 GENMASK(4, 1)
4092#define R_DACK1_K 0xc104
4093#define B_DACK1_EN BIT(0)
4094#define R_DACK11 0xC120
4095#define B_DACK11 GENMASK(4, 1)
4096#define R_DACK_S1P0 0xC140
4097#define B_DACK_S1P0_OK BIT(31)
4098#define R_DACK_BIAS10 0xC148
4099#define B_DACK_BIAS10 GENMASK(11, 2)
4100#define R_DACK10S 0xC15C
4101#define B_DACK10S GENMASK(31, 24)
4102#define R_DACK_S1P2 0xC15C
4103#define B_DACK_S1P2_OK BIT(2)
4104#define R_DACK_DADCK10 0xC160
4105#define B_DACK_DADCK10 GENMASK(31, 24)
4106#define R_DACK_S1P1 0xC164
4107#define B_DACK_S1P1_OK BIT(31)
4108#define R_DACK_BIAS11 0xC16C
4109#define B_DACK_BIAS11 GENMASK(11, 2)
4110#define R_DACK11S 0xC180
4111#define B_DACK11S GENMASK(31, 24)
4112#define R_DACK_S1P3 0xC180
4113#define B_DACK_S1P3_OK BIT(2)
4114#define R_DACK_DADCK11 0xC184
4115#define B_DACK_DADCK11 GENMASK(31, 24)
4041#define R_PATH1_SAMPL_DLY_T_V1 0xC1D4
4042#define B_PATH1_SAMPL_DLY_T_MSK_V1 GENMASK(27, 26)
4043#define R_PATH0_BW_SEL_V1 0xC0D8
4044#define B_PATH0_BW_SEL_MSK_V1 GENMASK(8, 5)
4045#define R_PATH1_BW_SEL_V1 0xC1D8
4046#define B_PATH1_BW_SEL_MSK_V1 GENMASK(8, 5)
4116#define R_PATH1_SAMPL_DLY_T_V1 0xC1D4
4117#define B_PATH1_SAMPL_DLY_T_MSK_V1 GENMASK(27, 26)
4118#define R_PATH0_BW_SEL_V1 0xC0D8
4119#define B_PATH0_BW_SEL_MSK_V1 GENMASK(8, 5)
4120#define R_PATH1_BW_SEL_V1 0xC1D8
4121#define B_PATH1_BW_SEL_MSK_V1 GENMASK(8, 5)
4047#define R_P0_CFCH_BW0 0xC0D4
4048#define B_P0_CFCH_BW0 GENMASK(27, 26)
4049#define R_P0_CFCH_BW1 0xC0D8
4050#define B_P0_CFCH_BW1 GENMASK(8, 5)
4122#define R_ADDCK1 0xC1F4
4123#define B_ADDCK1 GENMASK(9, 8)
4124#define B_ADDCK1_EN BIT(4)
4125#define B_ADDCK1_RST BIT(2)
4126#define R_ADDCK1_RL 0xC1F8
4127#define B_ADDCK1_RLS GENMASK(29, 28)
4128#define B_ADDCK1_RL1 GENMASK(27, 18)
4129#define B_ADDCK1_RL0 GENMASK(17, 8)
4130#define R_ADDCKR1 0xC1fC
4131#define B_ADDCKR1_A0 GENMASK(19, 10)
4132#define B_ADDCKR1_A1 GENMASK(9, 0)
4051
4052/* WiFi CPU local domain */
4053#define R_AX_WDT_CTRL 0x0040
4054#define B_AX_WDT_EN BIT(31)
4055#define B_AX_WDT_OPT_RESET_PLATFORM_EN BIT(29)
4056#define B_AX_IO_HANG_IMR BIT(27)
4057#define B_AX_IO_HANG_CMAC_RDATA_EN BIT(26)
4058#define B_AX_IO_HANG_DMAC_EN BIT(25)
4059#define B_AX_WDT_CLR BIT(16)
4060#define B_AX_WDT_COUNT_MASK GENMASK(15, 0)
4061#define WDT_CTRL_ALL_DIS 0
4062
4063#define R_AX_WDT_STATUS 0x0044
4064#define B_AX_FS_WDT_INT BIT(8)
4065#define B_AX_FS_WDT_INT_MSK BIT(0)
4066
4067#endif
4133
4134/* WiFi CPU local domain */
4135#define R_AX_WDT_CTRL 0x0040
4136#define B_AX_WDT_EN BIT(31)
4137#define B_AX_WDT_OPT_RESET_PLATFORM_EN BIT(29)
4138#define B_AX_IO_HANG_IMR BIT(27)
4139#define B_AX_IO_HANG_CMAC_RDATA_EN BIT(26)
4140#define B_AX_IO_HANG_DMAC_EN BIT(25)
4141#define B_AX_WDT_CLR BIT(16)
4142#define B_AX_WDT_COUNT_MASK GENMASK(15, 0)
4143#define WDT_CTRL_ALL_DIS 0
4144
4145#define R_AX_WDT_STATUS 0x0044
4146#define B_AX_FS_WDT_INT BIT(8)
4147#define B_AX_FS_WDT_INT_MSK BIT(0)
4148
4149#endif