phy.c (48ee4835b73c48590d05a54730dc8037ebd39d3b) phy.c (861e58c8fc6be0e1319525b5e9a27a0d2e776210)
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5#include "debug.h"
6#include "fw.h"
7#include "phy.h"
8#include "ps.h"

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563 }
564 break;
565 default:
566 break;
567 }
568
569 return txsc_idx;
570}
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5#include "debug.h"
6#include "fw.h"
7#include "phy.h"
8#include "ps.h"

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563 }
564 break;
565 default:
566 break;
567 }
568
569 return txsc_idx;
570}
571EXPORT_SYMBOL(rtw89_phy_get_txsc);
571
572u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
573 u32 addr, u32 mask)
574{
575 const struct rtw89_chip_info *chip = rtwdev->chip;
576 const u32 *base_addr = chip->rf_base_addr;
577 u32 val, direct_addr;
578

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967
968void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
969 u32 data, enum rtw89_phy_idx phy_idx)
970{
971 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
972 addr += rtw89_phy0_phy1_offset(rtwdev, addr);
973 rtw89_phy_write32_mask(rtwdev, addr, mask, data);
974}
572
573u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
574 u32 addr, u32 mask)
575{
576 const struct rtw89_chip_info *chip = rtwdev->chip;
577 const u32 *base_addr = chip->rf_base_addr;
578 u32 val, direct_addr;
579

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968
969void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
970 u32 data, enum rtw89_phy_idx phy_idx)
971{
972 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
973 addr += rtw89_phy0_phy1_offset(rtwdev, addr);
974 rtw89_phy_write32_mask(rtwdev, addr, mask, data);
975}
976EXPORT_SYMBOL(rtw89_phy_write32_idx);
975
976void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
977 u32 val)
978{
979 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0);
980
981 if (!rtwdev->dbcc_en)
982 return;

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990 const struct rtw89_reg3_def *reg3;
991 int i;
992
993 for (i = 0; i < tbl->size; i++) {
994 reg3 = &tbl->reg3[i];
995 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data);
996 }
997}
977
978void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
979 u32 val)
980{
981 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0);
982
983 if (!rtwdev->dbcc_en)
984 return;

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992 const struct rtw89_reg3_def *reg3;
993 int i;
994
995 for (i = 0; i < tbl->size; i++) {
996 reg3 = &tbl->reg3[i];
997 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data);
998 }
999}
1000EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl);
998
999const u8 rtw89_rs_idx_max[] = {
1000 [RTW89_RS_CCK] = RTW89_RATE_CCK_MAX,
1001 [RTW89_RS_OFDM] = RTW89_RATE_OFDM_MAX,
1002 [RTW89_RS_MCS] = RTW89_RATE_MCS_MAX,
1003 [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_MAX,
1004 [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_MAX,
1005};
1001
1002const u8 rtw89_rs_idx_max[] = {
1003 [RTW89_RS_CCK] = RTW89_RATE_CCK_MAX,
1004 [RTW89_RS_OFDM] = RTW89_RATE_OFDM_MAX,
1005 [RTW89_RS_MCS] = RTW89_RATE_MCS_MAX,
1006 [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_MAX,
1007 [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_MAX,
1008};
1009EXPORT_SYMBOL(rtw89_rs_idx_max);
1006
1007const u8 rtw89_rs_nss_max[] = {
1008 [RTW89_RS_CCK] = 1,
1009 [RTW89_RS_OFDM] = 1,
1010 [RTW89_RS_MCS] = RTW89_NSS_MAX,
1011 [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_MAX,
1012 [RTW89_RS_OFFSET] = 1,
1013};
1010
1011const u8 rtw89_rs_nss_max[] = {
1012 [RTW89_RS_CCK] = 1,
1013 [RTW89_RS_OFDM] = 1,
1014 [RTW89_RS_MCS] = RTW89_NSS_MAX,
1015 [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_MAX,
1016 [RTW89_RS_OFFSET] = 1,
1017};
1018EXPORT_SYMBOL(rtw89_rs_nss_max);
1014
1015static const u8 _byr_of_rs[] = {
1016 [RTW89_RS_CCK] = offsetof(struct rtw89_txpwr_byrate, cck),
1017 [RTW89_RS_OFDM] = offsetof(struct rtw89_txpwr_byrate, ofdm),
1018 [RTW89_RS_MCS] = offsetof(struct rtw89_txpwr_byrate, mcs),
1019 [RTW89_RS_HEDCM] = offsetof(struct rtw89_txpwr_byrate, hedcm),
1020 [RTW89_RS_OFFSET] = offsetof(struct rtw89_txpwr_byrate, offset),
1021};

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1039 data = cfg->data;
1040
1041 for (i = 0; i < cfg->len; i++, data >>= 8) {
1042 idx = _byr_idx(cfg->rs, cfg->nss, (cfg->shf + i));
1043 byr[idx] = (s8)(data & 0xff);
1044 }
1045 }
1046}
1019
1020static const u8 _byr_of_rs[] = {
1021 [RTW89_RS_CCK] = offsetof(struct rtw89_txpwr_byrate, cck),
1022 [RTW89_RS_OFDM] = offsetof(struct rtw89_txpwr_byrate, ofdm),
1023 [RTW89_RS_MCS] = offsetof(struct rtw89_txpwr_byrate, mcs),
1024 [RTW89_RS_HEDCM] = offsetof(struct rtw89_txpwr_byrate, hedcm),
1025 [RTW89_RS_OFFSET] = offsetof(struct rtw89_txpwr_byrate, offset),
1026};

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1044 data = cfg->data;
1045
1046 for (i = 0; i < cfg->len; i++, data >>= 8) {
1047 idx = _byr_idx(cfg->rs, cfg->nss, (cfg->shf + i));
1048 byr[idx] = (s8)(data & 0xff);
1049 }
1050 }
1051}
1052EXPORT_SYMBOL(rtw89_phy_load_txpwr_byrate);
1047
1048#define _phy_txpwr_rf_to_mac(rtwdev, txpwr_rf) \
1049({ \
1050 const struct rtw89_chip_info *__c = (rtwdev)->chip; \
1051 (txpwr_rf) >> (__c->txpwr_factor_rf - __c->txpwr_factor_mac); \
1052})
1053
1054s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev,

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1069 return 0;
1070 }
1071
1072 byr = _byr_seek(rate_desc->rs, &rtwdev->byr[band]);
1073 idx = _byr_idx(rate_desc->rs, rate_desc->nss, rate_desc->idx);
1074
1075 return _phy_txpwr_rf_to_mac(rtwdev, byr[idx]);
1076}
1053
1054#define _phy_txpwr_rf_to_mac(rtwdev, txpwr_rf) \
1055({ \
1056 const struct rtw89_chip_info *__c = (rtwdev)->chip; \
1057 (txpwr_rf) >> (__c->txpwr_factor_rf - __c->txpwr_factor_mac); \
1058})
1059
1060s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev,

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1075 return 0;
1076 }
1077
1078 byr = _byr_seek(rate_desc->rs, &rtwdev->byr[band]);
1079 idx = _byr_idx(rate_desc->rs, rate_desc->nss, rate_desc->idx);
1080
1081 return _phy_txpwr_rf_to_mac(rtwdev, byr[idx]);
1082}
1083EXPORT_SYMBOL(rtw89_phy_read_txpwr_byrate);
1077
1078static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 channel)
1079{
1080 switch (channel) {
1081 case 1 ... 14:
1082 return channel - 1;
1083 case 36 ... 64:
1084 return (channel - 36) / 2;

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1119 return 0;
1120 }
1121
1122 lmt = _phy_txpwr_rf_to_mac(rtwdev, lmt);
1123 sar = rtw89_query_sar(rtwdev);
1124
1125 return min(lmt, sar);
1126}
1084
1085static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 channel)
1086{
1087 switch (channel) {
1088 case 1 ... 14:
1089 return channel - 1;
1090 case 36 ... 64:
1091 return (channel - 36) / 2;

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1126 return 0;
1127 }
1128
1129 lmt = _phy_txpwr_rf_to_mac(rtwdev, lmt);
1130 sar = rtw89_query_sar(rtwdev);
1131
1132 return min(lmt, sar);
1133}
1134EXPORT_SYMBOL(rtw89_phy_read_txpwr_limit);
1127
1128#define __fill_txpwr_limit_nonbf_bf(ptr, bw, ntx, rs, ch) \
1129 do { \
1130 u8 __i; \
1131 for (__i = 0; __i < RTW89_BF_NUM; __i++) \
1132 ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \
1133 bw, ntx, \
1134 rs, __i, \

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1217 case RTW89_CHANNEL_WIDTH_40:
1218 rtw89_phy_fill_txpwr_limit_40m(rtwdev, lmt, ntx, ch);
1219 break;
1220 case RTW89_CHANNEL_WIDTH_80:
1221 rtw89_phy_fill_txpwr_limit_80m(rtwdev, lmt, ntx, ch);
1222 break;
1223 }
1224}
1135
1136#define __fill_txpwr_limit_nonbf_bf(ptr, bw, ntx, rs, ch) \
1137 do { \
1138 u8 __i; \
1139 for (__i = 0; __i < RTW89_BF_NUM; __i++) \
1140 ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \
1141 bw, ntx, \
1142 rs, __i, \

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1225 case RTW89_CHANNEL_WIDTH_40:
1226 rtw89_phy_fill_txpwr_limit_40m(rtwdev, lmt, ntx, ch);
1227 break;
1228 case RTW89_CHANNEL_WIDTH_80:
1229 rtw89_phy_fill_txpwr_limit_80m(rtwdev, lmt, ntx, ch);
1230 break;
1231 }
1232}
1233EXPORT_SYMBOL(rtw89_phy_fill_txpwr_limit);
1225
1226static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev,
1227 u8 ru, u8 ntx, u8 ch)
1228{
1229 const struct rtw89_chip_info *chip = rtwdev->chip;
1230 u8 ch_idx = rtw89_channel_to_idx(rtwdev, ch);
1231 u8 band = rtwdev->hal.current_band_type;
1232 u8 regd = rtw89_regd_get(rtwdev, band);

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1335 case RTW89_CHANNEL_WIDTH_40:
1336 rtw89_phy_fill_txpwr_limit_ru_40m(rtwdev, lmt_ru, ntx, ch);
1337 break;
1338 case RTW89_CHANNEL_WIDTH_80:
1339 rtw89_phy_fill_txpwr_limit_ru_80m(rtwdev, lmt_ru, ntx, ch);
1340 break;
1341 }
1342}
1234
1235static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev,
1236 u8 ru, u8 ntx, u8 ch)
1237{
1238 const struct rtw89_chip_info *chip = rtwdev->chip;
1239 u8 ch_idx = rtw89_channel_to_idx(rtwdev, ch);
1240 u8 band = rtwdev->hal.current_band_type;
1241 u8 regd = rtw89_regd_get(rtwdev, band);

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1344 case RTW89_CHANNEL_WIDTH_40:
1345 rtw89_phy_fill_txpwr_limit_ru_40m(rtwdev, lmt_ru, ntx, ch);
1346 break;
1347 case RTW89_CHANNEL_WIDTH_80:
1348 rtw89_phy_fill_txpwr_limit_ru_80m(rtwdev, lmt_ru, ntx, ch);
1349 break;
1350 }
1351}
1352EXPORT_SYMBOL(rtw89_phy_fill_txpwr_limit_ru);
1343
1344struct rtw89_phy_iter_ra_data {
1345 struct rtw89_dev *rtwdev;
1346 struct sk_buff *c2h;
1347};
1348
1349static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta)
1350{

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1354struct rtw89_phy_iter_ra_data {
1355 struct rtw89_dev *rtwdev;
1356 struct sk_buff *c2h;
1357};
1358
1359static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta)
1360{

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