mac.c (48ee4835b73c48590d05a54730dc8037ebd39d3b) mac.c (861e58c8fc6be0e1319525b5e9a27a0d2e776210)
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5#include "cam.h"
6#include "debug.h"
7#include "fw.h"
8#include "mac.h"

--- 467 unchanged lines hidden (view full) ---

476
477 rtw89_write32(rtwdev, R_AX_HALT_H2C, err);
478 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER);
479
480 return 0;
481}
482EXPORT_SYMBOL(rtw89_mac_set_err_status);
483
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5#include "cam.h"
6#include "debug.h"
7#include "fw.h"
8#include "mac.h"

--- 467 unchanged lines hidden (view full) ---

476
477 rtw89_write32(rtwdev, R_AX_HALT_H2C, err);
478 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER);
479
480 return 0;
481}
482EXPORT_SYMBOL(rtw89_mac_set_err_status);
483
484const struct rtw89_hfc_prec_cfg rtw_hfc_preccfg_pcie = {
484const struct rtw89_hfc_prec_cfg rtw89_hfc_preccfg_pcie = {
485 2, 40, 0, 0, 1, 0, 0, 0
486};
485 2, 40, 0, 0, 1, 0, 0, 0
486};
487EXPORT_SYMBOL(rtw89_hfc_preccfg_pcie);
487
488static int hfc_reset_param(struct rtw89_dev *rtwdev)
489{
490 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
491 struct rtw89_hfc_param_ini param_ini = {NULL};
492 u8 qta_mode = rtwdev->mac.dle_info.qta_mode;
493
494 switch (rtwdev->hci.type) {

--- 636 unchanged lines hidden (view full) ---

1131 ret = chip_func_en(rtwdev);
1132 if (ret)
1133 return ret;
1134
1135 return ret;
1136}
1137
1138/* PCIE 64 */
488
489static int hfc_reset_param(struct rtw89_dev *rtwdev)
490{
491 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
492 struct rtw89_hfc_param_ini param_ini = {NULL};
493 u8 qta_mode = rtwdev->mac.dle_info.qta_mode;
494
495 switch (rtwdev->hci.type) {

--- 636 unchanged lines hidden (view full) ---

1132 ret = chip_func_en(rtwdev);
1133 if (ret)
1134 return ret;
1135
1136 return ret;
1137}
1138
1139/* PCIE 64 */
1139const struct rtw89_dle_size wde_size0 = {
1140const struct rtw89_dle_size rtw89_wde_size0 = {
1140 RTW89_WDE_PG_64, 4095, 1,
1141};
1141 RTW89_WDE_PG_64, 4095, 1,
1142};
1143EXPORT_SYMBOL(rtw89_wde_size0);
1142
1143/* DLFW */
1144
1145/* DLFW */
1144const struct rtw89_dle_size wde_size4 = {
1146const struct rtw89_dle_size rtw89_wde_size4 = {
1145 RTW89_WDE_PG_64, 0, 4096,
1146};
1147 RTW89_WDE_PG_64, 0, 4096,
1148};
1149EXPORT_SYMBOL(rtw89_wde_size4);
1147
1148/* PCIE */
1150
1151/* PCIE */
1149const struct rtw89_dle_size ple_size0 = {
1152const struct rtw89_dle_size rtw89_ple_size0 = {
1150 RTW89_PLE_PG_128, 1520, 16,
1151};
1153 RTW89_PLE_PG_128, 1520, 16,
1154};
1155EXPORT_SYMBOL(rtw89_ple_size0);
1152
1153/* DLFW */
1156
1157/* DLFW */
1154const struct rtw89_dle_size ple_size4 = {
1158const struct rtw89_dle_size rtw89_ple_size4 = {
1155 RTW89_PLE_PG_128, 64, 1472,
1156};
1159 RTW89_PLE_PG_128, 64, 1472,
1160};
1161EXPORT_SYMBOL(rtw89_ple_size4);
1157
1158/* PCIE 64 */
1162
1163/* PCIE 64 */
1159const struct rtw89_wde_quota wde_qt0 = {
1164const struct rtw89_wde_quota rtw89_wde_qt0 = {
1160 3792, 196, 0, 107,
1161};
1165 3792, 196, 0, 107,
1166};
1167EXPORT_SYMBOL(rtw89_wde_qt0);
1162
1163/* DLFW */
1168
1169/* DLFW */
1164const struct rtw89_wde_quota wde_qt4 = {
1170const struct rtw89_wde_quota rtw89_wde_qt4 = {
1165 0, 0, 0, 0,
1166};
1171 0, 0, 0, 0,
1172};
1173EXPORT_SYMBOL(rtw89_wde_qt4);
1167
1168/* PCIE SCC */
1174
1175/* PCIE SCC */
1169const struct rtw89_ple_quota ple_qt4 = {
1176const struct rtw89_ple_quota rtw89_ple_qt4 = {
1170 264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,
1171};
1177 264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,
1178};
1179EXPORT_SYMBOL(rtw89_ple_qt4);
1172
1173/* PCIE SCC */
1180
1181/* PCIE SCC */
1174const struct rtw89_ple_quota ple_qt5 = {
1182const struct rtw89_ple_quota rtw89_ple_qt5 = {
1175 264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,
1176};
1183 264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,
1184};
1185EXPORT_SYMBOL(rtw89_ple_qt5);
1177
1178/* DLFW */
1186
1187/* DLFW */
1179const struct rtw89_ple_quota ple_qt13 = {
1188const struct rtw89_ple_quota rtw89_ple_qt13 = {
1180 0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0
1181};
1189 0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0
1190};
1191EXPORT_SYMBOL(rtw89_ple_qt13);
1182
1183static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev,
1184 enum rtw89_qta_mode mode)
1185{
1186 struct rtw89_mac_info *mac = &rtwdev->mac;
1187 const struct rtw89_dle_mem *cfg;
1188
1189 cfg = &rtwdev->chip->dle_mem[mode];

--- 921 unchanged lines hidden (view full) ---

2111 return ret;
2112 break;
2113 default:
2114 return 0;
2115 }
2116
2117 return 0;
2118}
1192
1193static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev,
1194 enum rtw89_qta_mode mode)
1195{
1196 struct rtw89_mac_info *mac = &rtwdev->mac;
1197 const struct rtw89_dle_mem *cfg;
1198
1199 cfg = &rtwdev->chip->dle_mem[mode];

--- 921 unchanged lines hidden (view full) ---

2121 return ret;
2122 break;
2123 default:
2124 return 0;
2125 }
2126
2127 return 0;
2128}
2129EXPORT_SYMBOL(rtw89_mac_stop_sch_tx);
2119
2120int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u16 tx_en)
2121{
2122 int ret;
2123
2124 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, 0xffff);
2125 if (ret)
2126 return ret;
2127
2128 return 0;
2129}
2130
2131int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u16 tx_en)
2132{
2133 int ret;
2134
2135 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, 0xffff);
2136 if (ret)
2137 return ret;
2138
2139 return 0;
2140}
2141EXPORT_SYMBOL(rtw89_mac_resume_sch_tx);
2130
2131static u16 rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len,
2132 bool wd)
2133{
2134 u32 val, reg;
2135 int ret;
2136
2137 reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ;

--- 1049 unchanged lines hidden (view full) ---

3187 return true;
3188
3189error:
3190 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n",
3191 addr, phy_idx);
3192
3193 return false;
3194}
2142
2143static u16 rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len,
2144 bool wd)
2145{
2146 u32 val, reg;
2147 int ret;
2148
2149 reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ;

--- 1049 unchanged lines hidden (view full) ---

3199 return true;
3200
3201error:
3202 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n",
3203 addr, phy_idx);
3204
3205 return false;
3206}
3207EXPORT_SYMBOL(rtw89_mac_get_txpwr_cr);
3195
3196int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)
3197{
3198 u32 reg = rtw89_mac_reg_by_idx(R_AX_PPDU_STAT, mac_idx);
3199 int ret = 0;
3200
3201 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
3202 if (ret)

--- 8 unchanged lines hidden (view full) ---

3211 B_AX_APP_MAC_INFO_RPT |
3212 B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT |
3213 B_AX_PPDU_STAT_RPT_CRC32);
3214 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK,
3215 RTW89_PRPT_DEST_HOST);
3216
3217 return ret;
3218}
3208
3209int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)
3210{
3211 u32 reg = rtw89_mac_reg_by_idx(R_AX_PPDU_STAT, mac_idx);
3212 int ret = 0;
3213
3214 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
3215 if (ret)

--- 8 unchanged lines hidden (view full) ---

3224 B_AX_APP_MAC_INFO_RPT |
3225 B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT |
3226 B_AX_PPDU_STAT_RPT_CRC32);
3227 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK,
3228 RTW89_PRPT_DEST_HOST);
3229
3230 return ret;
3231}
3232EXPORT_SYMBOL(rtw89_mac_cfg_ppdu_status);
3219
3220void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx)
3221{
3222#define MAC_AX_TIME_TH_SH 5
3223#define MAC_AX_LEN_TH_SH 4
3224#define MAC_AX_TIME_TH_MAX 255
3225#define MAC_AX_LEN_TH_MAX 255
3226#define MAC_AX_TIME_TH_DEF 88

--- 117 unchanged lines hidden (view full) ---

3344 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val);
3345 break;
3346 default:
3347 return -EINVAL;
3348 }
3349
3350 return 0;
3351}
3233
3234void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx)
3235{
3236#define MAC_AX_TIME_TH_SH 5
3237#define MAC_AX_LEN_TH_SH 4
3238#define MAC_AX_TIME_TH_MAX 255
3239#define MAC_AX_LEN_TH_MAX 255
3240#define MAC_AX_TIME_TH_DEF 88

--- 117 unchanged lines hidden (view full) ---

3358 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val);
3359 break;
3360 default:
3361 return -EINVAL;
3362 }
3363
3364 return 0;
3365}
3366EXPORT_SYMBOL(rtw89_mac_coex_init);
3352
3353int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev,
3354 const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
3355{
3356 u32 val, ret;
3357
3358 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_1, &val);
3359 if (ret) {

--- 488 unchanged lines hidden --- 		3367
3368int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev,
3369 const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
3370{
3371 u32 val, ret;
3372
3373 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_1, &val);
3374 if (ret) {

--- 488 unchanged lines hidden ---