fw.h (57cafeb18f06d3f4eaea9145d3396fdb8c699acc) fw.h (5c152231c341f0ea00b3ebd64cf6718b10106dab)
1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5#ifndef __RTW89_FW_H__
6#define __RTW89_FW_H__
7
8#include "core.h"

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3163struct rtw89_c2h_ra_rpt {
3164 struct rtw89_c2h_hdr hdr;
3165 __le32 w2;
3166 __le32 w3;
3167} __packed;
3168
3169#define RTW89_C2H_RA_RPT_W2_MACID GENMASK(15, 0)
3170#define RTW89_C2H_RA_RPT_W2_RETRY_RATIO GENMASK(23, 16)
1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5#ifndef __RTW89_FW_H__
6#define __RTW89_FW_H__
7
8#include "core.h"

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3163struct rtw89_c2h_ra_rpt {
3164 struct rtw89_c2h_hdr hdr;
3165 __le32 w2;
3166 __le32 w3;
3167} __packed;
3168
3169#define RTW89_C2H_RA_RPT_W2_MACID GENMASK(15, 0)
3170#define RTW89_C2H_RA_RPT_W2_RETRY_RATIO GENMASK(23, 16)
3171#define RTW89_C2H_RA_RPT_W2_MCSNSS_B7 BIT(31)
3171#define RTW89_C2H_RA_RPT_W3_MCSNSS GENMASK(6, 0)
3172#define RTW89_C2H_RA_RPT_W3_MD_SEL GENMASK(9, 8)
3173#define RTW89_C2H_RA_RPT_W3_GILTF GENMASK(12, 10)
3174#define RTW89_C2H_RA_RPT_W3_BW GENMASK(14, 13)
3172#define RTW89_C2H_RA_RPT_W3_MCSNSS GENMASK(6, 0)
3173#define RTW89_C2H_RA_RPT_W3_MD_SEL GENMASK(9, 8)
3174#define RTW89_C2H_RA_RPT_W3_GILTF GENMASK(12, 10)
3175#define RTW89_C2H_RA_RPT_W3_BW GENMASK(14, 13)
3176#define RTW89_C2H_RA_RPT_W3_MD_SEL_B2 BIT(15)
3177#define RTW89_C2H_RA_RPT_W3_BW_B2 BIT(16)
3175
3178
3176/* VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS
3177 * HT-new: [6:5]: NA, [4:0]: MCS
3179/* For WiFi 6 chips:
3180 * VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS
3181 * HT-new: [6:5]: NA, [4:0]: MCS
3182 * For WiFi 7 chips (V1):
3183 * HT, VHT, HE, EHT: [7:5]: NSS, [4:0]: MCS
3178 */
3179#define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4)
3180#define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0)
3184 */
3185#define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4)
3186#define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0)
3187#define RTW89_RA_RATE_MASK_NSS_V1 GENMASK(7, 5)
3188#define RTW89_RA_RATE_MASK_MCS_V1 GENMASK(4, 0)
3181#define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0)
3182#define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \
3183 FIELD_PREP(GENMASK(2, 0), mcs))
3184
3185#define RTW89_GET_MAC_C2H_PKTOFLD_ID(c2h) \
3186 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3187#define RTW89_GET_MAC_C2H_PKTOFLD_OP(c2h) \
3188 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(10, 8))

--- 462 unchanged lines hidden --- 		3189#define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0)
3190#define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \
3191 FIELD_PREP(GENMASK(2, 0), mcs))
3192
3193#define RTW89_GET_MAC_C2H_PKTOFLD_ID(c2h) \
3194 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3195#define RTW89_GET_MAC_C2H_PKTOFLD_OP(c2h) \
3196 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(10, 8))

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