| reg.h (7ae9fb1b7ecbb5d85d07857943f677fd1a559b18) | reg.h (65371a3f14e73979958aea0db1e3bb456a296149) |
|---|---|
| 1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2/* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5#ifndef __RTW_REG_DEF_H__ 6#define __RTW_REG_DEF_H__ 7 8#define REG_SYS_FUNC_EN 0x0002 --- 73 unchanged lines hidden (view full) --- 82#define REG_WL_BT_PWR_CTRL 0x0068 83#define BIT_BT_FUNC_EN BIT(18) 84#define BIT_BT_DIG_CLK_EN BIT(8) 85#define REG_SYS_SDIO_CTRL 0x0070 86#define BIT_DBG_GNT_WL_BT BIT(27) 87#define BIT_LTE_MUX_CTRL_PATH BIT(26) 88#define REG_HCI_OPT_CTRL 0x0074 89#define BIT_USB_SUS_DIS BIT(8) | 1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2/* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5#ifndef __RTW_REG_DEF_H__ 6#define __RTW_REG_DEF_H__ 7 8#define REG_SYS_FUNC_EN 0x0002 --- 73 unchanged lines hidden (view full) --- 82#define REG_WL_BT_PWR_CTRL 0x0068 83#define BIT_BT_FUNC_EN BIT(18) 84#define BIT_BT_DIG_CLK_EN BIT(8) 85#define REG_SYS_SDIO_CTRL 0x0070 86#define BIT_DBG_GNT_WL_BT BIT(27) 87#define BIT_LTE_MUX_CTRL_PATH BIT(26) 88#define REG_HCI_OPT_CTRL 0x0074 89#define BIT_USB_SUS_DIS BIT(8) |
| 90#define BIT_SDIO_PAD_E5 BIT(18) |
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| 90 91#define REG_AFE_CTRL_4 0x0078 92#define BIT_CK320M_AFE_EN BIT(4) 93#define BIT_EN_SYN BIT(15) 94 95#define REG_LDO_SWR_CTRL 0x007C 96#define LDO_SEL 0xC3 97#define SPS_SEL 0x83 --- 82 unchanged lines hidden (view full) --- 180#define BIT_TXDMA_VOQ_MAP(x) \ 181 (((x) & BIT_MASK_TXDMA_VOQ_MAP) << BIT_SHIFT_TXDMA_VOQ_MAP) 182#define BIT_SHIFT_TXDMA_VIQ_MAP 6 183#define BIT_MASK_TXDMA_VIQ_MAP 0x3 184#define BIT_TXDMA_VIQ_MAP(x) \ 185 (((x) & BIT_MASK_TXDMA_VIQ_MAP) << BIT_SHIFT_TXDMA_VIQ_MAP) 186#define REG_TXDMA_PQ_MAP 0x010C 187#define BIT_RXDMA_ARBBW_EN BIT(0) | 91 92#define REG_AFE_CTRL_4 0x0078 93#define BIT_CK320M_AFE_EN BIT(4) 94#define BIT_EN_SYN BIT(15) 95 96#define REG_LDO_SWR_CTRL 0x007C 97#define LDO_SEL 0xC3 98#define SPS_SEL 0x83 --- 82 unchanged lines hidden (view full) --- 181#define BIT_TXDMA_VOQ_MAP(x) \ 182 (((x) & BIT_MASK_TXDMA_VOQ_MAP) << BIT_SHIFT_TXDMA_VOQ_MAP) 183#define BIT_SHIFT_TXDMA_VIQ_MAP 6 184#define BIT_MASK_TXDMA_VIQ_MAP 0x3 185#define BIT_TXDMA_VIQ_MAP(x) \ 186 (((x) & BIT_MASK_TXDMA_VIQ_MAP) << BIT_SHIFT_TXDMA_VIQ_MAP) 187#define REG_TXDMA_PQ_MAP 0x010C 188#define BIT_RXDMA_ARBBW_EN BIT(0) |
| 189#define BIT_RXSHFT_EN BIT(1) 190#define BIT_RXDMA_AGG_EN BIT(2) 191#define BIT_TXDMA_BW_EN BIT(3) |
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| 188#define BIT_SHIFT_TXDMA_BEQ_MAP 8 189#define BIT_MASK_TXDMA_BEQ_MAP 0x3 190#define BIT_TXDMA_BEQ_MAP(x) \ 191 (((x) & BIT_MASK_TXDMA_BEQ_MAP) << BIT_SHIFT_TXDMA_BEQ_MAP) 192#define BIT_SHIFT_TXDMA_BKQ_MAP 10 193#define BIT_MASK_TXDMA_BKQ_MAP 0x3 194#define BIT_TXDMA_BKQ_MAP(x) \ 195 (((x) & BIT_MASK_TXDMA_BKQ_MAP) << BIT_SHIFT_TXDMA_BKQ_MAP) --- 82 unchanged lines hidden (view full) --- 278#define REG_FIFOPAGE_INFO_2 0x0234 279#define REG_FIFOPAGE_INFO_3 0x0238 280#define REG_FIFOPAGE_INFO_4 0x023C 281#define REG_FIFOPAGE_INFO_5 0x0240 282#define REG_H2C_HEAD 0x0244 283#define REG_H2C_TAIL 0x0248 284#define REG_H2C_READ_ADDR 0x024C 285#define REG_H2C_INFO 0x0254 | 192#define BIT_SHIFT_TXDMA_BEQ_MAP 8 193#define BIT_MASK_TXDMA_BEQ_MAP 0x3 194#define BIT_TXDMA_BEQ_MAP(x) \ 195 (((x) & BIT_MASK_TXDMA_BEQ_MAP) << BIT_SHIFT_TXDMA_BEQ_MAP) 196#define BIT_SHIFT_TXDMA_BKQ_MAP 10 197#define BIT_MASK_TXDMA_BKQ_MAP 0x3 198#define BIT_TXDMA_BKQ_MAP(x) \ 199 (((x) & BIT_MASK_TXDMA_BKQ_MAP) << BIT_SHIFT_TXDMA_BKQ_MAP) --- 82 unchanged lines hidden (view full) --- 282#define REG_FIFOPAGE_INFO_2 0x0234 283#define REG_FIFOPAGE_INFO_3 0x0238 284#define REG_FIFOPAGE_INFO_4 0x023C 285#define REG_FIFOPAGE_INFO_5 0x0240 286#define REG_H2C_HEAD 0x0244 287#define REG_H2C_TAIL 0x0248 288#define REG_H2C_READ_ADDR 0x024C 289#define REG_H2C_INFO 0x0254 |
| 290#define REG_RXDMA_AGG_PG_TH 0x0280 291#define BIT_RXDMA_AGG_PG_TH GENMASK(7, 0) 292#define BIT_DMA_AGG_TO_V1 GENMASK(15, 8) 293#define BIT_EN_PRE_CALC BIT(29) |
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| 286#define REG_RXPKT_NUM 0x0284 287#define BIT_RXDMA_REQ BIT(19) 288#define BIT_RW_RELEASE BIT(18) 289#define BIT_RXDMA_IDLE BIT(17) | 294#define REG_RXPKT_NUM 0x0284 295#define BIT_RXDMA_REQ BIT(19) 296#define BIT_RW_RELEASE BIT(18) 297#define BIT_RXDMA_IDLE BIT(17) |
| 298#define REG_RXDMA_STATUS 0x0288 299#define REG_RXDMA_DPR 0x028C 300#define REG_RXDMA_MODE 0x0290 301#define BIT_DMA_MODE BIT(1) |
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| 290#define REG_RXPKTNUM 0x02B0 291 292#define REG_INT_MIG 0x0304 293#define REG_HCI_MIX_CFG 0x03FC 294#define BIT_PCIE_EMAC_PDN_AUX_TO_FAST_CLK BIT(26) 295 296#define REG_BCNQ_INFO 0x0418 297#define BIT_MGQ_CPU_EMPTY BIT(24) --- 394 unchanged lines hidden --- | 302#define REG_RXPKTNUM 0x02B0 303 304#define REG_INT_MIG 0x0304 305#define REG_HCI_MIX_CFG 0x03FC 306#define BIT_PCIE_EMAC_PDN_AUX_TO_FAST_CLK BIT(26) 307 308#define REG_BCNQ_INFO 0x0418 309#define BIT_MGQ_CPU_EMPTY BIT(24) --- 394 unchanged lines hidden --- |