phy.c (4353dd3b70783ebbc83fcf12d9c0af3fbab0223b) phy.c (fc637a860a825e934886498874f9f8372798a462)
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5#include <linux/bcd.h>
6
7#include "main.h"
8#include "reg.h"

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135 dm_info->igi_history[0] = rtw_read32_mask(rtwdev, addr, mask);
136 rtw_phy_cck_pd_init(rtwdev);
137}
138
139void rtw_phy_dig_write(struct rtw_dev *rtwdev, u8 igi)
140{
141 struct rtw_chip_info *chip = rtwdev->chip;
142 struct rtw_hal *hal = &rtwdev->hal;
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5#include <linux/bcd.h>
6
7#include "main.h"
8#include "reg.h"

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135 dm_info->igi_history[0] = rtw_read32_mask(rtwdev, addr, mask);
136 rtw_phy_cck_pd_init(rtwdev);
137}
138
139void rtw_phy_dig_write(struct rtw_dev *rtwdev, u8 igi)
140{
141 struct rtw_chip_info *chip = rtwdev->chip;
142 struct rtw_hal *hal = &rtwdev->hal;
143 const struct rtw_hw_reg *dig_cck = &chip->dig_cck[0];
143 u32 addr, mask;
144 u8 path;
145
144 u32 addr, mask;
145 u8 path;
146
147 if (dig_cck)
148 rtw_write32_mask(rtwdev, dig_cck->addr, dig_cck->mask, igi >> 1);
149
146 for (path = 0; path < hal->rf_path_num; path++) {
147 addr = chip->dig[path].addr;
148 mask = chip->dig[path].mask;
149 rtw_write32_mask(rtwdev, addr, mask, igi);
150 }
151}
152
153static void rtw_phy_stat_false_alarm(struct rtw_dev *rtwdev)

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674u32 rtw_phy_read_rf(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
675 u32 addr, u32 mask)
676{
677 struct rtw_hal *hal = &rtwdev->hal;
678 struct rtw_chip_info *chip = rtwdev->chip;
679 const u32 *base_addr = chip->rf_base_addr;
680 u32 val, direct_addr;
681
150 for (path = 0; path < hal->rf_path_num; path++) {
151 addr = chip->dig[path].addr;
152 mask = chip->dig[path].mask;
153 rtw_write32_mask(rtwdev, addr, mask, igi);
154 }
155}
156
157static void rtw_phy_stat_false_alarm(struct rtw_dev *rtwdev)

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678u32 rtw_phy_read_rf(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
679 u32 addr, u32 mask)
680{
681 struct rtw_hal *hal = &rtwdev->hal;
682 struct rtw_chip_info *chip = rtwdev->chip;
683 const u32 *base_addr = chip->rf_base_addr;
684 u32 val, direct_addr;
685
682 if (rf_path >= hal->rf_path_num) {
686 if (rf_path >= hal->rf_phy_num) {
683 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
684 return INV_RF_DATA;
685 }
686
687 addr &= 0xff;
688 direct_addr = base_addr[rf_path] + (addr << 2);
689 mask &= RFREG_MASK;
690
691 val = rtw_read32_mask(rtwdev, direct_addr, mask);
692
693 return val;
694}
695
687 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
688 return INV_RF_DATA;
689 }
690
691 addr &= 0xff;
692 direct_addr = base_addr[rf_path] + (addr << 2);
693 mask &= RFREG_MASK;
694
695 val = rtw_read32_mask(rtwdev, direct_addr, mask);
696
697 return val;
698}
699
700u32 rtw_phy_read_rf_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
701 u32 addr, u32 mask)
702{
703 struct rtw_hal *hal = &rtwdev->hal;
704 struct rtw_chip_info *chip = rtwdev->chip;
705 const struct rtw_rf_sipi_addr *rf_sipi_addr;
706 const struct rtw_rf_sipi_addr *rf_sipi_addr_a;
707 u32 val32;
708 u32 en_pi;
709 u32 r_addr;
710 u32 shift;
711
712 if (rf_path >= hal->rf_phy_num) {
713 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
714 return INV_RF_DATA;
715 }
716
717 if (!chip->rf_sipi_read_addr) {
718 rtw_err(rtwdev, "rf_sipi_read_addr isn't defined\n");
719 return INV_RF_DATA;
720 }
721
722 rf_sipi_addr = &chip->rf_sipi_read_addr[rf_path];
723 rf_sipi_addr_a = &chip->rf_sipi_read_addr[RF_PATH_A];
724
725 addr &= 0xff;
726
727 val32 = rtw_read32(rtwdev, rf_sipi_addr->hssi_2);
728 val32 = (val32 & ~LSSI_READ_ADDR_MASK) | (addr << 23);
729 rtw_write32(rtwdev, rf_sipi_addr->hssi_2, val32);
730
731 /* toggle read edge of path A */
732 val32 = rtw_read32(rtwdev, rf_sipi_addr_a->hssi_2);
733 rtw_write32(rtwdev, rf_sipi_addr_a->hssi_2, val32 & ~LSSI_READ_EDGE_MASK);
734 rtw_write32(rtwdev, rf_sipi_addr_a->hssi_2, val32 | LSSI_READ_EDGE_MASK);
735
736 udelay(120);
737
738 en_pi = rtw_read32_mask(rtwdev, rf_sipi_addr->hssi_1, BIT(8));
739 r_addr = en_pi ? rf_sipi_addr->lssi_read_pi : rf_sipi_addr->lssi_read;
740
741 val32 = rtw_read32_mask(rtwdev, r_addr, LSSI_READ_DATA_MASK);
742
743 shift = __ffs(mask);
744
745 return (val32 & mask) >> shift;
746}
747
696bool rtw_phy_write_rf_reg_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
697 u32 addr, u32 mask, u32 data)
698{
699 struct rtw_hal *hal = &rtwdev->hal;
700 struct rtw_chip_info *chip = rtwdev->chip;
701 u32 *sipi_addr = chip->rf_sipi_addr;
702 u32 data_and_addr;
703 u32 old_data = 0;
704 u32 shift;
705
748bool rtw_phy_write_rf_reg_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
749 u32 addr, u32 mask, u32 data)
750{
751 struct rtw_hal *hal = &rtwdev->hal;
752 struct rtw_chip_info *chip = rtwdev->chip;
753 u32 *sipi_addr = chip->rf_sipi_addr;
754 u32 data_and_addr;
755 u32 old_data = 0;
756 u32 shift;
757
706 if (rf_path >= hal->rf_path_num) {
758 if (rf_path >= hal->rf_phy_num) {
707 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
708 return false;
709 }
710
711 addr &= 0xff;
712 mask &= RFREG_MASK;
713
714 if (mask != RFREG_MASK) {
759 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
760 return false;
761 }
762
763 addr &= 0xff;
764 mask &= RFREG_MASK;
765
766 if (mask != RFREG_MASK) {
715 old_data = rtw_phy_read_rf(rtwdev, rf_path, addr, RFREG_MASK);
767 old_data = chip->ops->read_rf(rtwdev, rf_path, addr, RFREG_MASK);
716
717 if (old_data == INV_RF_DATA) {
718 rtw_err(rtwdev, "Write fail, rf is disabled\n");
719 return false;
720 }
721
722 shift = __ffs(mask);
723 data = ((old_data) & (~mask)) | (data << shift);

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735bool rtw_phy_write_rf_reg(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
736 u32 addr, u32 mask, u32 data)
737{
738 struct rtw_hal *hal = &rtwdev->hal;
739 struct rtw_chip_info *chip = rtwdev->chip;
740 const u32 *base_addr = chip->rf_base_addr;
741 u32 direct_addr;
742
768
769 if (old_data == INV_RF_DATA) {
770 rtw_err(rtwdev, "Write fail, rf is disabled\n");
771 return false;
772 }
773
774 shift = __ffs(mask);
775 data = ((old_data) & (~mask)) | (data << shift);

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787bool rtw_phy_write_rf_reg(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
788 u32 addr, u32 mask, u32 data)
789{
790 struct rtw_hal *hal = &rtwdev->hal;
791 struct rtw_chip_info *chip = rtwdev->chip;
792 const u32 *base_addr = chip->rf_base_addr;
793 u32 direct_addr;
794
743 if (rf_path >= hal->rf_path_num) {
795 if (rf_path >= hal->rf_phy_num) {
744 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
745 return false;
746 }
747
748 addr &= 0xff;
749 direct_addr = base_addr[rf_path] + (addr << 2);
750 mask &= RFREG_MASK;
751

--- 1332 unchanged lines hidden --- 		796 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
797 return false;
798 }
799
800 addr &= 0xff;
801 direct_addr = base_addr[rf_path] + (addr << 2);
802 mask &= RFREG_MASK;
803

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