wil6210.h (262345265e599fe5ccc75ba435147d17df04bfd6) wil6210.h (eb4c02155881696ee6abb090d554b765e41d46ed)
1/*
2 * Copyright (c) 2012-2017 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

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166 #define HW_MACHINE_BOOT_DONE (0x3fffffd)
167#define RGF_USER_USER_CPU_0 (0x8801e0)
168 #define BIT_USER_USER_CPU_MAN_RST BIT(1) /* user_cpu_man_rst */
169#define RGF_USER_MAC_CPU_0 (0x8801fc)
170 #define BIT_USER_MAC_CPU_MAN_RST BIT(1) /* mac_cpu_man_rst */
171#define RGF_USER_USER_SCRATCH_PAD (0x8802bc)
172#define RGF_USER_BL (0x880A3C) /* Boot Loader */
173#define RGF_USER_FW_REV_ID (0x880a8c) /* chip revision */
1/*
2 * Copyright (c) 2012-2017 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

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166 #define HW_MACHINE_BOOT_DONE (0x3fffffd)
167#define RGF_USER_USER_CPU_0 (0x8801e0)
168 #define BIT_USER_USER_CPU_MAN_RST BIT(1) /* user_cpu_man_rst */
169#define RGF_USER_MAC_CPU_0 (0x8801fc)
170 #define BIT_USER_MAC_CPU_MAN_RST BIT(1) /* mac_cpu_man_rst */
171#define RGF_USER_USER_SCRATCH_PAD (0x8802bc)
172#define RGF_USER_BL (0x880A3C) /* Boot Loader */
173#define RGF_USER_FW_REV_ID (0x880a8c) /* chip revision */
174#define RGF_USER_FW_CALIB_RESULT (0x880a90) /* b0-7:result
175 * b8-15:signature
176 */
177 #define CALIB_RESULT_SIGNATURE (0x11)
174#define RGF_USER_CLKS_CTL_0 (0x880abc)
175 #define BIT_USER_CLKS_CAR_AHB_SW_SEL BIT(1) /* ref clk/PLL */
176 #define BIT_USER_CLKS_RST_PWGD BIT(11) /* reset on "power good" */
177#define RGF_USER_CLKS_CTL_SW_RST_VEC_0 (0x880b04)
178#define RGF_USER_CLKS_CTL_SW_RST_VEC_1 (0x880b08)
179#define RGF_USER_CLKS_CTL_SW_RST_VEC_2 (0x880b0c)
180#define RGF_USER_CLKS_CTL_SW_RST_VEC_3 (0x880b10)
181#define RGF_USER_CLKS_CTL_SW_RST_MASK_0 (0x880b14)

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719 struct mutex p2p_wdev_mutex; /* protect @p2p_wdev and @scan_request */
720 struct wireless_dev *radio_wdev;
721
722 /* High Access Latency Policy voting */
723 struct wil_halp halp;
724
725 enum wmi_ps_profile_type ps_profile;
726
178#define RGF_USER_CLKS_CTL_0 (0x880abc)
179 #define BIT_USER_CLKS_CAR_AHB_SW_SEL BIT(1) /* ref clk/PLL */
180 #define BIT_USER_CLKS_RST_PWGD BIT(11) /* reset on "power good" */
181#define RGF_USER_CLKS_CTL_SW_RST_VEC_0 (0x880b04)
182#define RGF_USER_CLKS_CTL_SW_RST_VEC_1 (0x880b08)
183#define RGF_USER_CLKS_CTL_SW_RST_VEC_2 (0x880b0c)
184#define RGF_USER_CLKS_CTL_SW_RST_VEC_3 (0x880b10)
185#define RGF_USER_CLKS_CTL_SW_RST_MASK_0 (0x880b14)

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723 struct mutex p2p_wdev_mutex; /* protect @p2p_wdev and @scan_request */
724 struct wireless_dev *radio_wdev;
725
726 /* High Access Latency Policy voting */
727 struct wil_halp halp;
728
729 enum wmi_ps_profile_type ps_profile;
730
731 int fw_calib_result;
732
727#ifdef CONFIG_PM
728#ifdef CONFIG_PM_SLEEP
729 struct notifier_block pm_notify;
730#endif /* CONFIG_PM_SLEEP */
731#endif /* CONFIG_PM */
732
733 bool suspend_resp_rcvd;
734 bool suspend_resp_comp;

--- 272 unchanged lines hidden --- 		733#ifdef CONFIG_PM
734#ifdef CONFIG_PM_SLEEP
735 struct notifier_block pm_notify;
736#endif /* CONFIG_PM_SLEEP */
737#endif /* CONFIG_PM */
738
739 bool suspend_resp_rcvd;
740 bool suspend_resp_comp;

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