| hw.h (6288cf1e768ae73db5ddaaae54d85245cc1c2b56) | hw.h (85ee5122abbc1b5c5f3622e46942291a2f6f1261) |
|---|---|
| 1/* 2 * Shared Atheros AR9170 Header 3 * 4 * Register map, hardware-specific definitions 5 * 6 * Copyright 2008, Johannes Berg <johannes@sipsolutions.net> | 1/* 2 * Shared Atheros AR9170 Header 3 * 4 * Register map, hardware-specific definitions 5 * 6 * Copyright 2008, Johannes Berg <johannes@sipsolutions.net> |
| 7 * Copyright 2009, 2010, Christian Lamparter <chunkeey@googlemail.com> | 7 * Copyright 2009-2011 Christian Lamparter <chunkeey@googlemail.com> |
| 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- 336 unchanged lines hidden (view full) --- 352#define AR9170_DMA_TRIGGER_TXQ1 BIT(1) 353#define AR9170_DMA_TRIGGER_TXQ2 BIT(2) 354#define AR9170_DMA_TRIGGER_TXQ3 BIT(3) 355#define AR9170_DMA_TRIGGER_TXQ4 BIT(4) 356#define AR9170_DMA_TRIGGER_RXQ BIT(8) 357 358#define AR9170_MAC_REG_DMA_WLAN_STATUS (AR9170_MAC_REG_BASE + 0xd38) 359#define AR9170_MAC_REG_DMA_STATUS (AR9170_MAC_REG_BASE + 0xd3c) | 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- 336 unchanged lines hidden (view full) --- 352#define AR9170_DMA_TRIGGER_TXQ1 BIT(1) 353#define AR9170_DMA_TRIGGER_TXQ2 BIT(2) 354#define AR9170_DMA_TRIGGER_TXQ3 BIT(3) 355#define AR9170_DMA_TRIGGER_TXQ4 BIT(4) 356#define AR9170_DMA_TRIGGER_RXQ BIT(8) 357 358#define AR9170_MAC_REG_DMA_WLAN_STATUS (AR9170_MAC_REG_BASE + 0xd38) 359#define AR9170_MAC_REG_DMA_STATUS (AR9170_MAC_REG_BASE + 0xd3c) |
| 360#define AR9170_MAC_REG_DMA_TXQ_LAST_ADDR (AR9170_MAC_REG_BASE + 0xd40) 361#define AR9170_MAC_REG_DMA_TXQ0_LAST_ADDR (AR9170_MAC_REG_BASE + 0xd40) 362#define AR9170_MAC_REG_DMA_TXQ1_LAST_ADDR (AR9170_MAC_REG_BASE + 0xd44) 363#define AR9170_MAC_REG_DMA_TXQ2_LAST_ADDR (AR9170_MAC_REG_BASE + 0xd48) 364#define AR9170_MAC_REG_DMA_TXQ3_LAST_ADDR (AR9170_MAC_REG_BASE + 0xd4c) 365#define AR9170_MAC_REG_DMA_TXQ4_LAST_ADDR (AR9170_MAC_REG_BASE + 0xd50) 366#define AR9170_MAC_REG_DMA_TXQ0Q1_LEN (AR9170_MAC_REG_BASE + 0xd54) 367#define AR9170_MAC_REG_DMA_TXQ2Q3_LEN (AR9170_MAC_REG_BASE + 0xd58) 368#define AR9170_MAC_REG_DMA_TXQ4_LEN (AR9170_MAC_REG_BASE + 0xd5c) |
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| 360 | 369 |
| 370#define AR9170_MAC_REG_DMA_TXQX_LAST_ADDR (AR9170_MAC_REG_BASE + 0xd74) 371#define AR9170_MAC_REG_DMA_TXQX_FAIL_ADDR (AR9170_MAC_REG_BASE + 0xd78) |
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| 361#define AR9170_MAC_REG_TXRX_MPI (AR9170_MAC_REG_BASE + 0xd7c) 362#define AR9170_MAC_TXRX_MPI_TX_MPI_MASK 0x0000000f 363#define AR9170_MAC_TXRX_MPI_TX_TO_MASK 0x0000fff0 364#define AR9170_MAC_TXRX_MPI_RX_MPI_MASK 0x000f0000 365#define AR9170_MAC_TXRX_MPI_RX_TO_MASK 0xfff00000 366 367#define AR9170_MAC_REG_BCN_ADDR (AR9170_MAC_REG_BASE + 0xd84) 368#define AR9170_MAC_REG_BCN_LENGTH (AR9170_MAC_REG_BASE + 0xd88) --- 401 unchanged lines hidden --- | 372#define AR9170_MAC_REG_TXRX_MPI (AR9170_MAC_REG_BASE + 0xd7c) 373#define AR9170_MAC_TXRX_MPI_TX_MPI_MASK 0x0000000f 374#define AR9170_MAC_TXRX_MPI_TX_TO_MASK 0x0000fff0 375#define AR9170_MAC_TXRX_MPI_RX_MPI_MASK 0x000f0000 376#define AR9170_MAC_TXRX_MPI_RX_TO_MASK 0xfff00000 377 378#define AR9170_MAC_REG_BCN_ADDR (AR9170_MAC_REG_BASE + 0xd84) 379#define AR9170_MAC_REG_BCN_LENGTH (AR9170_MAC_REG_BASE + 0xd88) --- 401 unchanged lines hidden --- |