reg.h (f97b12cce6dea51880a6a89d4607c29c70a6a841) reg.h (b141581923ab4904052174e3b4eb17cc3ce8632c)
1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

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1124
1125#define AR_RTC_PLL_DIV 0x0000001f
1126#define AR_RTC_PLL_DIV_S 0
1127#define AR_RTC_PLL_DIV2 0x00000020
1128#define AR_RTC_PLL_REFDIV_5 0x000000c0
1129#define AR_RTC_PLL_CLKSEL 0x00000300
1130#define AR_RTC_PLL_CLKSEL_S 8
1131
1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

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1124
1125#define AR_RTC_PLL_DIV 0x0000001f
1126#define AR_RTC_PLL_DIV_S 0
1127#define AR_RTC_PLL_DIV2 0x00000020
1128#define AR_RTC_PLL_REFDIV_5 0x000000c0
1129#define AR_RTC_PLL_CLKSEL 0x00000300
1130#define AR_RTC_PLL_CLKSEL_S 8
1131
1132#define PLL3 0x16188
1133#define PLL3_DO_MEAS_MASK 0x40000000
1134#define PLL4 0x1618c
1135#define PLL4_MEAS_DONE 0x8
1136#define SQSUM_DVC_MASK 0x007ffff8
1137
1132#define AR_RTC_RESET \
1133 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0040) : 0x7040)
1134#define AR_RTC_RESET_EN (0x00000001)
1135
1136#define AR_RTC_STATUS \
1137 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0044) : 0x7044)
1138
1139#define AR_RTC_STATUS_M \

--- 701 unchanged lines hidden --- 		1138#define AR_RTC_RESET \
1139 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0040) : 0x7040)
1140#define AR_RTC_RESET_EN (0x00000001)
1141
1142#define AR_RTC_STATUS \
1143 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0044) : 0x7044)
1144
1145#define AR_RTC_STATUS_M \

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