phy.h (066edc80ebd9e429d593dcfe97b3ed01c9823847) phy.h (7f63845f2a5f54c64968a4221561c619468b8a54)
1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

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414
415#define AR_PHY_CCK_DETECT 0xA208
416#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
417#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
418/* [12:6] settling time for antenna switch */
419#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0
420#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
421#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

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414
415#define AR_PHY_CCK_DETECT 0xA208
416#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
417#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
418/* [12:6] settling time for antenna switch */
419#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0
420#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
421#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
422#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13
422
423#define AR_PHY_GAIN_2GHZ 0xA20C
424#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00FC0000
425#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18
426#define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00
427#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10
428#define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F
429#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0

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424#define AR_PHY_GAIN_2GHZ 0xA20C
425#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00FC0000
426#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18
427#define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00
428#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10
429#define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F
430#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0

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