pci.c (aa7eb8e78d8ecd6cd0475d86ea8385ff9cb47ece) pci.c (d4930086bdd0c08a8b3a4d66a9c702297cb74a99)
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/nl80211.h>
18#include <linux/pci.h>
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/nl80211.h>
18#include <linux/pci.h>
19#include <linux/pci-aspm.h>
19#include <linux/ath9k_platform.h>
20#include "ath9k.h"
21
22static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
23 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
24 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
25 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
26 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */

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110 struct pci_dev *pdev = to_pci_dev(sc->dev);
111 u8 lnkctl;
112
113 pci_read_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, &lnkctl);
114 lnkctl |= PCI_EXP_LNKCTL_ES;
115 pci_write_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, lnkctl);
116}
117
20#include <linux/ath9k_platform.h>
21#include "ath9k.h"
22
23static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
24 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
25 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
26 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
27 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */

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111 struct pci_dev *pdev = to_pci_dev(sc->dev);
112 u8 lnkctl;
113
114 pci_read_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, &lnkctl);
115 lnkctl |= PCI_EXP_LNKCTL_ES;
116 pci_write_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, lnkctl);
117}
118
119static void ath_pci_aspm_init(struct ath_common *common)
120{
121 struct ath_softc *sc = (struct ath_softc *) common->priv;
122 struct ath_hw *ah = sc->sc_ah;
123 struct pci_dev *pdev = to_pci_dev(sc->dev);
124 struct pci_dev *parent;
125 int pos;
126 u8 aspm;
127
128 if (!pci_is_pcie(pdev))
129 return;
130
131 parent = pdev->bus->self;
132 if (WARN_ON(!parent))
133 return;
134
135 pos = pci_pcie_cap(parent);
136 pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm);
137 if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) {
138 ah->aspm_enabled = true;
139 /* Initialize PCIe PM and SERDES registers. */
140 ath9k_hw_configpcipowersave(ah, 0, 0);
141 }
142}
143
118static const struct ath_bus_ops ath_pci_bus_ops = {
119 .ath_bus_type = ATH_PCI,
120 .read_cachesize = ath_pci_read_cachesize,
121 .eeprom_read = ath_pci_eeprom_read,
122 .bt_coex_prep = ath_pci_bt_coex_prep,
123 .extn_synch_en = ath_pci_extn_synch_enable,
144static const struct ath_bus_ops ath_pci_bus_ops = {
145 .ath_bus_type = ATH_PCI,
146 .read_cachesize = ath_pci_read_cachesize,
147 .eeprom_read = ath_pci_eeprom_read,
148 .bt_coex_prep = ath_pci_bt_coex_prep,
149 .extn_synch_en = ath_pci_extn_synch_enable,
150 .aspm_init = ath_pci_aspm_init,
124};
125
126static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
127{
128 void __iomem *mem;
129 struct ath_softc *sc;
130 struct ieee80211_hw *hw;
131 u8 csz;

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273static int ath_pci_suspend(struct device *device)
274{
275 struct pci_dev *pdev = to_pci_dev(device);
276 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
277 struct ath_softc *sc = hw->priv;
278
279 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
280
151};
152
153static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
154{
155 void __iomem *mem;
156 struct ath_softc *sc;
157 struct ieee80211_hw *hw;
158 u8 csz;

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300static int ath_pci_suspend(struct device *device)
301{
302 struct pci_dev *pdev = to_pci_dev(device);
303 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
304 struct ath_softc *sc = hw->priv;
305
306 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
307
308 /* The device has to be moved to FULLSLEEP forcibly.
309 * Otherwise the chip never moved to full sleep,
310 * when no interface is up.
311 */
312 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
313
281 return 0;
282}
283
284static int ath_pci_resume(struct device *device)
285{
286 struct pci_dev *pdev = to_pci_dev(device);
287 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
288 struct ath_softc *sc = hw->priv;

--- 67 unchanged lines hidden --- 		314 return 0;
315}
316
317static int ath_pci_resume(struct device *device)
318{
319 struct pci_dev *pdev = to_pci_dev(device);
320 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
321 struct ath_softc *sc = hw->priv;

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