hw.h (c57b182b9fb7cc731f3d6620f86b43ce5ee702d2) hw.h (4ed15762dce67192d4662860470a8be1f6d5fd53)
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

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163#define POWER_UP_TIME 10000
164#define SPUR_RSSI_THRESH 40
165#define UPPER_5G_SUB_BAND_START 5700
166#define MID_5G_SUB_BAND_START 5400
167
168#define CAB_TIMEOUT_VAL 10
169#define BEACON_TIMEOUT_VAL 10
170#define MIN_BEACON_TIMEOUT_VAL 1
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

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163#define POWER_UP_TIME 10000
164#define SPUR_RSSI_THRESH 40
165#define UPPER_5G_SUB_BAND_START 5700
166#define MID_5G_SUB_BAND_START 5400
167
168#define CAB_TIMEOUT_VAL 10
169#define BEACON_TIMEOUT_VAL 10
170#define MIN_BEACON_TIMEOUT_VAL 1
171#define SLEEP_SLOP 3
171#define SLEEP_SLOP TU_TO_USEC(3)
172
173#define INIT_CONFIG_STATUS 0x00000000
174#define INIT_RSSI_THR 0x00000700
175#define INIT_BCON_CNTRL_REG 0x00000000
176
177#define TU_TO_USEC(_tu) ((_tu) << 10)
178
179#define ATH9K_HW_RX_HP_QDEPTH 16

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446};
447
448struct ath9k_beacon_state {
449 u32 bs_nexttbtt;
450 u32 bs_nextdtim;
451 u32 bs_intval;
452#define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
453 u32 bs_dtimperiod;
172
173#define INIT_CONFIG_STATUS 0x00000000
174#define INIT_RSSI_THR 0x00000700
175#define INIT_BCON_CNTRL_REG 0x00000000
176
177#define TU_TO_USEC(_tu) ((_tu) << 10)
178
179#define ATH9K_HW_RX_HP_QDEPTH 16

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446};
447
448struct ath9k_beacon_state {
449 u32 bs_nexttbtt;
450 u32 bs_nextdtim;
451 u32 bs_intval;
452#define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
453 u32 bs_dtimperiod;
454 u16 bs_cfpperiod;
455 u16 bs_cfpmaxduration;
456 u32 bs_cfpnext;
457 u16 bs_timoffset;
458 u16 bs_bmissthreshold;
459 u32 bs_sleepduration;
460 u32 bs_tsfoor_threshold;
461};
462
463struct chan_centers {
464 u16 synth_center;
465 u16 ctl_center;

--- 679 unchanged lines hidden --- 		454 u16 bs_bmissthreshold;
455 u32 bs_sleepduration;
456 u32 bs_tsfoor_threshold;
457};
458
459struct chan_centers {
460 u16 synth_center;
461 u16 ctl_center;

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