hw.h (9f6e20cee6253c4ca5faacba8dbd09ebe70132ed) hw.h (8a30930563521c9dba73c93b5631be1d0993f78f)
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

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204 ATH9K_HW_CAP_FASTCLOCK = BIT(7),
205 ATH9K_HW_CAP_SGI_20 = BIT(8),
206 ATH9K_HW_CAP_PAPRD = BIT(9),
207 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10),
208 ATH9K_HW_CAP_2GHZ = BIT(11),
209 ATH9K_HW_CAP_5GHZ = BIT(12),
210 ATH9K_HW_CAP_APM = BIT(13),
211 ATH9K_HW_CAP_RTT = BIT(14),
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

--- 195 unchanged lines hidden (view full) ---

204 ATH9K_HW_CAP_FASTCLOCK = BIT(7),
205 ATH9K_HW_CAP_SGI_20 = BIT(8),
206 ATH9K_HW_CAP_PAPRD = BIT(9),
207 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10),
208 ATH9K_HW_CAP_2GHZ = BIT(11),
209 ATH9K_HW_CAP_5GHZ = BIT(12),
210 ATH9K_HW_CAP_APM = BIT(13),
211 ATH9K_HW_CAP_RTT = BIT(14),
212#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
212 ATH9K_HW_CAP_MCI = BIT(15),
213 ATH9K_HW_CAP_MCI = BIT(15),
214#else
215 ATH9K_HW_CAP_MCI = 0,
216#endif
213 ATH9K_HW_CAP_DFS = BIT(16),
214};
215
216struct ath9k_hw_capabilities {
217 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
218 u16 rts_aggr_limit;
219 u8 tx_chainmask;
220 u8 rx_chainmask;

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1223bool ar9003_mci_check_int(struct ath_hw *ah, u32 ints);
1224void ar9003_mci_remote_reset(struct ath_hw *ah, bool wait_done);
1225void ar9003_mci_send_sys_waking(struct ath_hw *ah, bool wait_done);
1226void ar9003_mci_send_lna_transfer(struct ath_hw *ah, bool wait_done);
1227void ar9003_mci_sync_bt_state(struct ath_hw *ah);
1228void ar9003_mci_get_interrupt(struct ath_hw *ah, u32 *raw_intr,
1229 u32 *rx_msg_intr);
1230
217 ATH9K_HW_CAP_DFS = BIT(16),
218};
219
220struct ath9k_hw_capabilities {
221 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
222 u16 rts_aggr_limit;
223 u8 tx_chainmask;
224 u8 rx_chainmask;

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1227bool ar9003_mci_check_int(struct ath_hw *ah, u32 ints);
1228void ar9003_mci_remote_reset(struct ath_hw *ah, bool wait_done);
1229void ar9003_mci_send_sys_waking(struct ath_hw *ah, bool wait_done);
1230void ar9003_mci_send_lna_transfer(struct ath_hw *ah, bool wait_done);
1231void ar9003_mci_sync_bt_state(struct ath_hw *ah);
1232void ar9003_mci_get_interrupt(struct ath_hw *ah, u32 *raw_intr,
1233 u32 *rx_msg_intr);
1234
1235#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1236static inline enum ath_btcoex_scheme
1237ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
1238{
1239 return ah->btcoex_hw.scheme;
1240}
1241#else
1242#define ath9k_hw_get_btcoex_scheme(...) ATH_BTCOEX_CFG_NONE
1243#endif
1244
1231#define ATH9K_CLOCK_RATE_CCK 22
1232#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1233#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1234#define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
1235
1236#endif
1245#define ATH9K_CLOCK_RATE_CCK 22
1246#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1247#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1248#define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
1249
1250#endif