hw.h (64ea57d0c77bd85003b63c6090ddfae114ef6508) hw.h (990e08a0f6115ce93b480325a575b535c92513ee)
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

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703 enum ath9k_power_mode power_mode;
704
705 s8 noise;
706 struct ath9k_hw_cal_data *caldata;
707 struct ath9k_pacal_info pacal_info;
708 struct ar5416Stats stats;
709 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
710
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

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703 enum ath9k_power_mode power_mode;
704
705 s8 noise;
706 struct ath9k_hw_cal_data *caldata;
707 struct ath9k_pacal_info pacal_info;
708 struct ar5416Stats stats;
709 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
710
711 int16_t curchan_rad_index;
712 enum ath9k_int imask;
713 u32 imrs2_reg;
714 u32 txok_interrupt_mask;
715 u32 txerr_interrupt_mask;
716 u32 txdesc_interrupt_mask;
717 u32 txeol_interrupt_mask;
718 u32 txurn_interrupt_mask;
719 atomic_t intr_ref_cnt;

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757 u32 unsign[AR5416_MAX_CHAINS];
758 int32_t sign[AR5416_MAX_CHAINS];
759 } meas3;
760 u16 cal_samples;
761 u8 enabled_cals;
762
763 u32 sta_id1_defaults;
764 u32 misc_mode;
711 enum ath9k_int imask;
712 u32 imrs2_reg;
713 u32 txok_interrupt_mask;
714 u32 txerr_interrupt_mask;
715 u32 txdesc_interrupt_mask;
716 u32 txeol_interrupt_mask;
717 u32 txurn_interrupt_mask;
718 atomic_t intr_ref_cnt;

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756 u32 unsign[AR5416_MAX_CHAINS];
757 int32_t sign[AR5416_MAX_CHAINS];
758 } meas3;
759 u16 cal_samples;
760 u8 enabled_cals;
761
762 u32 sta_id1_defaults;
763 u32 misc_mode;
765 enum {
766 AUTO_32KHZ,
767 USE_32KHZ,
768 DONT_USE_32KHZ,
769 } enable_32kHz_clock;
770
771 /* Private to hardware code */
772 struct ath_hw_private_ops private_ops;
773 /* Accessed by the lower level driver */
774 struct ath_hw_ops ops;
775
776 /* Used to program the radio on non single-chip devices */
777 u32 *analogBank0Data;
778 u32 *analogBank1Data;
779 u32 *analogBank2Data;
780 u32 *analogBank3Data;
781 u32 *analogBank6Data;
782 u32 *analogBank6TPCData;
783 u32 *analogBank7Data;
784 u32 *bank6Temp;
785
764
765 /* Private to hardware code */
766 struct ath_hw_private_ops private_ops;
767 /* Accessed by the lower level driver */
768 struct ath_hw_ops ops;
769
770 /* Used to program the radio on non single-chip devices */
771 u32 *analogBank0Data;
772 u32 *analogBank1Data;
773 u32 *analogBank2Data;
774 u32 *analogBank3Data;
775 u32 *analogBank6Data;
776 u32 *analogBank6TPCData;
777 u32 *analogBank7Data;
778 u32 *bank6Temp;
779
786 u8 txpower_limit;
787 int coverage_class;
788 u32 slottime;
789 u32 globaltxtimeout;
790
791 /* ANI */
792 u32 proc_phyerr;
793 u32 aniperiod;
794 int totalSizeDesired[5];

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843 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
844 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
845
846 u32 intr_gen_timer_trigger;
847 u32 intr_gen_timer_thresh;
848 struct ath_gen_timer_table hw_gen_timers;
849
850 struct ar9003_txs *ts_ring;
780 int coverage_class;
781 u32 slottime;
782 u32 globaltxtimeout;
783
784 /* ANI */
785 u32 proc_phyerr;
786 u32 aniperiod;
787 int totalSizeDesired[5];

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836 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
837 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
838
839 u32 intr_gen_timer_trigger;
840 u32 intr_gen_timer_thresh;
841 struct ath_gen_timer_table hw_gen_timers;
842
843 struct ar9003_txs *ts_ring;
851 void *ts_start;
852 u32 ts_paddr_start;
853 u32 ts_paddr_end;
854 u16 ts_tail;
855 u16 ts_size;
856
857 u32 bb_watchdog_last_status;
858 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
859 u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */

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910}
911
912static inline u8 get_streams(int mask)
913{
914 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
915}
916
917/* Initialization, Detach, Reset */
844 u32 ts_paddr_start;
845 u32 ts_paddr_end;
846 u16 ts_tail;
847 u16 ts_size;
848
849 u32 bb_watchdog_last_status;
850 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
851 u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */

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902}
903
904static inline u8 get_streams(int mask)
905{
906 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
907}
908
909/* Initialization, Detach, Reset */
918const char *ath9k_hw_probe(u16 vendorid, u16 devid);
919void ath9k_hw_deinit(struct ath_hw *ah);
920int ath9k_hw_init(struct ath_hw *ah);
921int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
922 struct ath9k_hw_cal_data *caldata, bool fastcc);
923int ath9k_hw_fill_cap_info(struct ath_hw *ah);
924u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
925
926/* GPIO / RFKILL / Antennae */

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960void ath9k_hw_set11nmac2040(struct ath_hw *ah);
961void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
962void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
963 const struct ath9k_beacon_state *bs);
964bool ath9k_hw_check_alive(struct ath_hw *ah);
965
966bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
967
910void ath9k_hw_deinit(struct ath_hw *ah);
911int ath9k_hw_init(struct ath_hw *ah);
912int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
913 struct ath9k_hw_cal_data *caldata, bool fastcc);
914int ath9k_hw_fill_cap_info(struct ath_hw *ah);
915u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
916
917/* GPIO / RFKILL / Antennae */

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951void ath9k_hw_set11nmac2040(struct ath_hw *ah);
952void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
953void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
954 const struct ath9k_beacon_state *bs);
955bool ath9k_hw_check_alive(struct ath_hw *ah);
956
957bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
958
959#ifdef CONFIG_ATH9K_DEBUGFS
960void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause);
961#else
962static inline void ath9k_debug_sync_cause(struct ath_common *common,
963 u32 sync_cause) {}
964#endif
965
968/* Generic hw timer primitives */
969struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
970 void (*trigger)(void *),
971 void (*overflow)(void *),
972 void *arg,
973 u8 timer_index);
974void ath9k_hw_gen_timer_start(struct ath_hw *ah,
975 struct ath_gen_timer *timer,

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980void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
981void ath_gen_timer_isr(struct ath_hw *hw);
982
983void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
984
985/* PHY */
986void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
987 u32 *coef_mantissa, u32 *coef_exponent);
966/* Generic hw timer primitives */
967struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
968 void (*trigger)(void *),
969 void (*overflow)(void *),
970 void *arg,
971 u8 timer_index);
972void ath9k_hw_gen_timer_start(struct ath_hw *ah,
973 struct ath_gen_timer *timer,

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978void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
979void ath_gen_timer_isr(struct ath_hw *hw);
980
981void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
982
983/* PHY */
984void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
985 u32 *coef_mantissa, u32 *coef_exponent);
988void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
989 bool test);
986void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan);
990
991/*
992 * Code Specific to AR5008, AR9001 or AR9002,
993 * we stuff these here to avoid callbacks for AR9003.
994 */
995int ar9002_hw_rf_claim(struct ath_hw *ah);
996void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
997

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1007void ar9003_paprd_populate_single_table(struct ath_hw *ah,
1008 struct ath9k_hw_cal_data *caldata,
1009 int chain);
1010int ar9003_paprd_create_curve(struct ath_hw *ah,
1011 struct ath9k_hw_cal_data *caldata, int chain);
1012int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
1013int ar9003_paprd_init_table(struct ath_hw *ah);
1014bool ar9003_paprd_is_done(struct ath_hw *ah);
987
988/*
989 * Code Specific to AR5008, AR9001 or AR9002,
990 * we stuff these here to avoid callbacks for AR9003.
991 */
992int ar9002_hw_rf_claim(struct ath_hw *ah);
993void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
994

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1004void ar9003_paprd_populate_single_table(struct ath_hw *ah,
1005 struct ath9k_hw_cal_data *caldata,
1006 int chain);
1007int ar9003_paprd_create_curve(struct ath_hw *ah,
1008 struct ath9k_hw_cal_data *caldata, int chain);
1009int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
1010int ar9003_paprd_init_table(struct ath_hw *ah);
1011bool ar9003_paprd_is_done(struct ath_hw *ah);
1015void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains);
1016
1017/* Hardware family op attach helpers */
1018void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
1019void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
1020void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
1021
1022void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
1023void ar9003_hw_attach_calib_ops(struct ath_hw *ah);

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1013/* Hardware family op attach helpers */
1014void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
1015void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
1016void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
1017
1018void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
1019void ar9003_hw_attach_calib_ops(struct ath_hw *ah);

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