hw.h (621a5f7ad9cd1ce7933f1d302067cbd58354173c) hw.h (871d0051f06030bfddd5971ef2afc1eb7291ab4e)
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

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327#define AR_PCIE_PLL_PWRSAVE_ON_D3 BIT(1)
328#define AR_PCIE_PLL_PWRSAVE_ON_D0 BIT(2)
329#define AR_PCIE_CDR_PWRSAVE_ON_D3 BIT(3)
330#define AR_PCIE_CDR_PWRSAVE_ON_D0 BIT(4)
331
332struct ath9k_ops_config {
333 int dma_beacon_response_time;
334 int sw_beacon_response_time;
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

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327#define AR_PCIE_PLL_PWRSAVE_ON_D3 BIT(1)
328#define AR_PCIE_PLL_PWRSAVE_ON_D0 BIT(2)
329#define AR_PCIE_CDR_PWRSAVE_ON_D3 BIT(3)
330#define AR_PCIE_CDR_PWRSAVE_ON_D0 BIT(4)
331
332struct ath9k_ops_config {
333 int dma_beacon_response_time;
334 int sw_beacon_response_time;
335 bool cwm_ignore_extcca;
335 u32 cwm_ignore_extcca;
336 u32 pcie_waen;
337 u8 analog_shiftreg;
338 u32 ofdm_trig_low;
339 u32 ofdm_trig_high;
340 u32 cck_trig_high;
341 u32 cck_trig_low;
336 u32 pcie_waen;
337 u8 analog_shiftreg;
338 u32 ofdm_trig_low;
339 u32 ofdm_trig_high;
340 u32 cck_trig_high;
341 u32 cck_trig_low;
342 bool enable_paprd;
342 u32 enable_paprd;
343 int serialize_regmode;
344 bool rx_intr_mitigation;
345 bool tx_intr_mitigation;
346 u8 max_txtrig_level;
347 u16 ani_poll_interval; /* ANI poll interval in ms */
348 u16 hw_hang_checks;
349 u16 rimt_first;
350 u16 rimt_last;

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914 struct ar5416IniArray iniAdditional;
915 struct ar5416IniArray iniModesRxGain;
916 struct ar5416IniArray ini_modes_rx_gain_bounds;
917 struct ar5416IniArray iniModesTxGain;
918 struct ar5416IniArray iniCckfirNormal;
919 struct ar5416IniArray iniCckfirJapan2484;
920 struct ar5416IniArray iniModes_9271_ANI_reg;
921 struct ar5416IniArray ini_radio_post_sys2ant;
343 int serialize_regmode;
344 bool rx_intr_mitigation;
345 bool tx_intr_mitigation;
346 u8 max_txtrig_level;
347 u16 ani_poll_interval; /* ANI poll interval in ms */
348 u16 hw_hang_checks;
349 u16 rimt_first;
350 u16 rimt_last;

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914 struct ar5416IniArray iniAdditional;
915 struct ar5416IniArray iniModesRxGain;
916 struct ar5416IniArray ini_modes_rx_gain_bounds;
917 struct ar5416IniArray iniModesTxGain;
918 struct ar5416IniArray iniCckfirNormal;
919 struct ar5416IniArray iniCckfirJapan2484;
920 struct ar5416IniArray iniModes_9271_ANI_reg;
921 struct ar5416IniArray ini_radio_post_sys2ant;
922 struct ar5416IniArray ini_modes_rxgain_5g_xlna;
922 struct ar5416IniArray ini_modes_rxgain_xlna;
923 struct ar5416IniArray ini_modes_rxgain_bb_core;
924 struct ar5416IniArray ini_modes_rxgain_bb_postamble;
925
926 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
927 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
928 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
929 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
930

--- 287 unchanged lines hidden --- 		923 struct ar5416IniArray ini_modes_rxgain_bb_core;
924 struct ar5416IniArray ini_modes_rxgain_bb_postamble;
925
926 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
927 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
928 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
929 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
930

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