hw.h (1aa8e84736fb1a584c679f2893245826583a0526) hw.h (1cf6873a191388ff7d06bbd70f68bbffe1d70019)
1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

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122 ATH9K_MODE_11NG_HT20,
123 ATH9K_MODE_11NA_HT40PLUS,
124 ATH9K_MODE_11NA_HT40MINUS,
125 ATH9K_MODE_11NG_HT40PLUS,
126 ATH9K_MODE_11NG_HT40MINUS,
127 ATH9K_MODE_MAX,
128};
129
1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

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122 ATH9K_MODE_11NG_HT20,
123 ATH9K_MODE_11NA_HT40PLUS,
124 ATH9K_MODE_11NA_HT40MINUS,
125 ATH9K_MODE_11NG_HT40PLUS,
126 ATH9K_MODE_11NG_HT40MINUS,
127 ATH9K_MODE_MAX,
128};
129
130enum ath9k_ant_setting {
131 ATH9K_ANT_VARIABLE = 0,
132 ATH9K_ANT_FIXED_A,
133 ATH9K_ANT_FIXED_B
134};
135
130enum ath9k_hw_caps {
131 ATH9K_HW_CAP_MIC_AESCCM = BIT(0),
132 ATH9K_HW_CAP_MIC_CKIP = BIT(1),
133 ATH9K_HW_CAP_MIC_TKIP = BIT(2),
134 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3),
135 ATH9K_HW_CAP_CIPHER_CKIP = BIT(4),
136 ATH9K_HW_CAP_CIPHER_TKIP = BIT(5),
137 ATH9K_HW_CAP_VEOL = BIT(6),

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186 u32 pcie_waen;
187 u8 analog_shiftreg;
188 u8 ht_enable;
189 u32 ofdm_trig_low;
190 u32 ofdm_trig_high;
191 u32 cck_trig_high;
192 u32 cck_trig_low;
193 u32 enable_ani;
136enum ath9k_hw_caps {
137 ATH9K_HW_CAP_MIC_AESCCM = BIT(0),
138 ATH9K_HW_CAP_MIC_CKIP = BIT(1),
139 ATH9K_HW_CAP_MIC_TKIP = BIT(2),
140 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3),
141 ATH9K_HW_CAP_CIPHER_CKIP = BIT(4),
142 ATH9K_HW_CAP_CIPHER_TKIP = BIT(5),
143 ATH9K_HW_CAP_VEOL = BIT(6),

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192 u32 pcie_waen;
193 u8 analog_shiftreg;
194 u8 ht_enable;
195 u32 ofdm_trig_low;
196 u32 ofdm_trig_high;
197 u32 cck_trig_high;
198 u32 cck_trig_low;
199 u32 enable_ani;
194 u16 diversity_control;
200 enum ath9k_ant_setting diversity_control;
195 u16 antenna_switch_swap;
196 int serialize_regmode;
197 bool intr_mitigation;
198#define SPUR_DISABLE 0
199#define SPUR_ENABLE_IOCTL 1
200#define SPUR_ENABLE_EEPROM 2
201#define AR_EEPROM_MODAL_SPURS 5
202#define AR_SPUR_5413_1 1640

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325
326enum ath9k_power_mode {
327 ATH9K_PM_AWAKE = 0,
328 ATH9K_PM_FULL_SLEEP,
329 ATH9K_PM_NETWORK_SLEEP,
330 ATH9K_PM_UNDEFINED
331};
332
201 u16 antenna_switch_swap;
202 int serialize_regmode;
203 bool intr_mitigation;
204#define SPUR_DISABLE 0
205#define SPUR_ENABLE_IOCTL 1
206#define SPUR_ENABLE_EEPROM 2
207#define AR_EEPROM_MODAL_SPURS 5
208#define AR_SPUR_5413_1 1640

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331
332enum ath9k_power_mode {
333 ATH9K_PM_AWAKE = 0,
334 ATH9K_PM_FULL_SLEEP,
335 ATH9K_PM_NETWORK_SLEEP,
336 ATH9K_PM_UNDEFINED
337};
338
333enum ath9k_ant_setting {
334 ATH9K_ANT_VARIABLE = 0,
335 ATH9K_ANT_FIXED_A,
336 ATH9K_ANT_FIXED_B
337};
338
339enum ath9k_tp_scale {
340 ATH9K_TP_SCALE_MAX = 0,
341 ATH9K_TP_SCALE_50,
342 ATH9K_TP_SCALE_25,
343 ATH9K_TP_SCALE_12,
344 ATH9K_TP_SCALE_MIN
345};
346

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432 u32 mask_reg;
433 u32 txok_interrupt_mask;
434 u32 txerr_interrupt_mask;
435 u32 txdesc_interrupt_mask;
436 u32 txeol_interrupt_mask;
437 u32 txurn_interrupt_mask;
438 bool chip_fullsleep;
439 u32 atim_window;
339enum ath9k_tp_scale {
340 ATH9K_TP_SCALE_MAX = 0,
341 ATH9K_TP_SCALE_50,
342 ATH9K_TP_SCALE_25,
343 ATH9K_TP_SCALE_12,
344 ATH9K_TP_SCALE_MIN
345};
346

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432 u32 mask_reg;
433 u32 txok_interrupt_mask;
434 u32 txerr_interrupt_mask;
435 u32 txdesc_interrupt_mask;
436 u32 txeol_interrupt_mask;
437 u32 txurn_interrupt_mask;
438 bool chip_fullsleep;
439 u32 atim_window;
440 u16 antenna_switch_swap;
441 enum ath9k_ant_setting diversity_control;
442
443 /* Calibration */
444 enum ath9k_cal_types supp_cals;
445 struct ath9k_cal_list iq_caldata;
446 struct ath9k_cal_list adcgain_caldata;
447 struct ath9k_cal_list adcdc_calinitdata;
448 struct ath9k_cal_list adcdc_caldata;
449 struct ath9k_cal_list *cal_list;

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441 /* Calibration */
442 enum ath9k_cal_types supp_cals;
443 struct ath9k_cal_list iq_caldata;
444 struct ath9k_cal_list adcgain_caldata;
445 struct ath9k_cal_list adcdc_calinitdata;
446 struct ath9k_cal_list adcdc_caldata;
447 struct ath9k_cal_list *cal_list;

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