hw.c (89916cc90a78fffbc4c3d7cb1f6540fb2e551804) hw.c (a01ab81b09c55025365c1de1345b941a18e05529)
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

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2380 /* AR9580 will likely be our first target to get testing on */
2381 case AR_SREV_VERSION_9580:
2382 return true;
2383 default:
2384 return false;
2385 }
2386}
2387
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

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2380 /* AR9580 will likely be our first target to get testing on */
2381 case AR_SREV_VERSION_9580:
2382 return true;
2383 default:
2384 return false;
2385 }
2386}
2387
2388static void ath9k_gpio_cap_init(struct ath_hw *ah)
2389{
2390 struct ath9k_hw_capabilities *pCap = &ah->caps;
2391
2392 if (AR_SREV_9271(ah)) {
2393 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2394 pCap->gpio_mask = AR9271_GPIO_MASK;
2395 } else if (AR_DEVID_7010(ah)) {
2396 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2397 pCap->gpio_mask = AR7010_GPIO_MASK;
2398 } else if (AR_SREV_9287(ah)) {
2399 pCap->num_gpio_pins = AR9287_NUM_GPIO;
2400 pCap->gpio_mask = AR9287_GPIO_MASK;
2401 } else if (AR_SREV_9285(ah)) {
2402 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2403 pCap->gpio_mask = AR9285_GPIO_MASK;
2404 } else if (AR_SREV_9280(ah)) {
2405 pCap->num_gpio_pins = AR9280_NUM_GPIO;
2406 pCap->gpio_mask = AR9280_GPIO_MASK;
2407 } else if (AR_SREV_9300(ah)) {
2408 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2409 pCap->gpio_mask = AR9300_GPIO_MASK;
2410 } else if (AR_SREV_9330(ah)) {
2411 pCap->num_gpio_pins = AR9330_NUM_GPIO;
2412 pCap->gpio_mask = AR9330_GPIO_MASK;
2413 } else if (AR_SREV_9340(ah)) {
2414 pCap->num_gpio_pins = AR9340_NUM_GPIO;
2415 pCap->gpio_mask = AR9340_GPIO_MASK;
2416 } else if (AR_SREV_9462(ah)) {
2417 pCap->num_gpio_pins = AR9462_NUM_GPIO;
2418 pCap->gpio_mask = AR9462_GPIO_MASK;
2419 } else if (AR_SREV_9485(ah)) {
2420 pCap->num_gpio_pins = AR9485_NUM_GPIO;
2421 pCap->gpio_mask = AR9485_GPIO_MASK;
2422 } else if (AR_SREV_9531(ah)) {
2423 pCap->num_gpio_pins = AR9531_NUM_GPIO;
2424 pCap->gpio_mask = AR9531_GPIO_MASK;
2425 } else if (AR_SREV_9550(ah)) {
2426 pCap->num_gpio_pins = AR9550_NUM_GPIO;
2427 pCap->gpio_mask = AR9550_GPIO_MASK;
2428 } else if (AR_SREV_9561(ah)) {
2429 pCap->num_gpio_pins = AR9561_NUM_GPIO;
2430 pCap->gpio_mask = AR9561_GPIO_MASK;
2431 } else if (AR_SREV_9565(ah)) {
2432 pCap->num_gpio_pins = AR9565_NUM_GPIO;
2433 pCap->gpio_mask = AR9565_GPIO_MASK;
2434 } else if (AR_SREV_9580(ah)) {
2435 pCap->num_gpio_pins = AR9580_NUM_GPIO;
2436 pCap->gpio_mask = AR9580_GPIO_MASK;
2437 } else {
2438 pCap->num_gpio_pins = AR_NUM_GPIO;
2439 pCap->gpio_mask = AR_GPIO_MASK;
2440 }
2441}
2442
2388int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2389{
2390 struct ath9k_hw_capabilities *pCap = &ah->caps;
2391 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2392 struct ath_common *common = ath9k_hw_common(ah);
2393
2394 u16 eeval;
2395 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;

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2473
2474 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2475
2476 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
2477 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2478 else
2479 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2480
2443int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2444{
2445 struct ath9k_hw_capabilities *pCap = &ah->caps;
2446 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2447 struct ath_common *common = ath9k_hw_common(ah);
2448
2449 u16 eeval;
2450 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;

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2528
2529 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2530
2531 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
2532 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2533 else
2534 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2535
2481 if (AR_SREV_9271(ah))
2482 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2483 else if (AR_DEVID_7010(ah))
2484 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2485 else if (AR_SREV_9300_20_OR_LATER(ah))
2486 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2487 else if (AR_SREV_9287_11_OR_LATER(ah))
2488 pCap->num_gpio_pins = AR9287_NUM_GPIO;
2489 else if (AR_SREV_9285_12_OR_LATER(ah))
2490 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2491 else if (AR_SREV_9280_20_OR_LATER(ah))
2492 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2493 else
2494 pCap->num_gpio_pins = AR_NUM_GPIO;
2536 ath9k_gpio_cap_init(ah);
2495
2496 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
2497 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2498 else
2499 pCap->rts_aggr_limit = (8 * 1024);
2500
2501#ifdef CONFIG_ATH9K_RFKILL
2502 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);

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2538 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
2539 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2540 else
2541 pCap->rts_aggr_limit = (8 * 1024);
2542
2543#ifdef CONFIG_ATH9K_RFKILL
2544 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);

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