hw.c (6124a4e430b64d1577438c8648c59e996d02e73e) hw.c (d4930086bdd0c08a8b3a4d66a9c702297cb74a99)
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

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313 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
314 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
315 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
316 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
317
318 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
319}
320
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

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313 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
314 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
315 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
316 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
317
318 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
319}
320
321static void ath9k_hw_aspm_init(struct ath_hw *ah)
322{
323 struct ath_common *common = ath9k_hw_common(ah);
324
325 if (common->bus_ops->aspm_init)
326 common->bus_ops->aspm_init(common);
327}
328
321/* This should work for all families including legacy */
322static bool ath9k_hw_chip_test(struct ath_hw *ah)
323{
324 struct ath_common *common = ath9k_hw_common(ah);
325 u32 regAddr[2] = { AR_STA_ID0 };
326 u32 regHold[2];
327 static const u32 patternData[4] = {
328 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999

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373{
374 int i;
375
376 ah->config.dma_beacon_response_time = 2;
377 ah->config.sw_beacon_response_time = 10;
378 ah->config.additional_swba_backoff = 0;
379 ah->config.ack_6mb = 0x0;
380 ah->config.cwm_ignore_extcca = 0;
329/* This should work for all families including legacy */
330static bool ath9k_hw_chip_test(struct ath_hw *ah)
331{
332 struct ath_common *common = ath9k_hw_common(ah);
333 u32 regAddr[2] = { AR_STA_ID0 };
334 u32 regHold[2];
335 static const u32 patternData[4] = {
336 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999

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381{
382 int i;
383
384 ah->config.dma_beacon_response_time = 2;
385 ah->config.sw_beacon_response_time = 10;
386 ah->config.additional_swba_backoff = 0;
387 ah->config.ack_6mb = 0x0;
388 ah->config.cwm_ignore_extcca = 0;
381 ah->config.pcie_powersave_enable = 0;
382 ah->config.pcie_clock_req = 0;
383 ah->config.pcie_waen = 0;
384 ah->config.analog_shiftreg = 1;
385 ah->config.enable_ani = true;
386
387 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
388 ah->config.spurchans[i][0] = AR_NO_SPUR;
389 ah->config.spurchans[i][1] = AR_NO_SPUR;

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593 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
594 if (!AR_SREV_9300_20_OR_LATER(ah))
595 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
596
597 ath9k_hw_init_mode_regs(ah);
598
599
600 if (ah->is_pciexpress)
389 ah->config.pcie_clock_req = 0;
390 ah->config.pcie_waen = 0;
391 ah->config.analog_shiftreg = 1;
392 ah->config.enable_ani = true;
393
394 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
395 ah->config.spurchans[i][0] = AR_NO_SPUR;
396 ah->config.spurchans[i][1] = AR_NO_SPUR;

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600 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
601 if (!AR_SREV_9300_20_OR_LATER(ah))
602 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
603
604 ath9k_hw_init_mode_regs(ah);
605
606
607 if (ah->is_pciexpress)
601 ath9k_hw_configpcipowersave(ah, 0, 0);
608 ath9k_hw_aspm_init(ah);
602 else
603 ath9k_hw_disablepcie(ah);
604
605 if (!AR_SREV_9300_20_OR_LATER(ah))
606 ar9002_hw_cck_chan14_spread(ah);
607
608 r = ath9k_hw_post_init(ah);
609 if (r)

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610 ath9k_hw_disablepcie(ah);
611
612 if (!AR_SREV_9300_20_OR_LATER(ah))
613 ar9002_hw_cck_chan14_spread(ah);
614
615 r = ath9k_hw_post_init(ah);
616 if (r)

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