eeprom.c (495a1b4eff1a216a3ea171ac137f1807e6555f52) eeprom.c (8fbff4b838c53945d6baeafe609c627000f85cd6)
1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

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689 pPDADCValues[k] = pPDADCValues[k - 1];
690 k++;
691 }
692
693 return;
694#undef TMP_VAL_VPD_TABLE
695}
696
1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

--- 680 unchanged lines hidden (view full) ---

689 pPDADCValues[k] = pPDADCValues[k - 1];
690 k++;
691 }
692
693 return;
694#undef TMP_VAL_VPD_TABLE
695}
696
697static bool ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
697static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
698 struct ath9k_channel *chan,
699 int16_t *pTxPowerIndexOffset)
700{
701 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
702 struct cal_data_per_freq_4k *pRawDataset;
703 u8 *pCalBChans = NULL;
704 u16 pdGainOverlap_t2;
705 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];

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800 pdadcValues[4 * j + 3]);
801
802 regOffset += 4;
803 }
804 }
805 }
806
807 *pTxPowerIndexOffset = 0;
698 struct ath9k_channel *chan,
699 int16_t *pTxPowerIndexOffset)
700{
701 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
702 struct cal_data_per_freq_4k *pRawDataset;
703 u8 *pCalBChans = NULL;
704 u16 pdGainOverlap_t2;
705 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];

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800 pdadcValues[4 * j + 3]);
801
802 regOffset += 4;
803 }
804 }
805 }
806
807 *pTxPowerIndexOffset = 0;
808
809 return true;
810}
811
808}
809
812static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
810static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
813 struct ath9k_channel *chan,
814 int16_t *ratesArray,
815 u16 cfgCtl,
816 u16 AntennaReduction,
817 u16 twiceMaxRegulatoryPower,
818 u16 powerLimit)
819{
820 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;

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1036 ratesArray[rateHt40_0 + i] =
1037 targetPowerHt40.tPow2x[i];
1038 }
1039 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
1040 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
1041 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1042 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
1043 }
811 struct ath9k_channel *chan,
812 int16_t *ratesArray,
813 u16 cfgCtl,
814 u16 AntennaReduction,
815 u16 twiceMaxRegulatoryPower,
816 u16 powerLimit)
817{
818 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;

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1034 ratesArray[rateHt40_0 + i] =
1035 targetPowerHt40.tPow2x[i];
1036 }
1037 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
1038 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
1039 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1040 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
1041 }
1044 return true;
1045}
1046
1042}
1043
1047static int ath9k_hw_4k_set_txpower(struct ath_hw *ah,
1044static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
1048 struct ath9k_channel *chan,
1049 u16 cfgCtl,
1050 u8 twiceAntennaReduction,
1051 u8 twiceMaxRegulatoryPower,
1052 u8 powerLimit)
1053{
1054 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
1055 struct modal_eep_4k_header *pModal = &pEepData->modalHeader;

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1060
1061 memset(ratesArray, 0, sizeof(ratesArray));
1062
1063 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1064 AR5416_EEP_MINOR_VER_2) {
1065 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
1066 }
1067
1045 struct ath9k_channel *chan,
1046 u16 cfgCtl,
1047 u8 twiceAntennaReduction,
1048 u8 twiceMaxRegulatoryPower,
1049 u8 powerLimit)
1050{
1051 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
1052 struct modal_eep_4k_header *pModal = &pEepData->modalHeader;

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1057
1058 memset(ratesArray, 0, sizeof(ratesArray));
1059
1060 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1061 AR5416_EEP_MINOR_VER_2) {
1062 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
1063 }
1064
1068 if (!ath9k_hw_set_4k_power_per_rate_table(ah, chan,
1065 ath9k_hw_set_4k_power_per_rate_table(ah, chan,
1069 &ratesArray[0], cfgCtl,
1070 twiceAntennaReduction,
1071 twiceMaxRegulatoryPower,
1066 &ratesArray[0], cfgCtl,
1067 twiceAntennaReduction,
1068 twiceMaxRegulatoryPower,
1072 powerLimit)) {
1073 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1074 "ath9k_hw_set_txpower: unable to set "
1075 "tx power per rate table\n");
1076 return -EIO;
1077 }
1069 powerLimit);
1078
1070
1079 if (!ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset)) {
1080 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1081 "ath9k_hw_set_txpower: unable to set power table\n");
1082 return -EIO;
1083 }
1071 ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset);
1084
1085 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1086 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
1087 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
1088 ratesArray[i] = AR5416_MAX_RATE_POWER;
1089 }
1090
1091 if (AR_SREV_9280_10_OR_LATER(ah)) {

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1163 i = rateHt20_0;
1164
1165 if (AR_SREV_9280_10_OR_LATER(ah))
1166 ah->regulatory.max_power_level =
1167 ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
1168 else
1169 ah->regulatory.max_power_level = ratesArray[i];
1170
1072
1073 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1074 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
1075 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
1076 ratesArray[i] = AR5416_MAX_RATE_POWER;
1077 }
1078
1079 if (AR_SREV_9280_10_OR_LATER(ah)) {

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1151 i = rateHt20_0;
1152
1153 if (AR_SREV_9280_10_OR_LATER(ah))
1154 ah->regulatory.max_power_level =
1155 ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
1156 else
1157 ah->regulatory.max_power_level = ratesArray[i];
1158
1171 return 0;
1172}
1173
1174static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
1175 struct ath9k_channel *chan)
1176{
1177 struct modal_eep_4k_header *pModal;
1178 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1179 u8 biaslevel;

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2098 while (k < AR5416_NUM_PDADC_VALUES) {
2099 pPDADCValues[k] = pPDADCValues[k - 1];
2100 k++;
2101 }
2102
2103 return;
2104}
2105
1159}
1160
1161static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
1162 struct ath9k_channel *chan)
1163{
1164 struct modal_eep_4k_header *pModal;
1165 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1166 u8 biaslevel;

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2085 while (k < AR5416_NUM_PDADC_VALUES) {
2086 pPDADCValues[k] = pPDADCValues[k - 1];
2087 k++;
2088 }
2089
2090 return;
2091}
2092
2106static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
2093static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
2107 struct ath9k_channel *chan,
2108 int16_t *pTxPowerIndexOffset)
2109{
2110#define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
2111#define SM_PDGAIN_B(x, y) \
2112 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
2113
2114 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;

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2250 pdadcValues[4 * j + 3]);
2251
2252 regOffset += 4;
2253 }
2254 }
2255 }
2256
2257 *pTxPowerIndexOffset = 0;
2094 struct ath9k_channel *chan,
2095 int16_t *pTxPowerIndexOffset)
2096{
2097#define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
2098#define SM_PDGAIN_B(x, y) \
2099 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
2100
2101 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;

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2237 pdadcValues[4 * j + 3]);
2238
2239 regOffset += 4;
2240 }
2241 }
2242 }
2243
2244 *pTxPowerIndexOffset = 0;
2258
2259 return true;
2260#undef SM_PD_GAIN
2261#undef SM_PDGAIN_B
2262}
2263
2245#undef SM_PD_GAIN
2246#undef SM_PDGAIN_B
2247}
2248
2264static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
2249static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
2265 struct ath9k_channel *chan,
2266 int16_t *ratesArray,
2267 u16 cfgCtl,
2268 u16 AntennaReduction,
2269 u16 twiceMaxRegulatoryPower,
2270 u16 powerLimit)
2271{
2272#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */

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2544 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
2545 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
2546 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
2547 if (IS_CHAN_2GHZ(chan)) {
2548 ratesArray[rateExtCck] =
2549 targetPowerCckExt.tPow2x[0];
2550 }
2551 }
2250 struct ath9k_channel *chan,
2251 int16_t *ratesArray,
2252 u16 cfgCtl,
2253 u16 AntennaReduction,
2254 u16 twiceMaxRegulatoryPower,
2255 u16 powerLimit)
2256{
2257#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */

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2529 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
2530 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
2531 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
2532 if (IS_CHAN_2GHZ(chan)) {
2533 ratesArray[rateExtCck] =
2534 targetPowerCckExt.tPow2x[0];
2535 }
2536 }
2552 return true;
2553}
2554
2537}
2538
2555static int ath9k_hw_def_set_txpower(struct ath_hw *ah,
2539static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
2556 struct ath9k_channel *chan,
2557 u16 cfgCtl,
2558 u8 twiceAntennaReduction,
2559 u8 twiceMaxRegulatoryPower,
2560 u8 powerLimit)
2561{
2562#define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
2563 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;

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2570
2571 memset(ratesArray, 0, sizeof(ratesArray));
2572
2573 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
2574 AR5416_EEP_MINOR_VER_2) {
2575 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
2576 }
2577
2540 struct ath9k_channel *chan,
2541 u16 cfgCtl,
2542 u8 twiceAntennaReduction,
2543 u8 twiceMaxRegulatoryPower,
2544 u8 powerLimit)
2545{
2546#define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
2547 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;

--- 6 unchanged lines hidden (view full) ---

2554
2555 memset(ratesArray, 0, sizeof(ratesArray));
2556
2557 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
2558 AR5416_EEP_MINOR_VER_2) {
2559 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
2560 }
2561
2578 if (!ath9k_hw_set_def_power_per_rate_table(ah, chan,
2562 ath9k_hw_set_def_power_per_rate_table(ah, chan,
2579 &ratesArray[0], cfgCtl,
2580 twiceAntennaReduction,
2581 twiceMaxRegulatoryPower,
2563 &ratesArray[0], cfgCtl,
2564 twiceAntennaReduction,
2565 twiceMaxRegulatoryPower,
2582 powerLimit)) {
2583 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2584 "ath9k_hw_set_txpower: unable to set "
2585 "tx power per rate table\n");
2586 return -EIO;
2587 }
2566 powerLimit);
2588
2567
2589 if (!ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset)) {
2590 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2591 "ath9k_hw_set_txpower: unable to set power table\n");
2592 return -EIO;
2593 }
2568 ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset);
2594
2595 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
2596 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
2597 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
2598 ratesArray[i] = AR5416_MAX_RATE_POWER;
2599 }
2600
2601 if (AR_SREV_9280_10_OR_LATER(ah)) {

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2712 case 3:
2713 ah->regulatory.max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
2714 break;
2715 default:
2716 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2717 "Invalid chainmask configuration\n");
2718 break;
2719 }
2569
2570 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
2571 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
2572 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
2573 ratesArray[i] = AR5416_MAX_RATE_POWER;
2574 }
2575
2576 if (AR_SREV_9280_10_OR_LATER(ah)) {

--- 110 unchanged lines hidden (view full) ---

2687 case 3:
2688 ah->regulatory.max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
2689 break;
2690 default:
2691 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2692 "Invalid chainmask configuration\n");
2693 break;
2694 }
2720
2721 return 0;
2722}
2723
2724static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah,
2725 enum ieee80211_band freq_band)
2726{
2727 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
2728 struct modal_eep_header *pModal =
2729 &(eep->modalHeader[ATH9K_HAL_FREQ_BAND_2GHZ == freq_band]);

--- 84 unchanged lines hidden --- 		2695}
2696
2697static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah,
2698 enum ieee80211_band freq_band)
2699{
2700 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
2701 struct modal_eep_header *pModal =
2702 &(eep->modalHeader[ATH9K_HAL_FREQ_BAND_2GHZ == freq_band]);

--- 84 unchanged lines hidden ---