calib.c (379f04407c92d84f2506385b66fb9fc89ecd96c3) calib.c (cbfe946860ffc718c5d99a6b740e33ac95fe8b8d)
1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

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181 BUG_ON(1);
182 return false;
183 }
184
185 return true;
186}
187
188static void ath9k_hw_setup_calibration(struct ath_hw *ah,
1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

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181 BUG_ON(1);
182 return false;
183 }
184
185 return true;
186}
187
188static void ath9k_hw_setup_calibration(struct ath_hw *ah,
189 struct hal_cal_list *currCal)
189 struct ath9k_cal_list *currCal)
190{
191 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
192 AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
193 currCal->calData->calCountMax);
194
195 switch (currCal->calData->calType) {
196 case IQ_MISMATCH_CAL:
197 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);

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215 break;
216 }
217
218 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
219 AR_PHY_TIMING_CTRL4_DO_CAL);
220}
221
222static void ath9k_hw_reset_calibration(struct ath_hw *ah,
190{
191 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
192 AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
193 currCal->calData->calCountMax);
194
195 switch (currCal->calData->calType) {
196 case IQ_MISMATCH_CAL:
197 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);

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215 break;
216 }
217
218 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
219 AR_PHY_TIMING_CTRL4_DO_CAL);
220}
221
222static void ath9k_hw_reset_calibration(struct ath_hw *ah,
223 struct hal_cal_list *currCal)
223 struct ath9k_cal_list *currCal)
224{
225 int i;
226
227 ath9k_hw_setup_calibration(ah, currCal);
228
229 currCal->calState = CAL_RUNNING;
230
231 for (i = 0; i < AR5416_MAX_CHAINS; i++) {

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236 }
237
238 ah->cal_samples = 0;
239}
240
241static bool ath9k_hw_per_calibration(struct ath_hw *ah,
242 struct ath9k_channel *ichan,
243 u8 rxchainmask,
224{
225 int i;
226
227 ath9k_hw_setup_calibration(ah, currCal);
228
229 currCal->calState = CAL_RUNNING;
230
231 for (i = 0; i < AR5416_MAX_CHAINS; i++) {

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236 }
237
238 ah->cal_samples = 0;
239}
240
241static bool ath9k_hw_per_calibration(struct ath_hw *ah,
242 struct ath9k_channel *ichan,
243 u8 rxchainmask,
244 struct hal_cal_list *currCal)
244 struct ath9k_cal_list *currCal)
245{
246 bool iscaldone = false;
247
248 if (currCal->calState == CAL_RUNNING) {
249 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
250 AR_PHY_TIMING_CTRL4_DO_CAL)) {
251
252 currCal->calData->calCollect(ah);

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271 ath9k_hw_reset_calibration(ah, currCal);
272 }
273
274 return iscaldone;
275}
276
277/* Assumes you are talking about the currently configured channel */
278static bool ath9k_hw_iscal_supported(struct ath_hw *ah,
245{
246 bool iscaldone = false;
247
248 if (currCal->calState == CAL_RUNNING) {
249 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
250 AR_PHY_TIMING_CTRL4_DO_CAL)) {
251
252 currCal->calData->calCollect(ah);

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271 ath9k_hw_reset_calibration(ah, currCal);
272 }
273
274 return iscaldone;
275}
276
277/* Assumes you are talking about the currently configured channel */
278static bool ath9k_hw_iscal_supported(struct ath_hw *ah,
279 enum hal_cal_types calType)
279 enum ath9k_cal_types calType)
280{
281 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
282
283 switch (calType & ah->supp_cals) {
284 case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
285 return true;
286 case ADC_GAIN_CAL:
287 case ADC_DC_CAL:

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494 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
495 AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
496}
497
498static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
499{
500 u32 iOddMeasOffset, iEvenMeasOffset, val, i;
501 int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
280{
281 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
282
283 switch (calType & ah->supp_cals) {
284 case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
285 return true;
286 case ADC_GAIN_CAL:
287 case ADC_DC_CAL:

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494 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
495 AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
496}
497
498static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
499{
500 u32 iOddMeasOffset, iEvenMeasOffset, val, i;
501 int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
502 const struct hal_percal_data *calData =
502 const struct ath9k_percal_data *calData =
503 ah->cal_list_curr->calData;
504 u32 numSamples =
505 (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
506
507 for (i = 0; i < numChains; i++) {
508 iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i];
509 iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i];
510 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];

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551 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
552 AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
553}
554
555/* This is done for the currently configured channel */
556bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
557{
558 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
503 ah->cal_list_curr->calData;
504 u32 numSamples =
505 (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
506
507 for (i = 0; i < numChains; i++) {
508 iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i];
509 iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i];
510 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];

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551 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
552 AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
553}
554
555/* This is done for the currently configured channel */
556bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
557{
558 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
559 struct hal_cal_list *currCal = ah->cal_list_curr;
559 struct ath9k_cal_list *currCal = ah->cal_list_curr;
560
561 if (!ah->curchan)
562 return true;
563
564 if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah))
565 return true;
566
567 if (currCal == NULL)

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840 REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
841
842}
843
844bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
845 u8 rxchainmask, bool longcal)
846{
847 bool iscaldone = true;
560
561 if (!ah->curchan)
562 return true;
563
564 if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah))
565 return true;
566
567 if (currCal == NULL)

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840 REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
841
842}
843
844bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
845 u8 rxchainmask, bool longcal)
846{
847 bool iscaldone = true;
848 struct hal_cal_list *currCal = ah->cal_list_curr;
848 struct ath9k_cal_list *currCal = ah->cal_list_curr;
849
850 if (currCal &&
851 (currCal->calState == CAL_RUNNING ||
852 currCal->calState == CAL_WAITING)) {
853 iscaldone = ath9k_hw_per_calibration(ah, chan,
854 rxchainmask, currCal);
855 if (iscaldone) {
856 ah->cal_list_curr = currCal = currCal->calNext;

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1003 ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
1004 }
1005
1006 chan->CalValid = 0;
1007
1008 return true;
1009}
1010
849
850 if (currCal &&
851 (currCal->calState == CAL_RUNNING ||
852 currCal->calState == CAL_WAITING)) {
853 iscaldone = ath9k_hw_per_calibration(ah, chan,
854 rxchainmask, currCal);
855 if (iscaldone) {
856 ah->cal_list_curr = currCal = currCal->calNext;

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1003 ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
1004 }
1005
1006 chan->CalValid = 0;
1007
1008 return true;
1009}
1010
1011const struct hal_percal_data iq_cal_multi_sample = {
1011const struct ath9k_percal_data iq_cal_multi_sample = {
1012 IQ_MISMATCH_CAL,
1013 MAX_CAL_SAMPLES,
1014 PER_MIN_LOG_COUNT,
1015 ath9k_hw_iqcal_collect,
1016 ath9k_hw_iqcalibrate
1017};
1012 IQ_MISMATCH_CAL,
1013 MAX_CAL_SAMPLES,
1014 PER_MIN_LOG_COUNT,
1015 ath9k_hw_iqcal_collect,
1016 ath9k_hw_iqcalibrate
1017};
1018const struct hal_percal_data iq_cal_single_sample = {
1018const struct ath9k_percal_data iq_cal_single_sample = {
1019 IQ_MISMATCH_CAL,
1020 MIN_CAL_SAMPLES,
1021 PER_MAX_LOG_COUNT,
1022 ath9k_hw_iqcal_collect,
1023 ath9k_hw_iqcalibrate
1024};
1019 IQ_MISMATCH_CAL,
1020 MIN_CAL_SAMPLES,
1021 PER_MAX_LOG_COUNT,
1022 ath9k_hw_iqcal_collect,
1023 ath9k_hw_iqcalibrate
1024};
1025const struct hal_percal_data adc_gain_cal_multi_sample = {
1025const struct ath9k_percal_data adc_gain_cal_multi_sample = {
1026 ADC_GAIN_CAL,
1027 MAX_CAL_SAMPLES,
1028 PER_MIN_LOG_COUNT,
1029 ath9k_hw_adc_gaincal_collect,
1030 ath9k_hw_adc_gaincal_calibrate
1031};
1026 ADC_GAIN_CAL,
1027 MAX_CAL_SAMPLES,
1028 PER_MIN_LOG_COUNT,
1029 ath9k_hw_adc_gaincal_collect,
1030 ath9k_hw_adc_gaincal_calibrate
1031};
1032const struct hal_percal_data adc_gain_cal_single_sample = {
1032const struct ath9k_percal_data adc_gain_cal_single_sample = {
1033 ADC_GAIN_CAL,
1034 MIN_CAL_SAMPLES,
1035 PER_MAX_LOG_COUNT,
1036 ath9k_hw_adc_gaincal_collect,
1037 ath9k_hw_adc_gaincal_calibrate
1038};
1033 ADC_GAIN_CAL,
1034 MIN_CAL_SAMPLES,
1035 PER_MAX_LOG_COUNT,
1036 ath9k_hw_adc_gaincal_collect,
1037 ath9k_hw_adc_gaincal_calibrate
1038};
1039const struct hal_percal_data adc_dc_cal_multi_sample = {
1039const struct ath9k_percal_data adc_dc_cal_multi_sample = {
1040 ADC_DC_CAL,
1041 MAX_CAL_SAMPLES,
1042 PER_MIN_LOG_COUNT,
1043 ath9k_hw_adc_dccal_collect,
1044 ath9k_hw_adc_dccal_calibrate
1045};
1040 ADC_DC_CAL,
1041 MAX_CAL_SAMPLES,
1042 PER_MIN_LOG_COUNT,
1043 ath9k_hw_adc_dccal_collect,
1044 ath9k_hw_adc_dccal_calibrate
1045};
1046const struct hal_percal_data adc_dc_cal_single_sample = {
1046const struct ath9k_percal_data adc_dc_cal_single_sample = {
1047 ADC_DC_CAL,
1048 MIN_CAL_SAMPLES,
1049 PER_MAX_LOG_COUNT,
1050 ath9k_hw_adc_dccal_collect,
1051 ath9k_hw_adc_dccal_calibrate
1052};
1047 ADC_DC_CAL,
1048 MIN_CAL_SAMPLES,
1049 PER_MAX_LOG_COUNT,
1050 ath9k_hw_adc_dccal_collect,
1051 ath9k_hw_adc_dccal_calibrate
1052};
1053const struct hal_percal_data adc_init_dc_cal = {
1053const struct ath9k_percal_data adc_init_dc_cal = {
1054 ADC_DC_INIT_CAL,
1055 MIN_CAL_SAMPLES,
1056 INIT_LOG_COUNT,
1057 ath9k_hw_adc_dccal_collect,
1058 ath9k_hw_adc_dccal_calibrate
1059};
1054 ADC_DC_INIT_CAL,
1055 MIN_CAL_SAMPLES,
1056 INIT_LOG_COUNT,
1057 ath9k_hw_adc_dccal_collect,
1058 ath9k_hw_adc_dccal_calibrate
1059};