reset.c (1846ac3dbec0894095520b2756b68c4fd81e3fbb) reset.c (c47faa364cfb249d5d7670fb7293a6f9acd8aa9e)
1/*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
5 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 *
8 * Permission to use, copy, modify, and distribute this software for any

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14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 *
20 */
21
1/*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
5 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 *
8 * Permission to use, copy, modify, and distribute this software for any

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14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 *
20 */
21
22/*****************************\
23 Reset functions and helpers
24\*****************************/
22/****************************\
23 Reset function and helpers
24\****************************/
25
26#include <asm/unaligned.h>
27
28#include <linux/pci.h> /* To determine if a card is pci-e */
29#include <linux/log2.h>
30#include <linux/platform_device.h>
31#include "ath5k.h"
32#include "reg.h"
33#include "debug.h"
34
35
25
26#include <asm/unaligned.h>
27
28#include <linux/pci.h> /* To determine if a card is pci-e */
29#include <linux/log2.h>
30#include <linux/platform_device.h>
31#include "ath5k.h"
32#include "reg.h"
33#include "debug.h"
34
35
36/**
37 * DOC: Reset function and helpers
38 *
39 * Here we implement the main reset routine, used to bring the card
40 * to a working state and ready to receive. We also handle routines
41 * that don't fit on other places such as clock, sleep and power control
42 */
43
44
36/******************\
37* Helper functions *
38\******************/
39
45/******************\
46* Helper functions *
47\******************/
48
40/*
41 * Check if a register write has been completed
49/**
50 * ath5k_hw_register_timeout() - Poll a register for a flag/field change
51 * @ah: The &struct ath5k_hw
52 * @reg: The register to read
53 * @flag: The flag/field to check on the register
54 * @val: The field value we expect (if we check a field)
55 * @is_set: Instead of checking if the flag got cleared, check if it got set
56 *
57 * Some registers contain flags that indicate that an operation is
58 * running. We use this function to poll these registers and check
59 * if these flags get cleared. We also use it to poll a register
60 * field (containing multiple flags) until it gets a specific value.
61 *
62 * Returns -EAGAIN if we exceeded AR5K_TUNE_REGISTER_TIMEOUT * 15us or 0
42 */
63 */
43int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
64int
65ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
44 bool is_set)
45{
46 int i;
47 u32 data;
48
49 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
50 data = ath5k_hw_reg_read(ah, reg);
51 if (is_set && (data & flag))

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59}
60
61
62/*************************\
63* Clock related functions *
64\*************************/
65
66/**
66 bool is_set)
67{
68 int i;
69 u32 data;
70
71 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
72 data = ath5k_hw_reg_read(ah, reg);
73 if (is_set && (data & flag))

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81}
82
83
84/*************************\
85* Clock related functions *
86\*************************/
87
88/**
67 * ath5k_hw_htoclock - Translate usec to hw clock units
68 *
89 * ath5k_hw_htoclock() - Translate usec to hw clock units
69 * @ah: The &struct ath5k_hw
70 * @usec: value in microseconds
90 * @ah: The &struct ath5k_hw
91 * @usec: value in microseconds
92 *
93 * Translate usecs to hw clock units based on the current
94 * hw clock rate.
95 *
96 * Returns number of clock units
71 */
97 */
72unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec)
98unsigned int
99ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec)
73{
74 struct ath_common *common = ath5k_hw_common(ah);
75 return usec * common->clockrate;
76}
77
78/**
100{
101 struct ath_common *common = ath5k_hw_common(ah);
102 return usec * common->clockrate;
103}
104
105/**
79 * ath5k_hw_clocktoh - Translate hw clock units to usec
106 * ath5k_hw_clocktoh() - Translate hw clock units to usec
107 * @ah: The &struct ath5k_hw
80 * @clock: value in hw clock units
108 * @clock: value in hw clock units
109 *
110 * Translate hw clock units to usecs based on the current
111 * hw clock rate.
112 *
113 * Returns number of usecs
81 */
114 */
82unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock)
115unsigned int
116ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock)
83{
84 struct ath_common *common = ath5k_hw_common(ah);
85 return clock / common->clockrate;
86}
87
88/**
117{
118 struct ath_common *common = ath5k_hw_common(ah);
119 return clock / common->clockrate;
120}
121
122/**
89 * ath5k_hw_init_core_clock - Initialize core clock
123 * ath5k_hw_init_core_clock() - Initialize core clock
124 * @ah: The &struct ath5k_hw
90 *
125 *
91 * @ah The &struct ath5k_hw
92 *
93 * Initialize core clock parameters (usec, usec32, latencies etc).
126 * Initialize core clock parameters (usec, usec32, latencies etc),
127 * based on current bwmode and chipset properties.
94 */
128 */
95static void ath5k_hw_init_core_clock(struct ath5k_hw *ah)
129static void
130ath5k_hw_init_core_clock(struct ath5k_hw *ah)
96{
97 struct ieee80211_channel *channel = ah->ah_current_channel;
98 struct ath_common *common = ath5k_hw_common(ah);
99 u32 usec_reg, txlat, rxlat, usec, clock, sclock, txf2txs;
100
101 /*
102 * Set core clock frequency
103 */

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222 /* On 5112 set tx frame to tx data start delay */
223 if (ah->ah_radio == AR5K_RF5112) {
224 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL2,
225 AR5K_PHY_RF_CTL2_TXF2TXD_START,
226 txf2txs);
227 }
228}
229
131{
132 struct ieee80211_channel *channel = ah->ah_current_channel;
133 struct ath_common *common = ath5k_hw_common(ah);
134 u32 usec_reg, txlat, rxlat, usec, clock, sclock, txf2txs;
135
136 /*
137 * Set core clock frequency
138 */

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257 /* On 5112 set tx frame to tx data start delay */
258 if (ah->ah_radio == AR5K_RF5112) {
259 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL2,
260 AR5K_PHY_RF_CTL2_TXF2TXD_START,
261 txf2txs);
262 }
263}
264
230/*
265/**
266 * ath5k_hw_set_sleep_clock() - Setup sleep clock operation
267 * @ah: The &struct ath5k_hw
268 * @enable: Enable sleep clock operation (false to disable)
269 *
231 * If there is an external 32KHz crystal available, use it
232 * as ref. clock instead of 32/40MHz clock and baseband clocks
233 * to save power during sleep or restore normal 32/40MHz
234 * operation.
235 *
270 * If there is an external 32KHz crystal available, use it
271 * as ref. clock instead of 32/40MHz clock and baseband clocks
272 * to save power during sleep or restore normal 32/40MHz
273 * operation.
274 *
236 * XXX: When operating on 32KHz certain PHY registers (27 - 31,
237 * 123 - 127) require delay on access.
275 * NOTE: When operating on 32KHz certain PHY registers (27 - 31,
276 * 123 - 127) require delay on access.
238 */
277 */
239static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
278static void
279ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
240{
241 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
242 u32 scal, spending, sclock;
243
244 /* Only set 32KHz settings if we have an external
245 * 32KHz crystal present */
246 if ((AR5K_EEPROM_HAS32KHZCRYSTAL(ee->ee_misc1) ||
247 AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(ee->ee_misc1)) &&

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335 }
336}
337
338
339/*********************\
340* Reset/Sleep control *
341\*********************/
342
280{
281 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
282 u32 scal, spending, sclock;
283
284 /* Only set 32KHz settings if we have an external
285 * 32KHz crystal present */
286 if ((AR5K_EEPROM_HAS32KHZCRYSTAL(ee->ee_misc1) ||
287 AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(ee->ee_misc1)) &&

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375 }
376}
377
378
379/*********************\
380* Reset/Sleep control *
381\*********************/
382
343/*
344 * Reset chipset
383/**
384 * ath5k_hw_nic_reset() - Reset the various chipset units
385 * @ah: The &struct ath5k_hw
386 * @val: Mask to indicate what units to reset
387 *
388 * To reset the various chipset units we need to write
389 * the mask to AR5K_RESET_CTL and poll the register until
390 * all flags are cleared.
391 *
392 * Returns 0 if we are O.K. or -EAGAIN (from athk5_hw_register_timeout)
345 */
393 */
346static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
394static int
395ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
347{
348 int ret;
349 u32 mask = val ? val : ~0U;
350
351 /* Read-and-clear RX Descriptor Pointer*/
352 ath5k_hw_reg_read(ah, AR5K_RXDP);
353
354 /*

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377 * AR5K_INIT_CFG.
378 */
379 if ((val & AR5K_RESET_CTL_PCU) == 0)
380 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
381
382 return ret;
383}
384
396{
397 int ret;
398 u32 mask = val ? val : ~0U;
399
400 /* Read-and-clear RX Descriptor Pointer*/
401 ath5k_hw_reg_read(ah, AR5K_RXDP);
402
403 /*

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426 * AR5K_INIT_CFG.
427 */
428 if ((val & AR5K_RESET_CTL_PCU) == 0)
429 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
430
431 return ret;
432}
433
385/*
386 * Reset AHB chipset
387 * AR5K_RESET_CTL_PCU flag resets WMAC
388 * AR5K_RESET_CTL_BASEBAND flag resets WBB
434/**
435 * ath5k_hw_wisoc_reset() - Reset AHB chipset
436 * @ah: The &struct ath5k_hw
437 * @flags: Mask to indicate what units to reset
438 *
439 * Same as ath5k_hw_nic_reset but for AHB based devices
440 *
441 * Returns 0 if we are O.K. or -EAGAIN (from athk5_hw_register_timeout)
389 */
442 */
390static int ath5k_hw_wisoc_reset(struct ath5k_hw *ah, u32 flags)
443static int
444ath5k_hw_wisoc_reset(struct ath5k_hw *ah, u32 flags)
391{
392 u32 mask = flags ? flags : ~0U;
393 u32 __iomem *reg;
394 u32 regval;
395 u32 val = 0;
396
397 /* ah->ah_mac_srev is not available at this point yet */
398 if (ah->devid >= AR5K_SREV_AR2315_R6) {

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434 * AR5K_INIT_CFG.
435 */
436 if ((flags & AR5K_RESET_CTL_PCU) == 0)
437 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
438
439 return 0;
440}
441
445{
446 u32 mask = flags ? flags : ~0U;
447 u32 __iomem *reg;
448 u32 regval;
449 u32 val = 0;
450
451 /* ah->ah_mac_srev is not available at this point yet */
452 if (ah->devid >= AR5K_SREV_AR2315_R6) {

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488 * AR5K_INIT_CFG.
489 */
490 if ((flags & AR5K_RESET_CTL_PCU) == 0)
491 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
492
493 return 0;
494}
495
442
443/*
444 * Sleep control
496/**
497 * ath5k_hw_set_power_mode() - Set power mode
498 * @ah: The &struct ath5k_hw
499 * @mode: One of enum ath5k_power_mode
500 * @set_chip: Set to true to write sleep control register
501 * @sleep_duration: How much time the device is allowed to sleep
502 * when sleep logic is enabled (in 128 microsecond increments).
503 *
504 * This function is used to configure sleep policy and allowed
505 * sleep modes. For more information check out the sleep control
506 * register on reg.h and STA_ID1.
507 *
508 * Returns 0 on success, -EIO if chip didn't wake up or -EINVAL if an invalid
509 * mode is requested.
445 */
510 */
446static int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
511static int
512ath5k_hw_set_power_mode(struct ath5k_hw *ah, enum ath5k_power_mode mode,
447 bool set_chip, u16 sleep_duration)
448{
449 unsigned int i;
450 u32 staid, data;
451
452 staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
453
454 switch (mode) {

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518 }
519
520commit:
521 ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1);
522
523 return 0;
524}
525
513 bool set_chip, u16 sleep_duration)
514{
515 unsigned int i;
516 u32 staid, data;
517
518 staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
519
520 switch (mode) {

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584 }
585
586commit:
587 ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1);
588
589 return 0;
590}
591
526/*
527 * Put device on hold
592/**
593 * ath5k_hw_on_hold() - Put device on hold
594 * @ah: The &struct ath5k_hw
528 *
595 *
529 * Put MAC and Baseband on warm reset and
530 * keep that state (don't clean sleep control
531 * register). After this MAC and Baseband are
532 * disabled and a full reset is needed to come
533 * back. This way we save as much power as possible
596 * Put MAC and Baseband on warm reset and keep that state
597 * (don't clean sleep control register). After this MAC
598 * and Baseband are disabled and a full reset is needed
599 * to come back. This way we save as much power as possible
534 * without putting the card on full sleep.
600 * without putting the card on full sleep.
601 *
602 * Returns 0 on success or -EIO on error
535 */
603 */
536int ath5k_hw_on_hold(struct ath5k_hw *ah)
604int
605ath5k_hw_on_hold(struct ath5k_hw *ah)
537{
538 struct pci_dev *pdev = ah->pdev;
539 u32 bus_flags;
540 int ret;
541
542 if (ath5k_get_bus_type(ah) == ATH_AHB)
543 return 0;
544
545 /* Make sure device is awake */
606{
607 struct pci_dev *pdev = ah->pdev;
608 u32 bus_flags;
609 int ret;
610
611 if (ath5k_get_bus_type(ah) == ATH_AHB)
612 return 0;
613
614 /* Make sure device is awake */
546 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
615 ret = ath5k_hw_set_power_mode(ah, AR5K_PM_AWAKE, true, 0);
547 if (ret) {
548 ATH5K_ERR(ah, "failed to wakeup the MAC Chip\n");
549 return ret;
550 }
551
552 /*
553 * Put chipset on warm reset...
554 *

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570 }
571
572 if (ret) {
573 ATH5K_ERR(ah, "failed to put device on warm reset\n");
574 return -EIO;
575 }
576
577 /* ...wakeup again!*/
616 if (ret) {
617 ATH5K_ERR(ah, "failed to wakeup the MAC Chip\n");
618 return ret;
619 }
620
621 /*
622 * Put chipset on warm reset...
623 *

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639 }
640
641 if (ret) {
642 ATH5K_ERR(ah, "failed to put device on warm reset\n");
643 return -EIO;
644 }
645
646 /* ...wakeup again!*/
578 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
647 ret = ath5k_hw_set_power_mode(ah, AR5K_PM_AWAKE, true, 0);
579 if (ret) {
580 ATH5K_ERR(ah, "failed to put device on hold\n");
581 return ret;
582 }
583
584 return ret;
585}
586
648 if (ret) {
649 ATH5K_ERR(ah, "failed to put device on hold\n");
650 return ret;
651 }
652
653 return ret;
654}
655
587/*
656/**
657 * ath5k_hw_nic_wakeup() - Force card out of sleep
658 * @ah: The &struct ath5k_hw
659 * @channel: The &struct ieee80211_channel
660 *
588 * Bring up MAC + PHY Chips and program PLL
661 * Bring up MAC + PHY Chips and program PLL
589 * Channel is NULL for the initial wakeup.
662 * NOTE: Channel is NULL for the initial wakeup.
663 *
664 * Returns 0 on success, -EIO on hw failure or -EINVAL for false channel infos
590 */
665 */
591int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel)
666int
667ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel)
592{
593 struct pci_dev *pdev = ah->pdev;
594 u32 turbo, mode, clock, bus_flags;
595 int ret;
596
597 turbo = 0;
598 mode = 0;
599 clock = 0;
600
601 if ((ath5k_get_bus_type(ah) != ATH_AHB) || channel) {
602 /* Wakeup the device */
668{
669 struct pci_dev *pdev = ah->pdev;
670 u32 turbo, mode, clock, bus_flags;
671 int ret;
672
673 turbo = 0;
674 mode = 0;
675 clock = 0;
676
677 if ((ath5k_get_bus_type(ah) != ATH_AHB) || channel) {
678 /* Wakeup the device */
603 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
679 ret = ath5k_hw_set_power_mode(ah, AR5K_PM_AWAKE, true, 0);
604 if (ret) {
605 ATH5K_ERR(ah, "failed to wakeup the MAC Chip\n");
606 return ret;
607 }
608 }
609
610 /*
611 * Put chipset on warm reset...

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632 }
633
634 if (ret) {
635 ATH5K_ERR(ah, "failed to reset the MAC Chip\n");
636 return -EIO;
637 }
638
639 /* ...wakeup again!...*/
680 if (ret) {
681 ATH5K_ERR(ah, "failed to wakeup the MAC Chip\n");
682 return ret;
683 }
684 }
685
686 /*
687 * Put chipset on warm reset...

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708 }
709
710 if (ret) {
711 ATH5K_ERR(ah, "failed to reset the MAC Chip\n");
712 return -EIO;
713 }
714
715 /* ...wakeup again!...*/
640 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
716 ret = ath5k_hw_set_power_mode(ah, AR5K_PM_AWAKE, true, 0);
641 if (ret) {
642 ATH5K_ERR(ah, "failed to resume the MAC Chip\n");
643 return ret;
644 }
645
646 /* ...reset configuration register on Wisoc ...
647 * ...clear reset control register and pull device out of
648 * warm reset on others */

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750 return 0;
751}
752
753
754/**************************************\
755* Post-initvals register modifications *
756\**************************************/
757
717 if (ret) {
718 ATH5K_ERR(ah, "failed to resume the MAC Chip\n");
719 return ret;
720 }
721
722 /* ...reset configuration register on Wisoc ...
723 * ...clear reset control register and pull device out of
724 * warm reset on others */

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826 return 0;
827}
828
829
830/**************************************\
831* Post-initvals register modifications *
832\**************************************/
833
758/* TODO: Half/Quarter rate */
759static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
834/**
835 * ath5k_hw_tweak_initval_settings() - Tweak initial settings
836 * @ah: The &struct ath5k_hw
837 * @channel: The &struct ieee80211_channel
838 *
839 * Some settings are not handled on initvals, e.g. bwmode
840 * settings, some phy settings, workarounds etc that in general
841 * don't fit anywhere else or are too small to introduce a separate
842 * function for each one. So we have this function to handle
843 * them all during reset and complete card's initialization.
844 */
845static void
846ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
760 struct ieee80211_channel *channel)
761{
762 if (ah->ah_version == AR5K_AR5212 &&
763 ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
764
765 /* Setup ADC control */
766 ath5k_hw_reg_write(ah,
767 (AR5K_REG_SM(2,

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870 }
871 } else if (ah->ah_version == AR5K_AR5210) {
872 /* Set Frame Control Register for normal operation */
873 ath5k_hw_reg_write(ah, (AR5K_PHY_FRAME_CTL_INI | 0x1020),
874 AR5K_PHY_FRAME_CTL_5210);
875 }
876}
877
847 struct ieee80211_channel *channel)
848{
849 if (ah->ah_version == AR5K_AR5212 &&
850 ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
851
852 /* Setup ADC control */
853 ath5k_hw_reg_write(ah,
854 (AR5K_REG_SM(2,

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957 }
958 } else if (ah->ah_version == AR5K_AR5210) {
959 /* Set Frame Control Register for normal operation */
960 ath5k_hw_reg_write(ah, (AR5K_PHY_FRAME_CTL_INI | 0x1020),
961 AR5K_PHY_FRAME_CTL_5210);
962 }
963}
964
878static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
965/**
966 * ath5k_hw_commit_eeprom_settings() - Commit settings from EEPROM
967 * @ah: The &struct ath5k_hw
968 * @channel: The &struct ieee80211_channel
969 *
970 * Use settings stored on EEPROM to properly initialize the card
971 * based on various infos and per-mode calibration data.
972 */
973static void
974ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
879 struct ieee80211_channel *channel)
880{
881 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
882 s16 cck_ofdm_pwr_delta;
883 u8 ee_mode;
884
885 /* TODO: Add support for AR5210 EEPROM */
886 if (ah->ah_version == AR5K_AR5210)

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1024 ath5k_hw_reg_write(ah, 0, AR5K_PHY_HEAVY_CLIP_ENABLE);
1025}
1026
1027
1028/*********************\
1029* Main reset function *
1030\*********************/
1031
975 struct ieee80211_channel *channel)
976{
977 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
978 s16 cck_ofdm_pwr_delta;
979 u8 ee_mode;
980
981 /* TODO: Add support for AR5210 EEPROM */
982 if (ah->ah_version == AR5K_AR5210)

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1120 ath5k_hw_reg_write(ah, 0, AR5K_PHY_HEAVY_CLIP_ENABLE);
1121}
1122
1123
1124/*********************\
1125* Main reset function *
1126\*********************/
1127
1032int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1128/**
1129 * ath5k_hw_reset() - The main reset function
1130 * @ah: The &struct ath5k_hw
1131 * @op_mode: One of enum nl80211_iftype
1132 * @channel: The &struct ieee80211_channel
1133 * @fast: Enable fast channel switching
1134 * @skip_pcu: Skip pcu initialization
1135 *
1136 * This is the function we call each time we want to (re)initialize the
1137 * card and pass new settings to hw. We also call it when hw runs into
1138 * trouble to make it come back to a working state.
1139 *
1140 * Returns 0 on success, -EINVAL on false op_mode or channel infos, or -EIO
1141 * on failure.
1142 */
1143int
1144ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1033 struct ieee80211_channel *channel, bool fast, bool skip_pcu)
1034{
1035 u32 s_seq[10], s_led[3], tsf_up, tsf_lo;
1036 u8 mode;
1037 int i, ret;
1038
1039 tsf_up = 0;
1040 tsf_lo = 0;

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1237
1238 /* Gpio settings */
1239 ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
1240 ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
1241
1242 /*
1243 * Initialize PCU
1244 */
1145 struct ieee80211_channel *channel, bool fast, bool skip_pcu)
1146{
1147 u32 s_seq[10], s_led[3], tsf_up, tsf_lo;
1148 u8 mode;
1149 int i, ret;
1150
1151 tsf_up = 0;
1152 tsf_lo = 0;

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1349
1350 /* Gpio settings */
1351 ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
1352 ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
1353
1354 /*
1355 * Initialize PCU
1356 */
1245 ath5k_hw_pcu_init(ah, op_mode, mode);
1357 ath5k_hw_pcu_init(ah, op_mode);
1246
1247 /*
1248 * Initialize PHY
1249 */
1250 ret = ath5k_hw_phy_init(ah, channel, mode, false);
1251 if (ret) {
1252 ATH5K_ERR(ah,
1253 "failed to initialize PHY (%i) !\n", ret);

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1359 /*
1360 * Initialize PHY
1361 */
1362 ret = ath5k_hw_phy_init(ah, channel, mode, false);
1363 if (ret) {
1364 ATH5K_ERR(ah,
1365 "failed to initialize PHY (%i) !\n", ret);

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