pcu.c (d4bbf7e7759afc172e2bfbc5c416324590049cdd) pcu.c (c47faa364cfb249d5d7670fb7293a6f9acd8aa9e)
1/*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Matthew W. S. Bell <mentor@madwifi.org>
5 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
6 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
7 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
8 *

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25\*********************************/
26
27#include <asm/unaligned.h>
28
29#include "ath5k.h"
30#include "reg.h"
31#include "debug.h"
32
1/*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Matthew W. S. Bell <mentor@madwifi.org>
5 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
6 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
7 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
8 *

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25\*********************************/
26
27#include <asm/unaligned.h>
28
29#include "ath5k.h"
30#include "reg.h"
31#include "debug.h"
32
33/*
33/**
34 * DOC: Protocol Control Unit (PCU) functions
35 *
36 * Protocol control unit is responsible to maintain various protocol
37 * properties before a frame is send and after a frame is received to/from
38 * baseband. To be more specific, PCU handles:
39 *
40 * - Buffering of RX and TX frames (after QCU/DCUs)
41 *
42 * - Encrypting and decrypting (using the built-in engine)
43 *
44 * - Generating ACKs, RTS/CTS frames
45 *
46 * - Maintaining TSF
47 *
48 * - FCS
49 *
50 * - Updating beacon data (with TSF etc)
51 *
52 * - Generating virtual CCA
53 *
54 * - RX/Multicast filtering
55 *
56 * - BSSID filtering
57 *
58 * - Various statistics
59 *
60 * -Different operating modes: AP, STA, IBSS
61 *
62 * Note: Most of these functions can be tweaked/bypassed so you can do
63 * them on sw above for debugging or research. For more infos check out PCU
64 * registers on reg.h.
65 */
66
67/**
68 * DOC: ACK rates
69 *
34 * AR5212+ can use higher rates for ack transmission
35 * based on current tx rate instead of the base rate.
36 * It does this to better utilize channel usage.
70 * AR5212+ can use higher rates for ack transmission
71 * based on current tx rate instead of the base rate.
72 * It does this to better utilize channel usage.
37 * This is a mapping between G rates (that cover both
73 * There is a mapping between G rates (that cover both
38 * CCK and OFDM) and ack rates that we use when setting
39 * rate -> duration table. This mapping is hw-based so
40 * don't change anything.
41 *
42 * To enable this functionality we must set
43 * ah->ah_ack_bitrate_high to true else base rate is
44 * used (1Mb for CCK, 6Mb for OFDM).
45 */

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58/* 48Mb -> 24Mb */ 8,
59/* 54Mb -> 24Mb */ 8 };
60
61/*******************\
62* Helper functions *
63\*******************/
64
65/**
74 * CCK and OFDM) and ack rates that we use when setting
75 * rate -> duration table. This mapping is hw-based so
76 * don't change anything.
77 *
78 * To enable this functionality we must set
79 * ah->ah_ack_bitrate_high to true else base rate is
80 * used (1Mb for CCK, 6Mb for OFDM).
81 */

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94/* 48Mb -> 24Mb */ 8,
95/* 54Mb -> 24Mb */ 8 };
96
97/*******************\
98* Helper functions *
99\*******************/
100
101/**
66 * ath5k_hw_get_frame_duration - Get tx time of a frame
67 *
102 * ath5k_hw_get_frame_duration() - Get tx time of a frame
68 * @ah: The &struct ath5k_hw
69 * @len: Frame's length in bytes
70 * @rate: The @struct ieee80211_rate
103 * @ah: The &struct ath5k_hw
104 * @len: Frame's length in bytes
105 * @rate: The @struct ieee80211_rate
106 * @shortpre: Indicate short preample
71 *
72 * Calculate tx duration of a frame given it's rate and length
73 * It extends ieee80211_generic_frame_duration for non standard
74 * bwmodes.
75 */
107 *
108 * Calculate tx duration of a frame given it's rate and length
109 * It extends ieee80211_generic_frame_duration for non standard
110 * bwmodes.
111 */
76int ath5k_hw_get_frame_duration(struct ath5k_hw *ah,
112int
113ath5k_hw_get_frame_duration(struct ath5k_hw *ah,
77 int len, struct ieee80211_rate *rate, bool shortpre)
78{
79 int sifs, preamble, plcp_bits, sym_time;
80 int bitrate, bits, symbols, symbol_bits;
81 int dur;
82
83 /* Fallback */
84 if (!ah->ah_bwmode) {

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124 symbols = DIV_ROUND_UP(bits * 10, symbol_bits);
125
126 dur = sifs + preamble + (sym_time * symbols);
127
128 return dur;
129}
130
131/**
114 int len, struct ieee80211_rate *rate, bool shortpre)
115{
116 int sifs, preamble, plcp_bits, sym_time;
117 int bitrate, bits, symbols, symbol_bits;
118 int dur;
119
120 /* Fallback */
121 if (!ah->ah_bwmode) {

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161 symbols = DIV_ROUND_UP(bits * 10, symbol_bits);
162
163 dur = sifs + preamble + (sym_time * symbols);
164
165 return dur;
166}
167
168/**
132 * ath5k_hw_get_default_slottime - Get the default slot time for current mode
133 *
169 * ath5k_hw_get_default_slottime() - Get the default slot time for current mode
134 * @ah: The &struct ath5k_hw
135 */
170 * @ah: The &struct ath5k_hw
171 */
136unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah)
172unsigned int
173ath5k_hw_get_default_slottime(struct ath5k_hw *ah)
137{
138 struct ieee80211_channel *channel = ah->ah_current_channel;
139 unsigned int slot_time;
140
141 switch (ah->ah_bwmode) {
142 case AR5K_BWMODE_40MHZ:
143 slot_time = AR5K_INIT_SLOT_TIME_TURBO;
144 break;

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155 slot_time = AR5K_INIT_SLOT_TIME_B;
156 break;
157 }
158
159 return slot_time;
160}
161
162/**
174{
175 struct ieee80211_channel *channel = ah->ah_current_channel;
176 unsigned int slot_time;
177
178 switch (ah->ah_bwmode) {
179 case AR5K_BWMODE_40MHZ:
180 slot_time = AR5K_INIT_SLOT_TIME_TURBO;
181 break;

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192 slot_time = AR5K_INIT_SLOT_TIME_B;
193 break;
194 }
195
196 return slot_time;
197}
198
199/**
163 * ath5k_hw_get_default_sifs - Get the default SIFS for current mode
164 *
200 * ath5k_hw_get_default_sifs() - Get the default SIFS for current mode
165 * @ah: The &struct ath5k_hw
166 */
201 * @ah: The &struct ath5k_hw
202 */
167unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah)
203unsigned int
204ath5k_hw_get_default_sifs(struct ath5k_hw *ah)
168{
169 struct ieee80211_channel *channel = ah->ah_current_channel;
170 unsigned int sifs;
171
172 switch (ah->ah_bwmode) {
173 case AR5K_BWMODE_40MHZ:
174 sifs = AR5K_INIT_SIFS_TURBO;
175 break;

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186 sifs = AR5K_INIT_SIFS_DEFAULT_A;
187 break;
188 }
189
190 return sifs;
191}
192
193/**
205{
206 struct ieee80211_channel *channel = ah->ah_current_channel;
207 unsigned int sifs;
208
209 switch (ah->ah_bwmode) {
210 case AR5K_BWMODE_40MHZ:
211 sifs = AR5K_INIT_SIFS_TURBO;
212 break;

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223 sifs = AR5K_INIT_SIFS_DEFAULT_A;
224 break;
225 }
226
227 return sifs;
228}
229
230/**
194 * ath5k_hw_update_mib_counters - Update MIB counters (mac layer statistics)
195 *
231 * ath5k_hw_update_mib_counters() - Update MIB counters (mac layer statistics)
196 * @ah: The &struct ath5k_hw
197 *
198 * Reads MIB counters from PCU and updates sw statistics. Is called after a
199 * MIB interrupt, because one of these counters might have reached their maximum
200 * and triggered the MIB interrupt, to let us read and clear the counter.
201 *
232 * @ah: The &struct ath5k_hw
233 *
234 * Reads MIB counters from PCU and updates sw statistics. Is called after a
235 * MIB interrupt, because one of these counters might have reached their maximum
236 * and triggered the MIB interrupt, to let us read and clear the counter.
237 *
202 * Is called in interrupt context!
238 * NOTE: Is called in interrupt context!
203 */
239 */
204void ath5k_hw_update_mib_counters(struct ath5k_hw *ah)
240void
241ath5k_hw_update_mib_counters(struct ath5k_hw *ah)
205{
206 struct ath5k_statistics *stats = &ah->stats;
207
208 /* Read-And-Clear */
209 stats->ack_fail += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL);
210 stats->rts_fail += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL);
211 stats->rts_ok += ath5k_hw_reg_read(ah, AR5K_RTS_OK);
212 stats->fcs_error += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL);
213 stats->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);
214}
215
216
217/******************\
218* ACK/CTS Timeouts *
219\******************/
220
221/**
242{
243 struct ath5k_statistics *stats = &ah->stats;
244
245 /* Read-And-Clear */
246 stats->ack_fail += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL);
247 stats->rts_fail += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL);
248 stats->rts_ok += ath5k_hw_reg_read(ah, AR5K_RTS_OK);
249 stats->fcs_error += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL);
250 stats->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);
251}
252
253
254/******************\
255* ACK/CTS Timeouts *
256\******************/
257
258/**
222 * ath5k_hw_write_rate_duration - fill rate code to duration table
259 * ath5k_hw_write_rate_duration() - Fill rate code to duration table
260 * @ah: The &struct ath5k_hw
223 *
261 *
224 * @ah: the &struct ath5k_hw
225 * @mode: one of enum ath5k_driver_mode
226 *
227 * Write the rate code to duration table upon hw reset. This is a helper for
228 * ath5k_hw_pcu_init(). It seems all this is doing is setting an ACK timeout on
229 * the hardware, based on current mode, for each rate. The rates which are
230 * capable of short preamble (802.11b rates 2Mbps, 5.5Mbps, and 11Mbps) have
231 * different rate code so we write their value twice (one for long preamble
232 * and one for short).
233 *
234 * Note: Band doesn't matter here, if we set the values for OFDM it works
235 * on both a and g modes. So all we have to do is set values for all g rates
236 * that include all OFDM and CCK rates.
237 *
238 */
262 * Write the rate code to duration table upon hw reset. This is a helper for
263 * ath5k_hw_pcu_init(). It seems all this is doing is setting an ACK timeout on
264 * the hardware, based on current mode, for each rate. The rates which are
265 * capable of short preamble (802.11b rates 2Mbps, 5.5Mbps, and 11Mbps) have
266 * different rate code so we write their value twice (one for long preamble
267 * and one for short).
268 *
269 * Note: Band doesn't matter here, if we set the values for OFDM it works
270 * on both a and g modes. So all we have to do is set values for all g rates
271 * that include all OFDM and CCK rates.
272 *
273 */
239static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah)
274static inline void
275ath5k_hw_write_rate_duration(struct ath5k_hw *ah)
240{
241 struct ieee80211_rate *rate;
242 unsigned int i;
243 /* 802.11g covers both OFDM and CCK */
244 u8 band = IEEE80211_BAND_2GHZ;
245
246 /* Write rate duration table */
247 for (i = 0; i < ah->sbands[band].n_bitrates; i++) {

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275
276 tx_time = ath5k_hw_get_frame_duration(ah, 10, rate, true);
277 ath5k_hw_reg_write(ah, tx_time,
278 reg + (AR5K_SET_SHORT_PREAMBLE << 2));
279 }
280}
281
282/**
276{
277 struct ieee80211_rate *rate;
278 unsigned int i;
279 /* 802.11g covers both OFDM and CCK */
280 u8 band = IEEE80211_BAND_2GHZ;
281
282 /* Write rate duration table */
283 for (i = 0; i < ah->sbands[band].n_bitrates; i++) {

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311
312 tx_time = ath5k_hw_get_frame_duration(ah, 10, rate, true);
313 ath5k_hw_reg_write(ah, tx_time,
314 reg + (AR5K_SET_SHORT_PREAMBLE << 2));
315 }
316}
317
318/**
283 * ath5k_hw_set_ack_timeout - Set ACK timeout on PCU
284 *
319 * ath5k_hw_set_ack_timeout() - Set ACK timeout on PCU
285 * @ah: The &struct ath5k_hw
286 * @timeout: Timeout in usec
287 */
320 * @ah: The &struct ath5k_hw
321 * @timeout: Timeout in usec
322 */
288static int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
323static int
324ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
289{
290 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK))
291 <= timeout)
292 return -EINVAL;
293
294 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK,
295 ath5k_hw_htoclock(ah, timeout));
296
297 return 0;
298}
299
300/**
325{
326 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK))
327 <= timeout)
328 return -EINVAL;
329
330 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK,
331 ath5k_hw_htoclock(ah, timeout));
332
333 return 0;
334}
335
336/**
301 * ath5k_hw_set_cts_timeout - Set CTS timeout on PCU
302 *
337 * ath5k_hw_set_cts_timeout() - Set CTS timeout on PCU
303 * @ah: The &struct ath5k_hw
304 * @timeout: Timeout in usec
305 */
338 * @ah: The &struct ath5k_hw
339 * @timeout: Timeout in usec
340 */
306static int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
341static int
342ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
307{
308 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS))
309 <= timeout)
310 return -EINVAL;
311
312 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS,
313 ath5k_hw_htoclock(ah, timeout));
314
315 return 0;
316}
317
318
319/*******************\
320* RX filter Control *
321\*******************/
322
323/**
343{
344 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS))
345 <= timeout)
346 return -EINVAL;
347
348 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS,
349 ath5k_hw_htoclock(ah, timeout));
350
351 return 0;
352}
353
354
355/*******************\
356* RX filter Control *
357\*******************/
358
359/**
324 * ath5k_hw_set_lladdr - Set station id
325 *
360 * ath5k_hw_set_lladdr() - Set station id
326 * @ah: The &struct ath5k_hw
361 * @ah: The &struct ath5k_hw
327 * @mac: The card's mac address
362 * @mac: The card's mac address (array of octets)
328 *
329 * Set station id on hw using the provided mac address
330 */
363 *
364 * Set station id on hw using the provided mac address
365 */
331int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac)
366int
367ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac)
332{
333 struct ath_common *common = ath5k_hw_common(ah);
334 u32 low_id, high_id;
335 u32 pcu_reg;
336
337 /* Set new station ID */
338 memcpy(common->macaddr, mac, ETH_ALEN);
339

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344
345 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
346 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
347
348 return 0;
349}
350
351/**
368{
369 struct ath_common *common = ath5k_hw_common(ah);
370 u32 low_id, high_id;
371 u32 pcu_reg;
372
373 /* Set new station ID */
374 memcpy(common->macaddr, mac, ETH_ALEN);
375

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380
381 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
382 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
383
384 return 0;
385}
386
387/**
352 * ath5k_hw_set_bssid - Set current BSSID on hw
353 *
388 * ath5k_hw_set_bssid() - Set current BSSID on hw
354 * @ah: The &struct ath5k_hw
355 *
356 * Sets the current BSSID and BSSID mask we have from the
357 * common struct into the hardware
358 */
389 * @ah: The &struct ath5k_hw
390 *
391 * Sets the current BSSID and BSSID mask we have from the
392 * common struct into the hardware
393 */
359void ath5k_hw_set_bssid(struct ath5k_hw *ah)
394void
395ath5k_hw_set_bssid(struct ath5k_hw *ah)
360{
361 struct ath_common *common = ath5k_hw_common(ah);
362 u16 tim_offset = 0;
363
364 /*
365 * Set BSSID mask on 5212
366 */
367 if (ah->ah_version == AR5K_AR5212)

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384 }
385
386 AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM,
387 tim_offset ? tim_offset + 4 : 0);
388
389 ath5k_hw_enable_pspoll(ah, NULL, 0);
390}
391
396{
397 struct ath_common *common = ath5k_hw_common(ah);
398 u16 tim_offset = 0;
399
400 /*
401 * Set BSSID mask on 5212
402 */
403 if (ah->ah_version == AR5K_AR5212)

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420 }
421
422 AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM,
423 tim_offset ? tim_offset + 4 : 0);
424
425 ath5k_hw_enable_pspoll(ah, NULL, 0);
426}
427
392void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
428/**
429 * ath5k_hw_set_bssid_mask() - Filter out bssids we listen
430 * @ah: The &struct ath5k_hw
431 * @mask: The BSSID mask to set (array of octets)
432 *
433 * BSSID masking is a method used by AR5212 and newer hardware to inform PCU
434 * which bits of the interface's MAC address should be looked at when trying
435 * to decide which packets to ACK. In station mode and AP mode with a single
436 * BSS every bit matters since we lock to only one BSS. In AP mode with
437 * multiple BSSes (virtual interfaces) not every bit matters because hw must
438 * accept frames for all BSSes and so we tweak some bits of our mac address
439 * in order to have multiple BSSes.
440 *
441 * For more information check out ../hw.c of the common ath module.
442 */
443void
444ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
393{
394 struct ath_common *common = ath5k_hw_common(ah);
395
396 /* Cache bssid mask so that we can restore it
397 * on reset */
398 memcpy(common->bssidmask, mask, ETH_ALEN);
399 if (ah->ah_version == AR5K_AR5212)
400 ath_hw_setbssidmask(common);
401}
402
445{
446 struct ath_common *common = ath5k_hw_common(ah);
447
448 /* Cache bssid mask so that we can restore it
449 * on reset */
450 memcpy(common->bssidmask, mask, ETH_ALEN);
451 if (ah->ah_version == AR5K_AR5212)
452 ath_hw_setbssidmask(common);
453}
454
403/*
404 * Set multicast filter
455/**
456 * ath5k_hw_set_mcast_filter() - Set multicast filter
457 * @ah: The &struct ath5k_hw
458 * @filter0: Lower 32bits of muticast filter
459 * @filter1: Higher 16bits of multicast filter
405 */
460 */
406void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)
461void
462ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)
407{
408 ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0);
409 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1);
410}
411
412/**
463{
464 ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0);
465 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1);
466}
467
468/**
413 * ath5k_hw_get_rx_filter - Get current rx filter
414 *
469 * ath5k_hw_get_rx_filter() - Get current rx filter
415 * @ah: The &struct ath5k_hw
416 *
417 * Returns the RX filter by reading rx filter and
418 * phy error filter registers. RX filter is used
419 * to set the allowed frame types that PCU will accept
420 * and pass to the driver. For a list of frame types
421 * check out reg.h.
422 */
470 * @ah: The &struct ath5k_hw
471 *
472 * Returns the RX filter by reading rx filter and
473 * phy error filter registers. RX filter is used
474 * to set the allowed frame types that PCU will accept
475 * and pass to the driver. For a list of frame types
476 * check out reg.h.
477 */
423u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah)
478u32
479ath5k_hw_get_rx_filter(struct ath5k_hw *ah)
424{
425 u32 data, filter = 0;
426
427 filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER);
428
429 /*Radar detection for 5212*/
430 if (ah->ah_version == AR5K_AR5212) {
431 data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL);
432
433 if (data & AR5K_PHY_ERR_FIL_RADAR)
434 filter |= AR5K_RX_FILTER_RADARERR;
435 if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK))
436 filter |= AR5K_RX_FILTER_PHYERR;
437 }
438
439 return filter;
440}
441
442/**
480{
481 u32 data, filter = 0;
482
483 filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER);
484
485 /*Radar detection for 5212*/
486 if (ah->ah_version == AR5K_AR5212) {
487 data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL);
488
489 if (data & AR5K_PHY_ERR_FIL_RADAR)
490 filter |= AR5K_RX_FILTER_RADARERR;
491 if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK))
492 filter |= AR5K_RX_FILTER_PHYERR;
493 }
494
495 return filter;
496}
497
498/**
443 * ath5k_hw_set_rx_filter - Set rx filter
444 *
499 * ath5k_hw_set_rx_filter() - Set rx filter
445 * @ah: The &struct ath5k_hw
446 * @filter: RX filter mask (see reg.h)
447 *
448 * Sets RX filter register and also handles PHY error filter
449 * register on 5212 and newer chips so that we have proper PHY
450 * error reporting.
451 */
500 * @ah: The &struct ath5k_hw
501 * @filter: RX filter mask (see reg.h)
502 *
503 * Sets RX filter register and also handles PHY error filter
504 * register on 5212 and newer chips so that we have proper PHY
505 * error reporting.
506 */
452void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
507void
508ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
453{
454 u32 data = 0;
455
456 /* Set PHY error filter register on 5212*/
457 if (ah->ah_version == AR5K_AR5212) {
458 if (filter & AR5K_RX_FILTER_RADARERR)
459 data |= AR5K_PHY_ERR_FIL_RADAR;
460 if (filter & AR5K_RX_FILTER_PHYERR)

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488
489/****************\
490* Beacon control *
491\****************/
492
493#define ATH5K_MAX_TSF_READ 10
494
495/**
509{
510 u32 data = 0;
511
512 /* Set PHY error filter register on 5212*/
513 if (ah->ah_version == AR5K_AR5212) {
514 if (filter & AR5K_RX_FILTER_RADARERR)
515 data |= AR5K_PHY_ERR_FIL_RADAR;
516 if (filter & AR5K_RX_FILTER_PHYERR)

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544
545/****************\
546* Beacon control *
547\****************/
548
549#define ATH5K_MAX_TSF_READ 10
550
551/**
496 * ath5k_hw_get_tsf64 - Get the full 64bit TSF
497 *
552 * ath5k_hw_get_tsf64() - Get the full 64bit TSF
498 * @ah: The &struct ath5k_hw
499 *
500 * Returns the current TSF
501 */
553 * @ah: The &struct ath5k_hw
554 *
555 * Returns the current TSF
556 */
502u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
557u64
558ath5k_hw_get_tsf64(struct ath5k_hw *ah)
503{
504 u32 tsf_lower, tsf_upper1, tsf_upper2;
505 int i;
506 unsigned long flags;
507
508 /* This code is time critical - we don't want to be interrupted here */
509 local_irq_save(flags);
510

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531
532 local_irq_restore(flags);
533
534 WARN_ON(i == ATH5K_MAX_TSF_READ);
535
536 return ((u64)tsf_upper1 << 32) | tsf_lower;
537}
538
559{
560 u32 tsf_lower, tsf_upper1, tsf_upper2;
561 int i;
562 unsigned long flags;
563
564 /* This code is time critical - we don't want to be interrupted here */
565 local_irq_save(flags);
566

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587
588 local_irq_restore(flags);
589
590 WARN_ON(i == ATH5K_MAX_TSF_READ);
591
592 return ((u64)tsf_upper1 << 32) | tsf_lower;
593}
594
595#undef ATH5K_MAX_TSF_READ
596
539/**
597/**
540 * ath5k_hw_set_tsf64 - Set a new 64bit TSF
541 *
598 * ath5k_hw_set_tsf64() - Set a new 64bit TSF
542 * @ah: The &struct ath5k_hw
543 * @tsf64: The new 64bit TSF
544 *
545 * Sets the new TSF
546 */
599 * @ah: The &struct ath5k_hw
600 * @tsf64: The new 64bit TSF
601 *
602 * Sets the new TSF
603 */
547void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64)
604void
605ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64)
548{
549 ath5k_hw_reg_write(ah, tsf64 & 0xffffffff, AR5K_TSF_L32);
550 ath5k_hw_reg_write(ah, (tsf64 >> 32) & 0xffffffff, AR5K_TSF_U32);
551}
552
553/**
606{
607 ath5k_hw_reg_write(ah, tsf64 & 0xffffffff, AR5K_TSF_L32);
608 ath5k_hw_reg_write(ah, (tsf64 >> 32) & 0xffffffff, AR5K_TSF_U32);
609}
610
611/**
554 * ath5k_hw_reset_tsf - Force a TSF reset
555 *
612 * ath5k_hw_reset_tsf() - Force a TSF reset
556 * @ah: The &struct ath5k_hw
557 *
558 * Forces a TSF reset on PCU
559 */
613 * @ah: The &struct ath5k_hw
614 *
615 * Forces a TSF reset on PCU
616 */
560void ath5k_hw_reset_tsf(struct ath5k_hw *ah)
617void
618ath5k_hw_reset_tsf(struct ath5k_hw *ah)
561{
562 u32 val;
563
564 val = ath5k_hw_reg_read(ah, AR5K_BEACON) | AR5K_BEACON_RESET_TSF;
565
566 /*
567 * Each write to the RESET_TSF bit toggles a hardware internal
568 * signal to reset TSF, but if left high it will cause a TSF reset
569 * on the next chip reset as well. Thus we always write the value
570 * twice to clear the signal.
571 */
572 ath5k_hw_reg_write(ah, val, AR5K_BEACON);
573 ath5k_hw_reg_write(ah, val, AR5K_BEACON);
574}
575
619{
620 u32 val;
621
622 val = ath5k_hw_reg_read(ah, AR5K_BEACON) | AR5K_BEACON_RESET_TSF;
623
624 /*
625 * Each write to the RESET_TSF bit toggles a hardware internal
626 * signal to reset TSF, but if left high it will cause a TSF reset
627 * on the next chip reset as well. Thus we always write the value
628 * twice to clear the signal.
629 */
630 ath5k_hw_reg_write(ah, val, AR5K_BEACON);
631 ath5k_hw_reg_write(ah, val, AR5K_BEACON);
632}
633
576/*
577 * Initialize beacon timers
634/**
635 * ath5k_hw_init_beacon_timers() - Initialize beacon timers
636 * @ah: The &struct ath5k_hw
637 * @next_beacon: Next TBTT
638 * @interval: Current beacon interval
639 *
640 * This function is used to initialize beacon timers based on current
641 * operation mode and settings.
578 */
642 */
579void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
643void
644ath5k_hw_init_beacon_timers(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
580{
581 u32 timer1, timer2, timer3;
582
583 /*
584 * Set the additional timers by mode
585 */
586 switch (ah->opmode) {
587 case NL80211_IFTYPE_MONITOR:

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650 /* TODO: Set enhanced sleep registers on AR5212
651 * based on vif->bss_conf params, until then
652 * disable power save reporting.*/
653 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PWR_SV);
654
655}
656
657/**
645{
646 u32 timer1, timer2, timer3;
647
648 /*
649 * Set the additional timers by mode
650 */
651 switch (ah->opmode) {
652 case NL80211_IFTYPE_MONITOR:

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715 /* TODO: Set enhanced sleep registers on AR5212
716 * based on vif->bss_conf params, until then
717 * disable power save reporting.*/
718 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PWR_SV);
719
720}
721
722/**
658 * ath5k_check_timer_win - Check if timer B is timer A + window
659 *
723 * ath5k_check_timer_win() - Check if timer B is timer A + window
660 * @a: timer a (before b)
661 * @b: timer b (after a)
662 * @window: difference between a and b
663 * @intval: timers are increased by this interval
664 *
665 * This helper function checks if timer B is timer A + window and covers
666 * cases where timer A or B might have already been updated or wrapped
667 * around (Timers are 16 bit).

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681 (a - b == intval - window) || /* 2.) */
682 ((a | 0x10000) - b == intval - window) || /* 3.) */
683 ((b | 0x10000) - a == window)) /* 4.) */
684 return true; /* O.K. */
685 return false;
686}
687
688/**
724 * @a: timer a (before b)
725 * @b: timer b (after a)
726 * @window: difference between a and b
727 * @intval: timers are increased by this interval
728 *
729 * This helper function checks if timer B is timer A + window and covers
730 * cases where timer A or B might have already been updated or wrapped
731 * around (Timers are 16 bit).

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745 (a - b == intval - window) || /* 2.) */
746 ((a | 0x10000) - b == intval - window) || /* 3.) */
747 ((b | 0x10000) - a == window)) /* 4.) */
748 return true; /* O.K. */
749 return false;
750}
751
752/**
689 * ath5k_hw_check_beacon_timers - Check if the beacon timers are correct
690 *
753 * ath5k_hw_check_beacon_timers() - Check if the beacon timers are correct
691 * @ah: The &struct ath5k_hw
692 * @intval: beacon interval
693 *
754 * @ah: The &struct ath5k_hw
755 * @intval: beacon interval
756 *
694 * This is a workaround for IBSS mode:
757 * This is a workaround for IBSS mode
695 *
696 * The need for this function arises from the fact that we have 4 separate
697 * HW timer registers (TIMER0 - TIMER3), which are closely related to the
698 * next beacon target time (NBTT), and that the HW updates these timers
699 * separately based on the current TSF value. The hardware increments each
700 * timer by the beacon interval, when the local TSF converted to TU is equal
701 * to the value stored in the timer.
702 *

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741 if (ath5k_check_timer_win(nbtt, atim, 1, intval) &&
742 ath5k_check_timer_win(dma, nbtt, AR5K_TUNE_DMA_BEACON_RESP,
743 intval))
744 return true; /* O.K. */
745 return false;
746}
747
748/**
758 *
759 * The need for this function arises from the fact that we have 4 separate
760 * HW timer registers (TIMER0 - TIMER3), which are closely related to the
761 * next beacon target time (NBTT), and that the HW updates these timers
762 * separately based on the current TSF value. The hardware increments each
763 * timer by the beacon interval, when the local TSF converted to TU is equal
764 * to the value stored in the timer.
765 *

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804 if (ath5k_check_timer_win(nbtt, atim, 1, intval) &&
805 ath5k_check_timer_win(dma, nbtt, AR5K_TUNE_DMA_BEACON_RESP,
806 intval))
807 return true; /* O.K. */
808 return false;
809}
810
811/**
749 * ath5k_hw_set_coverage_class - Set IEEE 802.11 coverage class
750 *
812 * ath5k_hw_set_coverage_class() - Set IEEE 802.11 coverage class
751 * @ah: The &struct ath5k_hw
752 * @coverage_class: IEEE 802.11 coverage class number
753 *
754 * Sets IFS intervals and ACK/CTS timeouts for given coverage class.
755 */
813 * @ah: The &struct ath5k_hw
814 * @coverage_class: IEEE 802.11 coverage class number
815 *
816 * Sets IFS intervals and ACK/CTS timeouts for given coverage class.
817 */
756void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class)
818void
819ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class)
757{
758 /* As defined by IEEE 802.11-2007 17.3.8.6 */
759 int slot_time = ath5k_hw_get_default_slottime(ah) + 3 * coverage_class;
760 int ack_timeout = ath5k_hw_get_default_sifs(ah) + slot_time;
761 int cts_timeout = ack_timeout;
762
763 ath5k_hw_set_ifs_intervals(ah, slot_time);
764 ath5k_hw_set_ack_timeout(ah, ack_timeout);
765 ath5k_hw_set_cts_timeout(ah, cts_timeout);
766
767 ah->ah_coverage_class = coverage_class;
768}
769
770/***************************\
771* Init/Start/Stop functions *
772\***************************/
773
774/**
820{
821 /* As defined by IEEE 802.11-2007 17.3.8.6 */
822 int slot_time = ath5k_hw_get_default_slottime(ah) + 3 * coverage_class;
823 int ack_timeout = ath5k_hw_get_default_sifs(ah) + slot_time;
824 int cts_timeout = ack_timeout;
825
826 ath5k_hw_set_ifs_intervals(ah, slot_time);
827 ath5k_hw_set_ack_timeout(ah, ack_timeout);
828 ath5k_hw_set_cts_timeout(ah, cts_timeout);
829
830 ah->ah_coverage_class = coverage_class;
831}
832
833/***************************\
834* Init/Start/Stop functions *
835\***************************/
836
837/**
775 * ath5k_hw_start_rx_pcu - Start RX engine
776 *
838 * ath5k_hw_start_rx_pcu() - Start RX engine
777 * @ah: The &struct ath5k_hw
778 *
779 * Starts RX engine on PCU so that hw can process RXed frames
780 * (ACK etc).
781 *
782 * NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma
783 */
839 * @ah: The &struct ath5k_hw
840 *
841 * Starts RX engine on PCU so that hw can process RXed frames
842 * (ACK etc).
843 *
844 * NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma
845 */
784void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
846void
847ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
785{
786 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
787}
788
789/**
848{
849 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
850}
851
852/**
790 * at5k_hw_stop_rx_pcu - Stop RX engine
791 *
853 * at5k_hw_stop_rx_pcu() - Stop RX engine
792 * @ah: The &struct ath5k_hw
793 *
794 * Stops RX engine on PCU
795 */
854 * @ah: The &struct ath5k_hw
855 *
856 * Stops RX engine on PCU
857 */
796void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah)
858void
859ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah)
797{
798 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
799}
800
801/**
860{
861 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
862}
863
864/**
802 * ath5k_hw_set_opmode - Set PCU operating mode
803 *
865 * ath5k_hw_set_opmode() - Set PCU operating mode
804 * @ah: The &struct ath5k_hw
866 * @ah: The &struct ath5k_hw
805 * @op_mode: &enum nl80211_iftype operating mode
867 * @op_mode: One of enum nl80211_iftype
806 *
807 * Configure PCU for the various operating modes (AP/STA etc)
808 */
868 *
869 * Configure PCU for the various operating modes (AP/STA etc)
870 */
809int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode)
871int
872ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode)
810{
811 struct ath_common *common = ath5k_hw_common(ah);
812 u32 pcu_reg, beacon_reg, low_id, high_id;
813
814 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode %d\n", op_mode);
815
816 /* Preserve rest settings */
817 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;

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868 * Set Beacon Control Register on 5210
869 */
870 if (ah->ah_version == AR5K_AR5210)
871 ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR);
872
873 return 0;
874}
875
873{
874 struct ath_common *common = ath5k_hw_common(ah);
875 u32 pcu_reg, beacon_reg, low_id, high_id;
876
877 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode %d\n", op_mode);
878
879 /* Preserve rest settings */
880 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;

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931 * Set Beacon Control Register on 5210
932 */
933 if (ah->ah_version == AR5K_AR5210)
934 ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR);
935
936 return 0;
937}
938
876void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
877 u8 mode)
939/**
940 * ath5k_hw_pcu_init() - Initialize PCU
941 * @ah: The &struct ath5k_hw
942 * @op_mode: One of enum nl80211_iftype
943 * @mode: One of enum ath5k_driver_mode
944 *
945 * This function is used to initialize PCU by setting current
946 * operation mode and various other settings.
947 */
948void
949ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode)
878{
879 /* Set bssid and bssid mask */
880 ath5k_hw_set_bssid(ah);
881
882 /* Set PCU config */
883 ath5k_hw_set_opmode(ah, op_mode);
884
885 /* Write rate duration table only on AR5212 and if

--- 49 unchanged lines hidden --- 		950{
951 /* Set bssid and bssid mask */
952 ath5k_hw_set_bssid(ah);
953
954 /* Set PCU config */
955 ath5k_hw_set_opmode(ah, op_mode);
956
957 /* Write rate duration table only on AR5212 and if

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