initvals.c (d4bbf7e7759afc172e2bfbc5c416324590049cdd) initvals.c (c47faa364cfb249d5d7670fb7293a6f9acd8aa9e)
1/*
2 * Initial register settings functions
3 *
4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 *
8 * Permission to use, copy, modify, and distribute this software for any

--- 9 unchanged lines hidden (view full) ---

18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 *
20 */
21
22#include "ath5k.h"
23#include "reg.h"
24#include "debug.h"
25
1/*
2 * Initial register settings functions
3 *
4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 *
8 * Permission to use, copy, modify, and distribute this software for any

--- 9 unchanged lines hidden (view full) ---

18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 *
20 */
21
22#include "ath5k.h"
23#include "reg.h"
24#include "debug.h"
25
26/*
27 * Mode-independent initial register writes
26/**
27 * struct ath5k_ini - Mode-independent initial register writes
28 * @ini_register: Register address
29 * @ini_value: Default value
30 * @ini_mode: 0 to write 1 to read (and clear)
28 */
31 */
29
30struct ath5k_ini {
31 u16 ini_register;
32 u32 ini_value;
33
34 enum {
35 AR5K_INI_WRITE = 0, /* Default */
32struct ath5k_ini {
33 u16 ini_register;
34 u32 ini_value;
35
36 enum {
37 AR5K_INI_WRITE = 0, /* Default */
36 AR5K_INI_READ = 1, /* Cleared on read */
38 AR5K_INI_READ = 1,
37 } ini_mode;
38};
39
39 } ini_mode;
40};
41
40/*
41 * Mode specific initial register values
42/**
43 * struct ath5k_ini_mode - Mode specific initial register values
44 * @mode_register: Register address
45 * @mode_value: Set of values for each enum ath5k_driver_mode
42 */
46 */
43
44struct ath5k_ini_mode {
45 u16 mode_register;
46 u32 mode_value[3];
47};
48
49/* Initial register settings for AR5210 */
50static const struct ath5k_ini ar5210_ini[] = {
51 /* PCU and MAC registers */

--- 329 unchanged lines hidden (view full) ---

381 { AR5K_PHY(648), 0x0c53800a },
382 { AR5K_PHY(649), 0x0014df3b },
383 { AR5K_PHY(650), 0x000001b5 },
384 { AR5K_PHY(651), 0x00000020 },
385};
386
387/* Initial mode-specific settings for AR5211
388 * 5211 supports OFDM-only g (draft g) but we
47struct ath5k_ini_mode {
48 u16 mode_register;
49 u32 mode_value[3];
50};
51
52/* Initial register settings for AR5210 */
53static const struct ath5k_ini ar5210_ini[] = {
54 /* PCU and MAC registers */

--- 329 unchanged lines hidden (view full) ---

384 { AR5K_PHY(648), 0x0c53800a },
385 { AR5K_PHY(649), 0x0014df3b },
386 { AR5K_PHY(650), 0x000001b5 },
387 { AR5K_PHY(651), 0x00000020 },
388};
389
390/* Initial mode-specific settings for AR5211
391 * 5211 supports OFDM-only g (draft g) but we
389 * need to test it !
390 */
392 * need to test it ! */
391static const struct ath5k_ini_mode ar5211_ini_mode[] = {
392 { AR5K_TXCFG,
393static const struct ath5k_ini_mode ar5211_ini_mode[] = {
394 { AR5K_TXCFG,
393 /* A/XR B G */
395 /* A B G */
394 { 0x00000015, 0x0000001d, 0x00000015 } },
395 { AR5K_QUEUE_DFS_LOCAL_IFS(0),
396 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
397 { AR5K_QUEUE_DFS_LOCAL_IFS(1),
398 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
399 { AR5K_QUEUE_DFS_LOCAL_IFS(2),
400 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
401 { AR5K_QUEUE_DFS_LOCAL_IFS(3),

--- 53 unchanged lines hidden (view full) ---

455 { AR5K_PHY_FRAME_CTL_5211,
456 { 0x6fe01020, 0x6fe00920, 0x6fe01020 } },
457 { AR5K_PHY_PCDAC_TXPOWER_BASE,
458 { 0x05ff14ff, 0x05ff14ff, 0x05ff19ff } },
459 { AR5K_RF_BUFFER_CONTROL_4,
460 { 0x00000010, 0x00000010, 0x00000010 } },
461};
462
396 { 0x00000015, 0x0000001d, 0x00000015 } },
397 { AR5K_QUEUE_DFS_LOCAL_IFS(0),
398 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
399 { AR5K_QUEUE_DFS_LOCAL_IFS(1),
400 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
401 { AR5K_QUEUE_DFS_LOCAL_IFS(2),
402 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
403 { AR5K_QUEUE_DFS_LOCAL_IFS(3),

--- 53 unchanged lines hidden (view full) ---

457 { AR5K_PHY_FRAME_CTL_5211,
458 { 0x6fe01020, 0x6fe00920, 0x6fe01020 } },
459 { AR5K_PHY_PCDAC_TXPOWER_BASE,
460 { 0x05ff14ff, 0x05ff14ff, 0x05ff19ff } },
461 { AR5K_RF_BUFFER_CONTROL_4,
462 { 0x00000010, 0x00000010, 0x00000010 } },
463};
464
463/* Initial register settings for AR5212 */
465/* Initial register settings for AR5212 and newer chips */
464static const struct ath5k_ini ar5212_ini_common_start[] = {
465 { AR5K_RXDP, 0x00000000 },
466 { AR5K_RXCFG, 0x00000005 },
467 { AR5K_MIBC, 0x00000000 },
468 { AR5K_TOPS, 0x00000008 },
469 { AR5K_RXNOFRM, 0x00000008 },
470 { AR5K_TXNOFRM, 0x00000010 },
471 { AR5K_RPGTO, 0x00000000 },

--- 247 unchanged lines hidden (view full) ---

719 { AR5K_PHY(70),
720 { 0x000001b8, 0x00000084, 0x00000108 } },
721 { AR5K_PHY_OFDM_SELFCORR,
722 { 0x10058a05, 0x10058a05, 0x10058a05 } },
723 { 0xa230,
724 { 0x00000000, 0x00000000, 0x00000108 } },
725};
726
466static const struct ath5k_ini ar5212_ini_common_start[] = {
467 { AR5K_RXDP, 0x00000000 },
468 { AR5K_RXCFG, 0x00000005 },
469 { AR5K_MIBC, 0x00000000 },
470 { AR5K_TOPS, 0x00000008 },
471 { AR5K_RXNOFRM, 0x00000008 },
472 { AR5K_TXNOFRM, 0x00000010 },
473 { AR5K_RPGTO, 0x00000000 },

--- 247 unchanged lines hidden (view full) ---

721 { AR5K_PHY(70),
722 { 0x000001b8, 0x00000084, 0x00000108 } },
723 { AR5K_PHY_OFDM_SELFCORR,
724 { 0x10058a05, 0x10058a05, 0x10058a05 } },
725 { 0xa230,
726 { 0x00000000, 0x00000000, 0x00000108 } },
727};
728
727/* Initial mode-specific settings for AR5212 + RF5111 (Written after ar5212_ini) */
729/* Initial mode-specific settings for AR5212 + RF5111
730 * (Written after ar5212_ini) */
728static const struct ath5k_ini_mode rf5111_ini_mode_end[] = {
729 { AR5K_TXCFG,
730 /* A/XR B G */
731 { 0x00008015, 0x00008015, 0x00008015 } },
732 { AR5K_USEC_5211,
733 { 0x128d8fa7, 0x04e00f95, 0x12e00fab } },
734 { AR5K_PHY_RF_CTL3,
735 { 0x0a020001, 0x05010100, 0x0a020001 } },

--- 16 unchanged lines hidden (view full) ---

752 { AR5K_PHY_FRAME_CTL_5211,
753 { 0xf7b81020, 0xf7b80d20, 0xf7b81020 } },
754 { AR5K_PHY_GAIN_2GHZ,
755 { 0x642c416a, 0x6440416a, 0x6440416a } },
756 { AR5K_PHY_CCK_RX_CTL_4,
757 { 0x1883800a, 0x1873800a, 0x1883800a } },
758};
759
731static const struct ath5k_ini_mode rf5111_ini_mode_end[] = {
732 { AR5K_TXCFG,
733 /* A/XR B G */
734 { 0x00008015, 0x00008015, 0x00008015 } },
735 { AR5K_USEC_5211,
736 { 0x128d8fa7, 0x04e00f95, 0x12e00fab } },
737 { AR5K_PHY_RF_CTL3,
738 { 0x0a020001, 0x05010100, 0x0a020001 } },

--- 16 unchanged lines hidden (view full) ---

755 { AR5K_PHY_FRAME_CTL_5211,
756 { 0xf7b81020, 0xf7b80d20, 0xf7b81020 } },
757 { AR5K_PHY_GAIN_2GHZ,
758 { 0x642c416a, 0x6440416a, 0x6440416a } },
759 { AR5K_PHY_CCK_RX_CTL_4,
760 { 0x1883800a, 0x1873800a, 0x1883800a } },
761};
762
763/* Common for all modes */
760static const struct ath5k_ini rf5111_ini_common_end[] = {
761 { AR5K_DCU_FP, 0x00000000 },
762 { AR5K_PHY_AGC, 0x00000000 },
763 { AR5K_PHY_ADC_CTL, 0x00022ffe },
764 { 0x983c, 0x00020100 },
765 { AR5K_PHY_GAIN_OFFSET, 0x1284613c },
766 { AR5K_PHY_PAPD_PROBE, 0x00004883 },
767 { 0x9940, 0x00000004 },
768 { 0x9958, 0x000000ff },
769 { 0x9974, 0x00000000 },
770 { AR5K_PHY_SPENDING, 0x00000018 },
771 { AR5K_PHY_CCKTXCTL, 0x00000000 },
772 { AR5K_PHY_CCK_CROSSCORR, 0xd03e6788 },
773 { AR5K_PHY_DAG_CCK_CTL, 0x000001b5 },
774 { 0xa23c, 0x13c889af },
775};
776
764static const struct ath5k_ini rf5111_ini_common_end[] = {
765 { AR5K_DCU_FP, 0x00000000 },
766 { AR5K_PHY_AGC, 0x00000000 },
767 { AR5K_PHY_ADC_CTL, 0x00022ffe },
768 { 0x983c, 0x00020100 },
769 { AR5K_PHY_GAIN_OFFSET, 0x1284613c },
770 { AR5K_PHY_PAPD_PROBE, 0x00004883 },
771 { 0x9940, 0x00000004 },
772 { 0x9958, 0x000000ff },
773 { 0x9974, 0x00000000 },
774 { AR5K_PHY_SPENDING, 0x00000018 },
775 { AR5K_PHY_CCKTXCTL, 0x00000000 },
776 { AR5K_PHY_CCK_CROSSCORR, 0xd03e6788 },
777 { AR5K_PHY_DAG_CCK_CTL, 0x000001b5 },
778 { 0xa23c, 0x13c889af },
779};
780
777/* Initial mode-specific settings for AR5212 + RF5112 (Written after ar5212_ini) */
781
782/* Initial mode-specific settings for AR5212 + RF5112
783 * (Written after ar5212_ini) */
778static const struct ath5k_ini_mode rf5112_ini_mode_end[] = {
779 { AR5K_TXCFG,
780 /* A/XR B G */
781 { 0x00008015, 0x00008015, 0x00008015 } },
782 { AR5K_USEC_5211,
783 { 0x128d93a7, 0x04e01395, 0x12e013ab } },
784 { AR5K_PHY_RF_CTL3,
785 { 0x0a020001, 0x05020100, 0x0a020001 } },

--- 34 unchanged lines hidden (view full) ---

820 { AR5K_PHY_PAPD_PROBE, 0x00004882 },
821 { 0x9940, 0x00000004 },
822 { 0x9958, 0x000000ff },
823 { 0x9974, 0x00000000 },
824 { AR5K_PHY_DAG_CCK_CTL, 0x000001b5 },
825 { 0xa23c, 0x13c889af },
826};
827
784static const struct ath5k_ini_mode rf5112_ini_mode_end[] = {
785 { AR5K_TXCFG,
786 /* A/XR B G */
787 { 0x00008015, 0x00008015, 0x00008015 } },
788 { AR5K_USEC_5211,
789 { 0x128d93a7, 0x04e01395, 0x12e013ab } },
790 { AR5K_PHY_RF_CTL3,
791 { 0x0a020001, 0x05020100, 0x0a020001 } },

--- 34 unchanged lines hidden (view full) ---

826 { AR5K_PHY_PAPD_PROBE, 0x00004882 },
827 { 0x9940, 0x00000004 },
828 { 0x9958, 0x000000ff },
829 { 0x9974, 0x00000000 },
830 { AR5K_PHY_DAG_CCK_CTL, 0x000001b5 },
831 { 0xa23c, 0x13c889af },
832};
833
828/* Initial mode-specific settings for RF5413/5414 (Written after ar5212_ini) */
834
835/* Initial mode-specific settings for RF5413/5414
836 * (Written after ar5212_ini) */
829static const struct ath5k_ini_mode rf5413_ini_mode_end[] = {
830 { AR5K_TXCFG,
831 /* A/XR B G */
832 { 0x00000015, 0x00000015, 0x00000015 } },
833 { AR5K_USEC_5211,
834 { 0x128d93a7, 0x04e01395, 0x12e013ab } },
835 { AR5K_PHY_RF_CTL3,
836 { 0x0a020001, 0x05020100, 0x0a020001 } },

--- 121 unchanged lines hidden (view full) ---

958 { 0xa370, 0x3fc40883 },
959 { 0xa374, 0x57c00803 },
960 { 0xa378, 0x5fd80682 },
961 { 0xa37c, 0x7fe00482 },
962 { 0xa380, 0x7f3c7bba },
963 { 0xa384, 0xf3307ff0 },
964};
965
837static const struct ath5k_ini_mode rf5413_ini_mode_end[] = {
838 { AR5K_TXCFG,
839 /* A/XR B G */
840 { 0x00000015, 0x00000015, 0x00000015 } },
841 { AR5K_USEC_5211,
842 { 0x128d93a7, 0x04e01395, 0x12e013ab } },
843 { AR5K_PHY_RF_CTL3,
844 { 0x0a020001, 0x05020100, 0x0a020001 } },

--- 121 unchanged lines hidden (view full) ---

966 { 0xa370, 0x3fc40883 },
967 { 0xa374, 0x57c00803 },
968 { 0xa378, 0x5fd80682 },
969 { 0xa37c, 0x7fe00482 },
970 { 0xa380, 0x7f3c7bba },
971 { 0xa384, 0xf3307ff0 },
972};
973
966/* Initial mode-specific settings for RF2413/2414 (Written after ar5212_ini) */
974/* Initial mode-specific settings for RF2413/2414
975 * (Written after ar5212_ini) */
967/* XXX: a mode ? */
968static const struct ath5k_ini_mode rf2413_ini_mode_end[] = {
969 { AR5K_TXCFG,
970 /* A/XR B G */
971 { 0x00000015, 0x00000015, 0x00000015 } },
972 { AR5K_USEC_5211,
973 { 0x128d93a7, 0x04e01395, 0x12e013ab } },
974 { AR5K_PHY_RF_CTL3,

--- 105 unchanged lines hidden (view full) ---

1080 { 0xa370, 0x3fc40883 },
1081 { 0xa374, 0x57c00803 },
1082 { 0xa378, 0x5fd80682 },
1083 { 0xa37c, 0x7fe00482 },
1084 { 0xa380, 0x7f3c7bba },
1085 { 0xa384, 0xf3307ff0 },
1086};
1087
976/* XXX: a mode ? */
977static const struct ath5k_ini_mode rf2413_ini_mode_end[] = {
978 { AR5K_TXCFG,
979 /* A/XR B G */
980 { 0x00000015, 0x00000015, 0x00000015 } },
981 { AR5K_USEC_5211,
982 { 0x128d93a7, 0x04e01395, 0x12e013ab } },
983 { AR5K_PHY_RF_CTL3,

--- 105 unchanged lines hidden (view full) ---

1089 { 0xa370, 0x3fc40883 },
1090 { 0xa374, 0x57c00803 },
1091 { 0xa378, 0x5fd80682 },
1092 { 0xa37c, 0x7fe00482 },
1093 { 0xa380, 0x7f3c7bba },
1094 { 0xa384, 0xf3307ff0 },
1095};
1096
1088/* Initial mode-specific settings for RF2425 (Written after ar5212_ini) */
1097/* Initial mode-specific settings for RF2425
1098 * (Written after ar5212_ini) */
1089/* XXX: a mode ? */
1090static const struct ath5k_ini_mode rf2425_ini_mode_end[] = {
1091 { AR5K_TXCFG,
1092 /* A/XR B G */
1093 { 0x00000015, 0x00000015, 0x00000015 } },
1094 { AR5K_USEC_5211,
1095 { 0x128d93a7, 0x04e01395, 0x12e013ab } },
1096 { AR5K_PHY_RF_CTL3,

--- 255 unchanged lines hidden (view full) ---

1352 { AR5K_BB_GAIN(59), 0x00000035 },
1353 { AR5K_BB_GAIN(60), 0x00000035 },
1354 { AR5K_BB_GAIN(61), 0x00000035 },
1355 { AR5K_BB_GAIN(62), 0x00000010 },
1356 { AR5K_BB_GAIN(63), 0x0000001a },
1357};
1358
1359
1099/* XXX: a mode ? */
1100static const struct ath5k_ini_mode rf2425_ini_mode_end[] = {
1101 { AR5K_TXCFG,
1102 /* A/XR B G */
1103 { 0x00000015, 0x00000015, 0x00000015 } },
1104 { AR5K_USEC_5211,
1105 { 0x128d93a7, 0x04e01395, 0x12e013ab } },
1106 { AR5K_PHY_RF_CTL3,

--- 255 unchanged lines hidden (view full) ---

1362 { AR5K_BB_GAIN(59), 0x00000035 },
1363 { AR5K_BB_GAIN(60), 0x00000035 },
1364 { AR5K_BB_GAIN(61), 0x00000035 },
1365 { AR5K_BB_GAIN(62), 0x00000010 },
1366 { AR5K_BB_GAIN(63), 0x0000001a },
1367};
1368
1369
1360/*
1361 * Write initial register dump
1370/**
1371 * ath5k_hw_ini_registers() - Write initial register dump common for all modes
1372 * @ah: The &struct ath5k_hw
1373 * @size: Dump size
1374 * @ini_regs: The array of &struct ath5k_ini
1375 * @skip_pcu: Skip PCU registers
1362 */
1376 */
1363static void ath5k_hw_ini_registers(struct ath5k_hw *ah, unsigned int size,
1377static void
1378ath5k_hw_ini_registers(struct ath5k_hw *ah, unsigned int size,
1364 const struct ath5k_ini *ini_regs, bool skip_pcu)
1365{
1366 unsigned int i;
1367
1368 /* Write initial registers */
1369 for (i = 0; i < size; i++) {
1370 /* Skip PCU registers if
1371 * requested */

--- 11 unchanged lines hidden (view full) ---

1383 default:
1384 AR5K_REG_WAIT(i);
1385 ath5k_hw_reg_write(ah, ini_regs[i].ini_value,
1386 ini_regs[i].ini_register);
1387 }
1388 }
1389}
1390
1379 const struct ath5k_ini *ini_regs, bool skip_pcu)
1380{
1381 unsigned int i;
1382
1383 /* Write initial registers */
1384 for (i = 0; i < size; i++) {
1385 /* Skip PCU registers if
1386 * requested */

--- 11 unchanged lines hidden (view full) ---

1398 default:
1399 AR5K_REG_WAIT(i);
1400 ath5k_hw_reg_write(ah, ini_regs[i].ini_value,
1401 ini_regs[i].ini_register);
1402 }
1403 }
1404}
1405
1391static void ath5k_hw_ini_mode_registers(struct ath5k_hw *ah,
1406/**
1407 * ath5k_hw_ini_mode_registers() - Write initial mode-specific register dump
1408 * @ah: The &struct ath5k_hw
1409 * @size: Dump size
1410 * @ini_mode: The array of &struct ath5k_ini_mode
1411 * @mode: One of enum ath5k_driver_mode
1412 */
1413static void
1414ath5k_hw_ini_mode_registers(struct ath5k_hw *ah,
1392 unsigned int size, const struct ath5k_ini_mode *ini_mode,
1393 u8 mode)
1394{
1395 unsigned int i;
1396
1397 for (i = 0; i < size; i++) {
1398 AR5K_REG_WAIT(i);
1399 ath5k_hw_reg_write(ah, ini_mode[i].mode_value[mode],
1400 (u32)ini_mode[i].mode_register);
1401 }
1402
1403}
1404
1415 unsigned int size, const struct ath5k_ini_mode *ini_mode,
1416 u8 mode)
1417{
1418 unsigned int i;
1419
1420 for (i = 0; i < size; i++) {
1421 AR5K_REG_WAIT(i);
1422 ath5k_hw_reg_write(ah, ini_mode[i].mode_value[mode],
1423 (u32)ini_mode[i].mode_register);
1424 }
1425
1426}
1427
1405int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool skip_pcu)
1428/**
1429 * ath5k_hw_write_initvals() - Write initial chip-specific register dump
1430 * @ah: The &struct ath5k_hw
1431 * @mode: One of enum ath5k_driver_mode
1432 * @skip_pcu: Skip PCU registers
1433 *
1434 * Write initial chip-specific register dump, to get the chipset on a
1435 * clean and ready-to-work state after warm reset.
1436 */
1437int
1438ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool skip_pcu)
1406{
1407 /*
1408 * Write initial register settings
1409 */
1410
1411 /* For AR5212 and compatible */
1412 if (ah->ah_version == AR5K_AR5212) {
1413

--- 158 unchanged lines hidden --- 		1439{
1440 /*
1441 * Write initial register settings
1442 */
1443
1444 /* For AR5212 and compatible */
1445 if (ah->ah_version == AR5K_AR5212) {
1446

--- 158 unchanged lines hidden ---