initvals.c (b7e56edba4b02f2079042c326a8cd72a44635817) initvals.c (8c2b418a07b4dc77d7efadb890ba9ad1a4161c3f)
1/*
2 * Initial register settings functions
3 *
4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 *
8 * Permission to use, copy, modify, and distribute this software for any

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39};
40
41/*
42 * Mode specific initial register values
43 */
44
45struct ath5k_ini_mode {
46 u16 mode_register;
1/*
2 * Initial register settings functions
3 *
4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 *
8 * Permission to use, copy, modify, and distribute this software for any

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39};
40
41/*
42 * Mode specific initial register values
43 */
44
45struct ath5k_ini_mode {
46 u16 mode_register;
47 u32 mode_value[5];
47 u32 mode_value[3];
48};
49
50/* Initial register settings for AR5210 */
51static const struct ath5k_ini ar5210_ini[] = {
52 /* PCU and MAC registers */
53 { AR5K_NOQCU_TXDP0, 0 },
54 { AR5K_NOQCU_TXDP1, 0 },
55 { AR5K_RXDP, 0 },

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386};
387
388/* Initial mode-specific settings for AR5211
389 * 5211 supports OFDM-only g (draft g) but we
390 * need to test it !
391 */
392static const struct ath5k_ini_mode ar5211_ini_mode[] = {
393 { AR5K_TXCFG,
48};
49
50/* Initial register settings for AR5210 */
51static const struct ath5k_ini ar5210_ini[] = {
52 /* PCU and MAC registers */
53 { AR5K_NOQCU_TXDP0, 0 },
54 { AR5K_NOQCU_TXDP1, 0 },
55 { AR5K_RXDP, 0 },

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386};
387
388/* Initial mode-specific settings for AR5211
389 * 5211 supports OFDM-only g (draft g) but we
390 * need to test it !
391 */
392static const struct ath5k_ini_mode ar5211_ini_mode[] = {
393 { AR5K_TXCFG,
394 /* a aTurbo b g (OFDM) */
395 { 0x00000015, 0x00000015, 0x0000001d, 0x00000015 } },
394 /* A/XR B G */
395 { 0x00000015, 0x0000001d, 0x00000015 } },
396 { AR5K_QUEUE_DFS_LOCAL_IFS(0),
396 { AR5K_QUEUE_DFS_LOCAL_IFS(0),
397 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
397 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
398 { AR5K_QUEUE_DFS_LOCAL_IFS(1),
398 { AR5K_QUEUE_DFS_LOCAL_IFS(1),
399 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
399 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
400 { AR5K_QUEUE_DFS_LOCAL_IFS(2),
400 { AR5K_QUEUE_DFS_LOCAL_IFS(2),
401 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
401 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
402 { AR5K_QUEUE_DFS_LOCAL_IFS(3),
402 { AR5K_QUEUE_DFS_LOCAL_IFS(3),
403 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
403 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
404 { AR5K_QUEUE_DFS_LOCAL_IFS(4),
404 { AR5K_QUEUE_DFS_LOCAL_IFS(4),
405 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
405 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
406 { AR5K_QUEUE_DFS_LOCAL_IFS(5),
406 { AR5K_QUEUE_DFS_LOCAL_IFS(5),
407 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
407 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
408 { AR5K_QUEUE_DFS_LOCAL_IFS(6),
408 { AR5K_QUEUE_DFS_LOCAL_IFS(6),
409 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
409 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
410 { AR5K_QUEUE_DFS_LOCAL_IFS(7),
410 { AR5K_QUEUE_DFS_LOCAL_IFS(7),
411 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
411 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
412 { AR5K_QUEUE_DFS_LOCAL_IFS(8),
412 { AR5K_QUEUE_DFS_LOCAL_IFS(8),
413 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
413 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
414 { AR5K_QUEUE_DFS_LOCAL_IFS(9),
414 { AR5K_QUEUE_DFS_LOCAL_IFS(9),
415 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
415 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
416 { AR5K_DCU_GBL_IFS_SLOT,
416 { AR5K_DCU_GBL_IFS_SLOT,
417 { 0x00000168, 0x000001e0, 0x000001b8, 0x00000168 } },
417 { 0x00000168, 0x000001b8, 0x00000168 } },
418 { AR5K_DCU_GBL_IFS_SIFS,
418 { AR5K_DCU_GBL_IFS_SIFS,
419 { 0x00000230, 0x000001e0, 0x000000b0, 0x00000230 } },
419 { 0x00000230, 0x000000b0, 0x00000230 } },
420 { AR5K_DCU_GBL_IFS_EIFS,
420 { AR5K_DCU_GBL_IFS_EIFS,
421 { 0x00000d98, 0x00001180, 0x00001f48, 0x00000d98 } },
421 { 0x00000d98, 0x00001f48, 0x00000d98 } },
422 { AR5K_DCU_GBL_IFS_MISC,
422 { AR5K_DCU_GBL_IFS_MISC,
423 { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000a0e0 } },
423 { 0x0000a0e0, 0x00005880, 0x0000a0e0 } },
424 { AR5K_TIME_OUT,
424 { AR5K_TIME_OUT,
425 { 0x04000400, 0x08000800, 0x20003000, 0x04000400 } },
425 { 0x04000400, 0x20003000, 0x04000400 } },
426 { AR5K_USEC_5211,
426 { AR5K_USEC_5211,
427 { 0x0e8d8fa7, 0x0e8d8fcf, 0x01608f95, 0x0e8d8fa7 } },
428 { AR5K_PHY_TURBO,
429 { 0x00000000, 0x00000003, 0x00000000, 0x00000000 } },
427 { 0x0e8d8fa7, 0x01608f95, 0x0e8d8fa7 } },
430 { AR5K_PHY(8),
428 { AR5K_PHY(8),
431 { 0x02020200, 0x02020200, 0x02010200, 0x02020200 } },
432 { AR5K_PHY(9),
433 { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e } },
434 { AR5K_PHY(10),
435 { 0x0a020001, 0x0a020001, 0x05010000, 0x0a020001 } },
436 { AR5K_PHY(13),
437 { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
438 { AR5K_PHY(14),
439 { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b } },
440 { AR5K_PHY(17),
441 { 0x1372169c, 0x137216a5, 0x137216a8, 0x1372169c } },
442 { AR5K_PHY(18),
443 { 0x0018ba67, 0x0018ba67, 0x0018ba69, 0x0018ba69 } },
444 { AR5K_PHY(20),
445 { 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 } },
429 { 0x02020200, 0x02010200, 0x02020200 } },
430 { AR5K_PHY_RF_CTL2,
431 { 0x00000e0e, 0x00000707, 0x00000e0e } },
432 { AR5K_PHY_RF_CTL3,
433 { 0x0a020001, 0x05010000, 0x0a020001 } },
434 { AR5K_PHY_RF_CTL4,
435 { 0x00000e0e, 0x00000e0e, 0x00000e0e } },
436 { AR5K_PHY_PA_CTL,
437 { 0x00000007, 0x0000000b, 0x0000000b } },
438 { AR5K_PHY_SETTLING,
439 { 0x1372169c, 0x137216a8, 0x1372169c } },
440 { AR5K_PHY_GAIN,
441 { 0x0018ba67, 0x0018ba69, 0x0018ba69 } },
442 { AR5K_PHY_DESIRED_SIZE,
443 { 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 } },
446 { AR5K_PHY_SIG,
444 { AR5K_PHY_SIG,
447 { 0x7e800d2e, 0x7e800d2e, 0x7ec00d2e, 0x7e800d2e } },
445 { 0x7e800d2e, 0x7ec00d2e, 0x7e800d2e } },
448 { AR5K_PHY_AGCCOARSE,
446 { AR5K_PHY_AGCCOARSE,
449 { 0x31375d5e, 0x31375d5e, 0x313a5d5e, 0x31375d5e } },
447 { 0x31375d5e, 0x313a5d5e, 0x31375d5e } },
450 { AR5K_PHY_AGCCTL,
448 { AR5K_PHY_AGCCTL,
451 { 0x0000bd10, 0x0000bd10, 0x0000bd38, 0x0000bd10 } },
449 { 0x0000bd10, 0x0000bd38, 0x0000bd10 } },
452 { AR5K_PHY_NF,
450 { AR5K_PHY_NF,
453 { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
451 { 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
454 { AR5K_PHY_RX_DELAY,
452 { AR5K_PHY_RX_DELAY,
455 { 0x00002710, 0x00002710, 0x0000157c, 0x00002710 } },
453 { 0x00002710, 0x0000157c, 0x00002710 } },
456 { AR5K_PHY(70),
454 { AR5K_PHY(70),
457 { 0x00000190, 0x00000190, 0x00000084, 0x00000190 } },
455 { 0x00000190, 0x00000084, 0x00000190 } },
458 { AR5K_PHY_FRAME_CTL_5211,
456 { AR5K_PHY_FRAME_CTL_5211,
459 { 0x6fe01020, 0x6fe01020, 0x6fe00920, 0x6fe01020 } },
457 { 0x6fe01020, 0x6fe00920, 0x6fe01020 } },
460 { AR5K_PHY_PCDAC_TXPOWER_BASE,
458 { AR5K_PHY_PCDAC_TXPOWER_BASE,
461 { 0x05ff14ff, 0x05ff14ff, 0x05ff14ff, 0x05ff19ff } },
459 { 0x05ff14ff, 0x05ff14ff, 0x05ff19ff } },
462 { AR5K_RF_BUFFER_CONTROL_4,
460 { AR5K_RF_BUFFER_CONTROL_4,
463 { 0x00000010, 0x00000014, 0x00000010, 0x00000010 } },
461 { 0x00000010, 0x00000010, 0x00000010 } },
464};
465
466/* Initial register settings for AR5212 */
467static const struct ath5k_ini ar5212_ini_common_start[] = {
468 { AR5K_RXDP, 0x00000000 },
469 { AR5K_RXCFG, 0x00000005 },
470 { AR5K_MIBC, 0x00000000 },
471 { AR5K_TOPS, 0x00000008 },

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672 { AR5K_PHY(656), 0x38490a20 },
673 { AR5K_PHY(657), 0x00007bb6 },
674 { AR5K_PHY(658), 0x0fff3ffc },
675};
676
677/* Initial mode-specific settings for AR5212 (Written before ar5212_ini) */
678static const struct ath5k_ini_mode ar5212_ini_mode_start[] = {
679 { AR5K_QUEUE_DFS_LOCAL_IFS(0),
462};
463
464/* Initial register settings for AR5212 */
465static const struct ath5k_ini ar5212_ini_common_start[] = {
466 { AR5K_RXDP, 0x00000000 },
467 { AR5K_RXCFG, 0x00000005 },
468 { AR5K_MIBC, 0x00000000 },
469 { AR5K_TOPS, 0x00000008 },

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670 { AR5K_PHY(656), 0x38490a20 },
671 { AR5K_PHY(657), 0x00007bb6 },
672 { AR5K_PHY(658), 0x0fff3ffc },
673};
674
675/* Initial mode-specific settings for AR5212 (Written before ar5212_ini) */
676static const struct ath5k_ini_mode ar5212_ini_mode_start[] = {
677 { AR5K_QUEUE_DFS_LOCAL_IFS(0),
680 /* a/XR aTurbo b g (DYN) gTurbo */
681 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
678 /* A/XR B G */
679 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
682 { AR5K_QUEUE_DFS_LOCAL_IFS(1),
680 { AR5K_QUEUE_DFS_LOCAL_IFS(1),
683 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
681 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
684 { AR5K_QUEUE_DFS_LOCAL_IFS(2),
682 { AR5K_QUEUE_DFS_LOCAL_IFS(2),
685 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
683 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
686 { AR5K_QUEUE_DFS_LOCAL_IFS(3),
684 { AR5K_QUEUE_DFS_LOCAL_IFS(3),
687 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
685 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
688 { AR5K_QUEUE_DFS_LOCAL_IFS(4),
686 { AR5K_QUEUE_DFS_LOCAL_IFS(4),
689 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
687 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
690 { AR5K_QUEUE_DFS_LOCAL_IFS(5),
688 { AR5K_QUEUE_DFS_LOCAL_IFS(5),
691 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
689 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
692 { AR5K_QUEUE_DFS_LOCAL_IFS(6),
690 { AR5K_QUEUE_DFS_LOCAL_IFS(6),
693 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
691 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
694 { AR5K_QUEUE_DFS_LOCAL_IFS(7),
692 { AR5K_QUEUE_DFS_LOCAL_IFS(7),
695 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
693 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
696 { AR5K_QUEUE_DFS_LOCAL_IFS(8),
694 { AR5K_QUEUE_DFS_LOCAL_IFS(8),
697 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
695 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
698 { AR5K_QUEUE_DFS_LOCAL_IFS(9),
696 { AR5K_QUEUE_DFS_LOCAL_IFS(9),
699 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
697 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
700 { AR5K_DCU_GBL_IFS_SIFS,
698 { AR5K_DCU_GBL_IFS_SIFS,
701 { 0x00000230, 0x000001e0, 0x000000b0, 0x00000160, 0x000001e0 } },
699 { 0x00000230, 0x000000b0, 0x00000160 } },
702 { AR5K_DCU_GBL_IFS_SLOT,
700 { AR5K_DCU_GBL_IFS_SLOT,
703 { 0x00000168, 0x000001e0, 0x000001b8, 0x0000018c, 0x000001e0 } },
701 { 0x00000168, 0x000001b8, 0x0000018c } },
704 { AR5K_DCU_GBL_IFS_EIFS,
702 { AR5K_DCU_GBL_IFS_EIFS,
705 { 0x00000e60, 0x00001180, 0x00001f1c, 0x00003e38, 0x00001180 } },
703 { 0x00000e60, 0x00001f1c, 0x00003e38 } },
706 { AR5K_DCU_GBL_IFS_MISC,
704 { AR5K_DCU_GBL_IFS_MISC,
707 { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000b0e0, 0x00014068 } },
705 { 0x0000a0e0, 0x00005880, 0x0000b0e0 } },
708 { AR5K_TIME_OUT,
706 { AR5K_TIME_OUT,
709 { 0x03e803e8, 0x06e006e0, 0x04200420, 0x08400840, 0x06e006e0 } },
710 { AR5K_PHY_TURBO,
711 { 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000003 } },
707 { 0x03e803e8, 0x04200420, 0x08400840 } },
712 { AR5K_PHY(8),
708 { AR5K_PHY(8),
713 { 0x02020200, 0x02020200, 0x02010200, 0x02020200, 0x02020200 } },
709 { 0x02020200, 0x02010200, 0x02020200 } },
714 { AR5K_PHY_RF_CTL2,
710 { AR5K_PHY_RF_CTL2,
715 { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e, 0x00000e0e } },
711 { 0x00000e0e, 0x00000707, 0x00000e0e } },
716 { AR5K_PHY_SETTLING,
712 { AR5K_PHY_SETTLING,
717 { 0x1372161c, 0x13721c25, 0x13721722, 0x137216a2, 0x13721c25 } },
713 { 0x1372161c, 0x13721722, 0x137216a2 } },
718 { AR5K_PHY_AGCCTL,
714 { AR5K_PHY_AGCCTL,
719 { 0x00009d10, 0x00009d10, 0x00009d18, 0x00009d18, 0x00009d10 } },
715 { 0x00009d10, 0x00009d18, 0x00009d18 } },
720 { AR5K_PHY_NF,
716 { AR5K_PHY_NF,
721 { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
717 { 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
722 { AR5K_PHY_WEAK_OFDM_HIGH_THR,
718 { AR5K_PHY_WEAK_OFDM_HIGH_THR,
723 { 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 } },
719 { 0x409a4190, 0x409a4190, 0x409a4190 } },
724 { AR5K_PHY(70),
720 { AR5K_PHY(70),
725 { 0x000001b8, 0x000001b8, 0x00000084, 0x00000108, 0x000001b8 } },
721 { 0x000001b8, 0x00000084, 0x00000108 } },
726 { AR5K_PHY_OFDM_SELFCORR,
722 { AR5K_PHY_OFDM_SELFCORR,
727 { 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05 } },
723 { 0x10058a05, 0x10058a05, 0x10058a05 } },
728 { 0xa230,
724 { 0xa230,
729 { 0x00000000, 0x00000000, 0x00000000, 0x00000108, 0x00000000 } },
725 { 0x00000000, 0x00000000, 0x00000108 } },
730};
731
732/* Initial mode-specific settings for AR5212 + RF5111 (Written after ar5212_ini) */
733static const struct ath5k_ini_mode rf5111_ini_mode_end[] = {
734 { AR5K_TXCFG,
726};
727
728/* Initial mode-specific settings for AR5212 + RF5111 (Written after ar5212_ini) */
729static const struct ath5k_ini_mode rf5111_ini_mode_end[] = {
730 { AR5K_TXCFG,
735 /* a/XR aTurbo b g (DYN) gTurbo */
736 { 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } },
731 /* A/XR B G */
732 { 0x00008015, 0x00008015, 0x00008015 } },
737 { AR5K_USEC_5211,
733 { AR5K_USEC_5211,
738 { 0x128d8fa7, 0x09880fcf, 0x04e00f95, 0x12e00fab, 0x09880fcf } },
734 { 0x128d8fa7, 0x04e00f95, 0x12e00fab } },
739 { AR5K_PHY_RF_CTL3,
735 { AR5K_PHY_RF_CTL3,
740 { 0x0a020001, 0x0a020001, 0x05010100, 0x0a020001, 0x0a020001 } },
736 { 0x0a020001, 0x05010100, 0x0a020001 } },
741 { AR5K_PHY_RF_CTL4,
737 { AR5K_PHY_RF_CTL4,
742 { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
738 { 0x00000e0e, 0x00000e0e, 0x00000e0e } },
743 { AR5K_PHY_PA_CTL,
739 { AR5K_PHY_PA_CTL,
744 { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
740 { 0x00000007, 0x0000000b, 0x0000000b } },
745 { AR5K_PHY_GAIN,
741 { AR5K_PHY_GAIN,
746 { 0x0018da5a, 0x0018da5a, 0x0018ca69, 0x0018ca69, 0x0018ca69 } },
742 { 0x0018da5a, 0x0018ca69, 0x0018ca69 } },
747 { AR5K_PHY_DESIRED_SIZE,
743 { AR5K_PHY_DESIRED_SIZE,
748 { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
744 { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
749 { AR5K_PHY_SIG,
745 { AR5K_PHY_SIG,
750 { 0x7e800d2e, 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e, 0x7e800d2e } },
746 { 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e } },
751 { AR5K_PHY_AGCCOARSE,
747 { AR5K_PHY_AGCCOARSE,
752 { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137615e } },
748 { 0x3137665e, 0x3137665e, 0x3137665e } },
753 { AR5K_PHY_WEAK_OFDM_LOW_THR,
749 { AR5K_PHY_WEAK_OFDM_LOW_THR,
754 { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb080, 0x050cb080 } },
750 { 0x050cb081, 0x050cb081, 0x050cb080 } },
755 { AR5K_PHY_RX_DELAY,
751 { AR5K_PHY_RX_DELAY,
756 { 0x00002710, 0x00002710, 0x0000157c, 0x00002af8, 0x00002710 } },
752 { 0x00002710, 0x0000157c, 0x00002af8 } },
757 { AR5K_PHY_FRAME_CTL_5211,
753 { AR5K_PHY_FRAME_CTL_5211,
758 { 0xf7b81020, 0xf7b81020, 0xf7b80d20, 0xf7b81020, 0xf7b81020 } },
754 { 0xf7b81020, 0xf7b80d20, 0xf7b81020 } },
759 { AR5K_PHY_GAIN_2GHZ,
755 { AR5K_PHY_GAIN_2GHZ,
760 { 0x642c416a, 0x642c416a, 0x6440416a, 0x6440416a, 0x6440416a } },
756 { 0x642c416a, 0x6440416a, 0x6440416a } },
761 { AR5K_PHY_CCK_RX_CTL_4,
757 { AR5K_PHY_CCK_RX_CTL_4,
762 { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } },
758 { 0x1883800a, 0x1873800a, 0x1883800a } },
763};
764
765static const struct ath5k_ini rf5111_ini_common_end[] = {
766 { AR5K_DCU_FP, 0x00000000 },
767 { AR5K_PHY_AGC, 0x00000000 },
768 { AR5K_PHY_ADC_CTL, 0x00022ffe },
769 { 0x983c, 0x00020100 },
770 { AR5K_PHY_GAIN_OFFSET, 0x1284613c },

--- 6 unchanged lines hidden (view full) ---

777 { AR5K_PHY_CCK_CROSSCORR, 0xd03e6788 },
778 { AR5K_PHY_DAG_CCK_CTL, 0x000001b5 },
779 { 0xa23c, 0x13c889af },
780};
781
782/* Initial mode-specific settings for AR5212 + RF5112 (Written after ar5212_ini) */
783static const struct ath5k_ini_mode rf5112_ini_mode_end[] = {
784 { AR5K_TXCFG,
759};
760
761static const struct ath5k_ini rf5111_ini_common_end[] = {
762 { AR5K_DCU_FP, 0x00000000 },
763 { AR5K_PHY_AGC, 0x00000000 },
764 { AR5K_PHY_ADC_CTL, 0x00022ffe },
765 { 0x983c, 0x00020100 },
766 { AR5K_PHY_GAIN_OFFSET, 0x1284613c },

--- 6 unchanged lines hidden (view full) ---

773 { AR5K_PHY_CCK_CROSSCORR, 0xd03e6788 },
774 { AR5K_PHY_DAG_CCK_CTL, 0x000001b5 },
775 { 0xa23c, 0x13c889af },
776};
777
778/* Initial mode-specific settings for AR5212 + RF5112 (Written after ar5212_ini) */
779static const struct ath5k_ini_mode rf5112_ini_mode_end[] = {
780 { AR5K_TXCFG,
785 /* a/XR aTurbo b g (DYN) gTurbo */
786 { 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } },
781 /* A/XR B G */
782 { 0x00008015, 0x00008015, 0x00008015 } },
787 { AR5K_USEC_5211,
783 { AR5K_USEC_5211,
788 { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
784 { 0x128d93a7, 0x04e01395, 0x12e013ab } },
789 { AR5K_PHY_RF_CTL3,
785 { AR5K_PHY_RF_CTL3,
790 { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
786 { 0x0a020001, 0x05020100, 0x0a020001 } },
791 { AR5K_PHY_RF_CTL4,
787 { AR5K_PHY_RF_CTL4,
792 { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
788 { 0x00000e0e, 0x00000e0e, 0x00000e0e } },
793 { AR5K_PHY_PA_CTL,
789 { AR5K_PHY_PA_CTL,
794 { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
790 { 0x00000007, 0x0000000b, 0x0000000b } },
795 { AR5K_PHY_GAIN,
791 { AR5K_PHY_GAIN,
796 { 0x0018da6d, 0x0018da6d, 0x0018ca75, 0x0018ca75, 0x0018ca75 } },
792 { 0x0018da6d, 0x0018ca75, 0x0018ca75 } },
797 { AR5K_PHY_DESIRED_SIZE,
793 { AR5K_PHY_DESIRED_SIZE,
798 { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
794 { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
799 { AR5K_PHY_SIG,
795 { AR5K_PHY_SIG,
800 { 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ee80d2e, 0x7e800d2e } },
796 { 0x7e800d2e, 0x7ee80d2e, 0x7ee80d2e } },
801 { AR5K_PHY_AGCCOARSE,
797 { AR5K_PHY_AGCCOARSE,
802 { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e } },
798 { 0x3137665e, 0x3137665e, 0x3137665e } },
803 { AR5K_PHY_WEAK_OFDM_LOW_THR,
799 { AR5K_PHY_WEAK_OFDM_LOW_THR,
804 { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
800 { 0x050cb081, 0x050cb081, 0x050cb081 } },
805 { AR5K_PHY_RX_DELAY,
801 { AR5K_PHY_RX_DELAY,
806 { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
802 { 0x000007d0, 0x0000044c, 0x00000898 } },
807 { AR5K_PHY_FRAME_CTL_5211,
803 { AR5K_PHY_FRAME_CTL_5211,
808 { 0xf7b81020, 0xf7b81020, 0xf7b80d10, 0xf7b81010, 0xf7b81010 } },
804 { 0xf7b81020, 0xf7b80d10, 0xf7b81010 } },
809 { AR5K_PHY_CCKTXCTL,
805 { AR5K_PHY_CCKTXCTL,
810 { 0x00000000, 0x00000000, 0x00000008, 0x00000008, 0x00000008 } },
806 { 0x00000000, 0x00000008, 0x00000008 } },
811 { AR5K_PHY_CCK_CROSSCORR,
807 { AR5K_PHY_CCK_CROSSCORR,
812 { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
808 { 0xd6be6788, 0xd03e6788, 0xd03e6788 } },
813 { AR5K_PHY_GAIN_2GHZ,
809 { AR5K_PHY_GAIN_2GHZ,
814 { 0x642c0140, 0x642c0140, 0x6442c160, 0x6442c160, 0x6442c160 } },
810 { 0x642c0140, 0x6442c160, 0x6442c160 } },
815 { AR5K_PHY_CCK_RX_CTL_4,
811 { AR5K_PHY_CCK_RX_CTL_4,
816 { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } },
812 { 0x1883800a, 0x1873800a, 0x1883800a } },
817};
818
819static const struct ath5k_ini rf5112_ini_common_end[] = {
820 { AR5K_DCU_FP, 0x00000000 },
821 { AR5K_PHY_AGC, 0x00000000 },
822 { AR5K_PHY_ADC_CTL, 0x00022ffe },
823 { 0x983c, 0x00020100 },
824 { AR5K_PHY_GAIN_OFFSET, 0x1284613c },
825 { AR5K_PHY_PAPD_PROBE, 0x00004882 },
826 { 0x9940, 0x00000004 },
827 { 0x9958, 0x000000ff },
828 { 0x9974, 0x00000000 },
829 { AR5K_PHY_DAG_CCK_CTL, 0x000001b5 },
830 { 0xa23c, 0x13c889af },
831};
832
833/* Initial mode-specific settings for RF5413/5414 (Written after ar5212_ini) */
834static const struct ath5k_ini_mode rf5413_ini_mode_end[] = {
835 { AR5K_TXCFG,
813};
814
815static const struct ath5k_ini rf5112_ini_common_end[] = {
816 { AR5K_DCU_FP, 0x00000000 },
817 { AR5K_PHY_AGC, 0x00000000 },
818 { AR5K_PHY_ADC_CTL, 0x00022ffe },
819 { 0x983c, 0x00020100 },
820 { AR5K_PHY_GAIN_OFFSET, 0x1284613c },
821 { AR5K_PHY_PAPD_PROBE, 0x00004882 },
822 { 0x9940, 0x00000004 },
823 { 0x9958, 0x000000ff },
824 { 0x9974, 0x00000000 },
825 { AR5K_PHY_DAG_CCK_CTL, 0x000001b5 },
826 { 0xa23c, 0x13c889af },
827};
828
829/* Initial mode-specific settings for RF5413/5414 (Written after ar5212_ini) */
830static const struct ath5k_ini_mode rf5413_ini_mode_end[] = {
831 { AR5K_TXCFG,
836 /* a/XR aTurbo b g (DYN) gTurbo */
837 { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
832 /* A/XR B G */
833 { 0x00000015, 0x00000015, 0x00000015 } },
838 { AR5K_USEC_5211,
834 { AR5K_USEC_5211,
839 { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
835 { 0x128d93a7, 0x04e01395, 0x12e013ab } },
840 { AR5K_PHY_RF_CTL3,
836 { AR5K_PHY_RF_CTL3,
841 { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
837 { 0x0a020001, 0x05020100, 0x0a020001 } },
842 { AR5K_PHY_RF_CTL4,
838 { AR5K_PHY_RF_CTL4,
843 { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
839 { 0x00000e0e, 0x00000e0e, 0x00000e0e } },
844 { AR5K_PHY_PA_CTL,
840 { AR5K_PHY_PA_CTL,
845 { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
841 { 0x00000007, 0x0000000b, 0x0000000b } },
846 { AR5K_PHY_GAIN,
842 { AR5K_PHY_GAIN,
847 { 0x0018fa61, 0x0018fa61, 0x001a1a63, 0x001a1a63, 0x001a1a63 } },
843 { 0x0018fa61, 0x001a1a63, 0x001a1a63 } },
848 { AR5K_PHY_DESIRED_SIZE,
844 { AR5K_PHY_DESIRED_SIZE,
849 { 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da, 0x0c98b0da } },
845 { 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da } },
850 { AR5K_PHY_SIG,
846 { AR5K_PHY_SIG,
851 { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },
847 { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },
852 { AR5K_PHY_AGCCOARSE,
848 { AR5K_PHY_AGCCOARSE,
853 { 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e } },
849 { 0x3139605e, 0x3139605e, 0x3139605e } },
854 { AR5K_PHY_WEAK_OFDM_LOW_THR,
850 { AR5K_PHY_WEAK_OFDM_LOW_THR,
855 { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
851 { 0x050cb081, 0x050cb081, 0x050cb081 } },
856 { AR5K_PHY_RX_DELAY,
852 { AR5K_PHY_RX_DELAY,
857 { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
853 { 0x000007d0, 0x0000044c, 0x00000898 } },
858 { AR5K_PHY_FRAME_CTL_5211,
854 { AR5K_PHY_FRAME_CTL_5211,
859 { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
855 { 0xf7b81000, 0xf7b80d00, 0xf7b81000 } },
860 { AR5K_PHY_CCKTXCTL,
856 { AR5K_PHY_CCKTXCTL,
861 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
857 { 0x00000000, 0x00000000, 0x00000000 } },
862 { AR5K_PHY_CCK_CROSSCORR,
858 { AR5K_PHY_CCK_CROSSCORR,
863 { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
859 { 0xd6be6788, 0xd03e6788, 0xd03e6788 } },
864 { AR5K_PHY_GAIN_2GHZ,
860 { AR5K_PHY_GAIN_2GHZ,
865 { 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 } },
861 { 0x002ec1e0, 0x002ac120, 0x002ac120 } },
866 { AR5K_PHY_CCK_RX_CTL_4,
862 { AR5K_PHY_CCK_RX_CTL_4,
867 { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
863 { 0x1883800a, 0x1863800a, 0x1883800a } },
868 { 0xa300,
864 { 0xa300,
869 { 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 } },
865 { 0x18010000, 0x18010000, 0x18010000 } },
870 { 0xa304,
866 { 0xa304,
871 { 0x30032602, 0x30032602, 0x30032602, 0x30032602, 0x30032602 } },
867 { 0x30032602, 0x30032602, 0x30032602 } },
872 { 0xa308,
868 { 0xa308,
873 { 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06 } },
869 { 0x48073e06, 0x48073e06, 0x48073e06 } },
874 { 0xa30c,
870 { 0xa30c,
875 { 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a } },
871 { 0x560b4c0a, 0x560b4c0a, 0x560b4c0a } },
876 { 0xa310,
872 { 0xa310,
877 { 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f } },
873 { 0x641a600f, 0x641a600f, 0x641a600f } },
878 { 0xa314,
874 { 0xa314,
879 { 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b } },
875 { 0x784f6e1b, 0x784f6e1b, 0x784f6e1b } },
880 { 0xa318,
876 { 0xa318,
881 { 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a } },
877 { 0x868f7c5a, 0x868f7c5a, 0x868f7c5a } },
882 { 0xa31c,
878 { 0xa31c,
883 { 0x90cf865b, 0x90cf865b, 0x8ecf865b, 0x8ecf865b, 0x8ecf865b } },
879 { 0x90cf865b, 0x8ecf865b, 0x8ecf865b } },
884 { 0xa320,
880 { 0xa320,
885 { 0x9d4f970f, 0x9d4f970f, 0x9b4f970f, 0x9b4f970f, 0x9b4f970f } },
881 { 0x9d4f970f, 0x9b4f970f, 0x9b4f970f } },
886 { 0xa324,
882 { 0xa324,
887 { 0xa7cfa38f, 0xa7cfa38f, 0xa3cf9f8f, 0xa3cf9f8f, 0xa3cf9f8f } },
883 { 0xa7cfa38f, 0xa3cf9f8f, 0xa3cf9f8f } },
888 { 0xa328,
884 { 0xa328,
889 { 0xb55faf1f, 0xb55faf1f, 0xb35faf1f, 0xb35faf1f, 0xb35faf1f } },
885 { 0xb55faf1f, 0xb35faf1f, 0xb35faf1f } },
890 { 0xa32c,
886 { 0xa32c,
891 { 0xbddfb99f, 0xbddfb99f, 0xbbdfb99f, 0xbbdfb99f, 0xbbdfb99f } },
887 { 0xbddfb99f, 0xbbdfb99f, 0xbbdfb99f } },
892 { 0xa330,
888 { 0xa330,
893 { 0xcb7fc53f, 0xcb7fc53f, 0xcb7fc73f, 0xcb7fc73f, 0xcb7fc73f } },
889 { 0xcb7fc53f, 0xcb7fc73f, 0xcb7fc73f } },
894 { 0xa334,
890 { 0xa334,
895 { 0xd5ffd1bf, 0xd5ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf } },
891 { 0xd5ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf } },
896};
897
898static const struct ath5k_ini rf5413_ini_common_end[] = {
899 { AR5K_DCU_FP, 0x000003e0 },
900 { AR5K_5414_CBCFG, 0x00000010 },
901 { AR5K_SEQ_MASK, 0x0000000f },
902 { 0x809c, 0x00000000 },
903 { 0x80a0, 0x00000000 },

--- 63 unchanged lines hidden (view full) ---

967 { 0xa380, 0x7f3c7bba },
968 { 0xa384, 0xf3307ff0 },
969};
970
971/* Initial mode-specific settings for RF2413/2414 (Written after ar5212_ini) */
972/* XXX: a mode ? */
973static const struct ath5k_ini_mode rf2413_ini_mode_end[] = {
974 { AR5K_TXCFG,
892};
893
894static const struct ath5k_ini rf5413_ini_common_end[] = {
895 { AR5K_DCU_FP, 0x000003e0 },
896 { AR5K_5414_CBCFG, 0x00000010 },
897 { AR5K_SEQ_MASK, 0x0000000f },
898 { 0x809c, 0x00000000 },
899 { 0x80a0, 0x00000000 },

--- 63 unchanged lines hidden (view full) ---

963 { 0xa380, 0x7f3c7bba },
964 { 0xa384, 0xf3307ff0 },
965};
966
967/* Initial mode-specific settings for RF2413/2414 (Written after ar5212_ini) */
968/* XXX: a mode ? */
969static const struct ath5k_ini_mode rf2413_ini_mode_end[] = {
970 { AR5K_TXCFG,
975 /* a/XR aTurbo b g (DYN) gTurbo */
976 { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
971 /* A/XR B G */
972 { 0x00000015, 0x00000015, 0x00000015 } },
977 { AR5K_USEC_5211,
973 { AR5K_USEC_5211,
978 { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
974 { 0x128d93a7, 0x04e01395, 0x12e013ab } },
979 { AR5K_PHY_RF_CTL3,
975 { AR5K_PHY_RF_CTL3,
980 { 0x0a020001, 0x0a020001, 0x05020000, 0x0a020001, 0x0a020001 } },
976 { 0x0a020001, 0x05020000, 0x0a020001 } },
981 { AR5K_PHY_RF_CTL4,
977 { AR5K_PHY_RF_CTL4,
982 { 0x00000e00, 0x00000e00, 0x00000e00, 0x00000e00, 0x00000e00 } },
978 { 0x00000e00, 0x00000e00, 0x00000e00 } },
983 { AR5K_PHY_PA_CTL,
979 { AR5K_PHY_PA_CTL,
984 { 0x00000002, 0x00000002, 0x0000000a, 0x0000000a, 0x0000000a } },
980 { 0x00000002, 0x0000000a, 0x0000000a } },
985 { AR5K_PHY_GAIN,
981 { AR5K_PHY_GAIN,
986 { 0x0018da6d, 0x0018da6d, 0x001a6a64, 0x001a6a64, 0x001a6a64 } },
982 { 0x0018da6d, 0x001a6a64, 0x001a6a64 } },
987 { AR5K_PHY_DESIRED_SIZE,
983 { AR5K_PHY_DESIRED_SIZE,
988 { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b0da, 0x0c98b0da, 0x0de8b0da } },
984 { 0x0de8b4e0, 0x0de8b0da, 0x0c98b0da } },
989 { AR5K_PHY_SIG,
985 { AR5K_PHY_SIG,
990 { 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ec80d2e, 0x7e800d2e } },
986 { 0x7e800d2e, 0x7ee80d2e, 0x7ec80d2e } },
991 { AR5K_PHY_AGCCOARSE,
987 { AR5K_PHY_AGCCOARSE,
992 { 0x3137665e, 0x3137665e, 0x3137665e, 0x3139605e, 0x3137665e } },
988 { 0x3137665e, 0x3137665e, 0x3139605e } },
993 { AR5K_PHY_WEAK_OFDM_LOW_THR,
989 { AR5K_PHY_WEAK_OFDM_LOW_THR,
994 { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
990 { 0x050cb081, 0x050cb081, 0x050cb081 } },
995 { AR5K_PHY_RX_DELAY,
991 { AR5K_PHY_RX_DELAY,
996 { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
992 { 0x000007d0, 0x0000044c, 0x00000898 } },
997 { AR5K_PHY_FRAME_CTL_5211,
993 { AR5K_PHY_FRAME_CTL_5211,
998 { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
994 { 0xf7b81000, 0xf7b80d00, 0xf7b81000 } },
999 { AR5K_PHY_CCKTXCTL,
995 { AR5K_PHY_CCKTXCTL,
1000 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
996 { 0x00000000, 0x00000000, 0x00000000 } },
1001 { AR5K_PHY_CCK_CROSSCORR,
997 { AR5K_PHY_CCK_CROSSCORR,
1002 { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
998 { 0xd6be6788, 0xd03e6788, 0xd03e6788 } },
1003 { AR5K_PHY_GAIN_2GHZ,
999 { AR5K_PHY_GAIN_2GHZ,
1004 { 0x002c0140, 0x002c0140, 0x0042c140, 0x0042c140, 0x0042c140 } },
1000 { 0x002c0140, 0x0042c140, 0x0042c140 } },
1005 { AR5K_PHY_CCK_RX_CTL_4,
1001 { AR5K_PHY_CCK_RX_CTL_4,
1006 { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
1002 { 0x1883800a, 0x1863800a, 0x1883800a } },
1007};
1008
1009static const struct ath5k_ini rf2413_ini_common_end[] = {
1010 { AR5K_DCU_FP, 0x000003e0 },
1011 { AR5K_SEQ_MASK, 0x0000000f },
1012 { AR5K_MIC_QOS_CTL, 0x00000000 },
1013 { AR5K_MIC_QOS_SEL, 0x00000000 },
1014 { AR5K_MISC_MODE, 0x00000000 },

--- 74 unchanged lines hidden (view full) ---

1089 { 0xa380, 0x7f3c7bba },
1090 { 0xa384, 0xf3307ff0 },
1091};
1092
1093/* Initial mode-specific settings for RF2425 (Written after ar5212_ini) */
1094/* XXX: a mode ? */
1095static const struct ath5k_ini_mode rf2425_ini_mode_end[] = {
1096 { AR5K_TXCFG,
1003};
1004
1005static const struct ath5k_ini rf2413_ini_common_end[] = {
1006 { AR5K_DCU_FP, 0x000003e0 },
1007 { AR5K_SEQ_MASK, 0x0000000f },
1008 { AR5K_MIC_QOS_CTL, 0x00000000 },
1009 { AR5K_MIC_QOS_SEL, 0x00000000 },
1010 { AR5K_MISC_MODE, 0x00000000 },

--- 74 unchanged lines hidden (view full) ---

1085 { 0xa380, 0x7f3c7bba },
1086 { 0xa384, 0xf3307ff0 },
1087};
1088
1089/* Initial mode-specific settings for RF2425 (Written after ar5212_ini) */
1090/* XXX: a mode ? */
1091static const struct ath5k_ini_mode rf2425_ini_mode_end[] = {
1092 { AR5K_TXCFG,
1097 /* a/XR aTurbo b g (DYN) gTurbo */
1098 { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
1093 /* A/XR B G */
1094 { 0x00000015, 0x00000015, 0x00000015 } },
1099 { AR5K_USEC_5211,
1095 { AR5K_USEC_5211,
1100 { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
1101 { AR5K_PHY_TURBO,
1102 { 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000001 } },
1096 { 0x128d93a7, 0x04e01395, 0x12e013ab } },
1103 { AR5K_PHY_RF_CTL3,
1097 { AR5K_PHY_RF_CTL3,
1104 { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
1098 { 0x0a020001, 0x05020100, 0x0a020001 } },
1105 { AR5K_PHY_RF_CTL4,
1099 { AR5K_PHY_RF_CTL4,
1106 { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
1100 { 0x00000e0e, 0x00000e0e, 0x00000e0e } },
1107 { AR5K_PHY_PA_CTL,
1101 { AR5K_PHY_PA_CTL,
1108 { 0x00000003, 0x00000003, 0x0000000b, 0x0000000b, 0x0000000b } },
1102 { 0x00000003, 0x0000000b, 0x0000000b } },
1109 { AR5K_PHY_SETTLING,
1103 { AR5K_PHY_SETTLING,
1110 { 0x1372161c, 0x13721c25, 0x13721722, 0x13721422, 0x13721c25 } },
1104 { 0x1372161c, 0x13721722, 0x13721422 } },
1111 { AR5K_PHY_GAIN,
1105 { AR5K_PHY_GAIN,
1112 { 0x0018fa61, 0x0018fa61, 0x00199a65, 0x00199a65, 0x00199a65 } },
1106 { 0x0018fa61, 0x00199a65, 0x00199a65 } },
1113 { AR5K_PHY_DESIRED_SIZE,
1107 { AR5K_PHY_DESIRED_SIZE,
1114 { 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da, 0x0c98b0da } },
1108 { 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da } },
1115 { AR5K_PHY_SIG,
1109 { AR5K_PHY_SIG,
1116 { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },
1110 { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },
1117 { AR5K_PHY_AGCCOARSE,
1111 { AR5K_PHY_AGCCOARSE,
1118 { 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e } },
1112 { 0x3139605e, 0x3139605e, 0x3139605e } },
1119 { AR5K_PHY_WEAK_OFDM_LOW_THR,
1113 { AR5K_PHY_WEAK_OFDM_LOW_THR,
1120 { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
1114 { 0x050cb081, 0x050cb081, 0x050cb081 } },
1121 { AR5K_PHY_RX_DELAY,
1115 { AR5K_PHY_RX_DELAY,
1122 { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
1116 { 0x000007d0, 0x0000044c, 0x00000898 } },
1123 { AR5K_PHY_FRAME_CTL_5211,
1117 { AR5K_PHY_FRAME_CTL_5211,
1124 { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
1118 { 0xf7b81000, 0xf7b80d00, 0xf7b81000 } },
1125 { AR5K_PHY_CCKTXCTL,
1119 { AR5K_PHY_CCKTXCTL,
1126 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1120 { 0x00000000, 0x00000000, 0x00000000 } },
1127 { AR5K_PHY_CCK_CROSSCORR,
1121 { AR5K_PHY_CCK_CROSSCORR,
1128 { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
1122 { 0xd6be6788, 0xd03e6788, 0xd03e6788 } },
1129 { AR5K_PHY_GAIN_2GHZ,
1123 { AR5K_PHY_GAIN_2GHZ,
1130 { 0x00000140, 0x00000140, 0x0052c140, 0x0052c140, 0x0052c140 } },
1124 { 0x00000140, 0x0052c140, 0x0052c140 } },
1131 { AR5K_PHY_CCK_RX_CTL_4,
1125 { AR5K_PHY_CCK_RX_CTL_4,
1132 { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
1126 { 0x1883800a, 0x1863800a, 0x1883800a } },
1133 { 0xa324,
1127 { 0xa324,
1134 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
1128 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
1135 { 0xa328,
1129 { 0xa328,
1136 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
1130 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
1137 { 0xa32c,
1131 { 0xa32c,
1138 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
1132 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
1139 { 0xa330,
1133 { 0xa330,
1140 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
1134 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
1141 { 0xa334,
1135 { 0xa334,
1142 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
1136 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
1143};
1144
1145static const struct ath5k_ini rf2425_ini_common_end[] = {
1146 { AR5K_DCU_FP, 0x000003e0 },
1147 { AR5K_SEQ_MASK, 0x0000000f },
1148 { 0x809c, 0x00000000 },
1149 { 0x80a0, 0x00000000 },
1150 { AR5K_MIC_QOS_CTL, 0x00000000 },

--- 212 unchanged lines hidden (view full) ---

1363 { AR5K_BB_GAIN(63), 0x0000001a },
1364};
1365
1366
1367/*
1368 * Write initial register dump
1369 */
1370static void ath5k_hw_ini_registers(struct ath5k_hw *ah, unsigned int size,
1137};
1138
1139static const struct ath5k_ini rf2425_ini_common_end[] = {
1140 { AR5K_DCU_FP, 0x000003e0 },
1141 { AR5K_SEQ_MASK, 0x0000000f },
1142 { 0x809c, 0x00000000 },
1143 { 0x80a0, 0x00000000 },
1144 { AR5K_MIC_QOS_CTL, 0x00000000 },

--- 212 unchanged lines hidden (view full) ---

1357 { AR5K_BB_GAIN(63), 0x0000001a },
1358};
1359
1360
1361/*
1362 * Write initial register dump
1363 */
1364static void ath5k_hw_ini_registers(struct ath5k_hw *ah, unsigned int size,
1371 const struct ath5k_ini *ini_regs, bool change_channel)
1365 const struct ath5k_ini *ini_regs, bool skip_pcu)
1372{
1373 unsigned int i;
1374
1375 /* Write initial registers */
1376 for (i = 0; i < size; i++) {
1366{
1367 unsigned int i;
1368
1369 /* Write initial registers */
1370 for (i = 0; i < size; i++) {
1377 /* On channel change there is
1378 * no need to mess with PCU */
1379 if (change_channel &&
1371 /* Skip PCU registers if
1372 * requested */
1373 if (skip_pcu &&
1380 ini_regs[i].ini_register >= AR5K_PCU_MIN &&
1381 ini_regs[i].ini_register <= AR5K_PCU_MAX)
1382 continue;
1383
1384 switch (ini_regs[i].ini_mode) {
1385 case AR5K_INI_READ:
1386 /* Cleared on read */
1387 ath5k_hw_reg_read(ah, ini_regs[i].ini_register);

--- 16 unchanged lines hidden (view full) ---

1404 for (i = 0; i < size; i++) {
1405 AR5K_REG_WAIT(i);
1406 ath5k_hw_reg_write(ah, ini_mode[i].mode_value[mode],
1407 (u32)ini_mode[i].mode_register);
1408 }
1409
1410}
1411
1374 ini_regs[i].ini_register >= AR5K_PCU_MIN &&
1375 ini_regs[i].ini_register <= AR5K_PCU_MAX)
1376 continue;
1377
1378 switch (ini_regs[i].ini_mode) {
1379 case AR5K_INI_READ:
1380 /* Cleared on read */
1381 ath5k_hw_reg_read(ah, ini_regs[i].ini_register);

--- 16 unchanged lines hidden (view full) ---

1398 for (i = 0; i < size; i++) {
1399 AR5K_REG_WAIT(i);
1400 ath5k_hw_reg_write(ah, ini_mode[i].mode_value[mode],
1401 (u32)ini_mode[i].mode_register);
1402 }
1403
1404}
1405
1412int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel)
1406int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool skip_pcu)
1413{
1414 /*
1415 * Write initial register settings
1416 */
1417
1418 /* For AR5212 and combatible */
1419 if (ah->ah_version == AR5K_AR5212) {
1420
1421 /* First set of mode-specific settings */
1422 ath5k_hw_ini_mode_registers(ah,
1423 ARRAY_SIZE(ar5212_ini_mode_start),
1424 ar5212_ini_mode_start, mode);
1425
1426 /*
1427 * Write initial settings common for all modes
1428 */
1429 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5212_ini_common_start),
1407{
1408 /*
1409 * Write initial register settings
1410 */
1411
1412 /* For AR5212 and combatible */
1413 if (ah->ah_version == AR5K_AR5212) {
1414
1415 /* First set of mode-specific settings */
1416 ath5k_hw_ini_mode_registers(ah,
1417 ARRAY_SIZE(ar5212_ini_mode_start),
1418 ar5212_ini_mode_start, mode);
1419
1420 /*
1421 * Write initial settings common for all modes
1422 */
1423 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5212_ini_common_start),
1430 ar5212_ini_common_start, change_channel);
1424 ar5212_ini_common_start, skip_pcu);
1431
1432 /* Second set of mode-specific settings */
1433 switch (ah->ah_radio) {
1434 case AR5K_RF5111:
1435
1436 ath5k_hw_ini_mode_registers(ah,
1437 ARRAY_SIZE(rf5111_ini_mode_end),
1438 rf5111_ini_mode_end, mode);
1439
1440 ath5k_hw_ini_registers(ah,
1441 ARRAY_SIZE(rf5111_ini_common_end),
1425
1426 /* Second set of mode-specific settings */
1427 switch (ah->ah_radio) {
1428 case AR5K_RF5111:
1429
1430 ath5k_hw_ini_mode_registers(ah,
1431 ARRAY_SIZE(rf5111_ini_mode_end),
1432 rf5111_ini_mode_end, mode);
1433
1434 ath5k_hw_ini_registers(ah,
1435 ARRAY_SIZE(rf5111_ini_common_end),
1442 rf5111_ini_common_end, change_channel);
1436 rf5111_ini_common_end, skip_pcu);
1443
1444 /* Baseband gain table */
1445 ath5k_hw_ini_registers(ah,
1446 ARRAY_SIZE(rf5111_ini_bbgain),
1437
1438 /* Baseband gain table */
1439 ath5k_hw_ini_registers(ah,
1440 ARRAY_SIZE(rf5111_ini_bbgain),
1447 rf5111_ini_bbgain, change_channel);
1441 rf5111_ini_bbgain, skip_pcu);
1448
1449 break;
1450 case AR5K_RF5112:
1451
1452 ath5k_hw_ini_mode_registers(ah,
1453 ARRAY_SIZE(rf5112_ini_mode_end),
1454 rf5112_ini_mode_end, mode);
1455
1456 ath5k_hw_ini_registers(ah,
1457 ARRAY_SIZE(rf5112_ini_common_end),
1442
1443 break;
1444 case AR5K_RF5112:
1445
1446 ath5k_hw_ini_mode_registers(ah,
1447 ARRAY_SIZE(rf5112_ini_mode_end),
1448 rf5112_ini_mode_end, mode);
1449
1450 ath5k_hw_ini_registers(ah,
1451 ARRAY_SIZE(rf5112_ini_common_end),
1458 rf5112_ini_common_end, change_channel);
1452 rf5112_ini_common_end, skip_pcu);
1459
1460 ath5k_hw_ini_registers(ah,
1461 ARRAY_SIZE(rf5112_ini_bbgain),
1453
1454 ath5k_hw_ini_registers(ah,
1455 ARRAY_SIZE(rf5112_ini_bbgain),
1462 rf5112_ini_bbgain, change_channel);
1456 rf5112_ini_bbgain, skip_pcu);
1463
1464 break;
1465 case AR5K_RF5413:
1466
1467 ath5k_hw_ini_mode_registers(ah,
1468 ARRAY_SIZE(rf5413_ini_mode_end),
1469 rf5413_ini_mode_end, mode);
1470
1471 ath5k_hw_ini_registers(ah,
1472 ARRAY_SIZE(rf5413_ini_common_end),
1457
1458 break;
1459 case AR5K_RF5413:
1460
1461 ath5k_hw_ini_mode_registers(ah,
1462 ARRAY_SIZE(rf5413_ini_mode_end),
1463 rf5413_ini_mode_end, mode);
1464
1465 ath5k_hw_ini_registers(ah,
1466 ARRAY_SIZE(rf5413_ini_common_end),
1473 rf5413_ini_common_end, change_channel);
1467 rf5413_ini_common_end, skip_pcu);
1474
1475 ath5k_hw_ini_registers(ah,
1476 ARRAY_SIZE(rf5112_ini_bbgain),
1468
1469 ath5k_hw_ini_registers(ah,
1470 ARRAY_SIZE(rf5112_ini_bbgain),
1477 rf5112_ini_bbgain, change_channel);
1471 rf5112_ini_bbgain, skip_pcu);
1478
1479 break;
1480 case AR5K_RF2316:
1481 case AR5K_RF2413:
1482
1483 ath5k_hw_ini_mode_registers(ah,
1484 ARRAY_SIZE(rf2413_ini_mode_end),
1485 rf2413_ini_mode_end, mode);
1486
1487 ath5k_hw_ini_registers(ah,
1488 ARRAY_SIZE(rf2413_ini_common_end),
1472
1473 break;
1474 case AR5K_RF2316:
1475 case AR5K_RF2413:
1476
1477 ath5k_hw_ini_mode_registers(ah,
1478 ARRAY_SIZE(rf2413_ini_mode_end),
1479 rf2413_ini_mode_end, mode);
1480
1481 ath5k_hw_ini_registers(ah,
1482 ARRAY_SIZE(rf2413_ini_common_end),
1489 rf2413_ini_common_end, change_channel);
1483 rf2413_ini_common_end, skip_pcu);
1490
1491 /* Override settings from rf2413_ini_common_end */
1492 if (ah->ah_radio == AR5K_RF2316) {
1493 ath5k_hw_reg_write(ah, 0x00004000,
1494 AR5K_PHY_AGC);
1495 ath5k_hw_reg_write(ah, 0x081b7caa,
1496 0xa274);
1497 }
1498
1499 ath5k_hw_ini_registers(ah,
1500 ARRAY_SIZE(rf5112_ini_bbgain),
1484
1485 /* Override settings from rf2413_ini_common_end */
1486 if (ah->ah_radio == AR5K_RF2316) {
1487 ath5k_hw_reg_write(ah, 0x00004000,
1488 AR5K_PHY_AGC);
1489 ath5k_hw_reg_write(ah, 0x081b7caa,
1490 0xa274);
1491 }
1492
1493 ath5k_hw_ini_registers(ah,
1494 ARRAY_SIZE(rf5112_ini_bbgain),
1501 rf5112_ini_bbgain, change_channel);
1495 rf5112_ini_bbgain, skip_pcu);
1502 break;
1503 case AR5K_RF2317:
1504 case AR5K_RF2425:
1505
1506 ath5k_hw_ini_mode_registers(ah,
1507 ARRAY_SIZE(rf2425_ini_mode_end),
1508 rf2425_ini_mode_end, mode);
1509
1510 ath5k_hw_ini_registers(ah,
1511 ARRAY_SIZE(rf2425_ini_common_end),
1496 break;
1497 case AR5K_RF2317:
1498 case AR5K_RF2425:
1499
1500 ath5k_hw_ini_mode_registers(ah,
1501 ARRAY_SIZE(rf2425_ini_mode_end),
1502 rf2425_ini_mode_end, mode);
1503
1504 ath5k_hw_ini_registers(ah,
1505 ARRAY_SIZE(rf2425_ini_common_end),
1512 rf2425_ini_common_end, change_channel);
1506 rf2425_ini_common_end, skip_pcu);
1513
1514 ath5k_hw_ini_registers(ah,
1515 ARRAY_SIZE(rf5112_ini_bbgain),
1507
1508 ath5k_hw_ini_registers(ah,
1509 ARRAY_SIZE(rf5112_ini_bbgain),
1516 rf5112_ini_bbgain, change_channel);
1510 rf5112_ini_bbgain, skip_pcu);
1517 break;
1518 default:
1519 return -EINVAL;
1520
1521 }
1522
1523 /* For AR5211 */
1524 } else if (ah->ah_version == AR5K_AR5211) {

--- 8 unchanged lines hidden (view full) ---

1533 /* Mode-specific settings */
1534 ath5k_hw_ini_mode_registers(ah, ARRAY_SIZE(ar5211_ini_mode),
1535 ar5211_ini_mode, mode);
1536
1537 /*
1538 * Write initial settings common for all modes
1539 */
1540 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5211_ini),
1511 break;
1512 default:
1513 return -EINVAL;
1514
1515 }
1516
1517 /* For AR5211 */
1518 } else if (ah->ah_version == AR5K_AR5211) {

--- 8 unchanged lines hidden (view full) ---

1527 /* Mode-specific settings */
1528 ath5k_hw_ini_mode_registers(ah, ARRAY_SIZE(ar5211_ini_mode),
1529 ar5211_ini_mode, mode);
1530
1531 /*
1532 * Write initial settings common for all modes
1533 */
1534 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5211_ini),
1541 ar5211_ini, change_channel);
1535 ar5211_ini, skip_pcu);
1542
1543 /* AR5211 only comes with 5111 */
1544
1545 /* Baseband gain table */
1546 ath5k_hw_ini_registers(ah, ARRAY_SIZE(rf5111_ini_bbgain),
1536
1537 /* AR5211 only comes with 5111 */
1538
1539 /* Baseband gain table */
1540 ath5k_hw_ini_registers(ah, ARRAY_SIZE(rf5111_ini_bbgain),
1547 rf5111_ini_bbgain, change_channel);
1541 rf5111_ini_bbgain, skip_pcu);
1548 /* For AR5210 (for mode settings check out ath5k_hw_reset_tx_queue) */
1549 } else if (ah->ah_version == AR5K_AR5210) {
1550 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5210_ini),
1542 /* For AR5210 (for mode settings check out ath5k_hw_reset_tx_queue) */
1543 } else if (ah->ah_version == AR5K_AR5210) {
1544 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5210_ini),
1551 ar5210_ini, change_channel);
1545 ar5210_ini, skip_pcu);
1552 }
1553
1554 return 0;
1555}
1546 }
1547
1548 return 0;
1549}