dma.c (34ce644aa8342f95eb1e187178f83febade4af37) dma.c (c47faa364cfb249d5d7670fb7293a6f9acd8aa9e)
1/*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *

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15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 */
18
19/*************************************\
20* DMA and interrupt masking functions *
21\*************************************/
22
1/*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *

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15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 */
18
19/*************************************\
20* DMA and interrupt masking functions *
21\*************************************/
22
23/*
24 * dma.c - DMA and interrupt masking functions
23/**
24 * DOC: DMA and interrupt masking functions
25 *
26 * Here we setup descriptor pointers (rxdp/txdp) start/stop dma engine and
27 * handle queue setup for 5210 chipset (rest are handled on qcu.c).
28 * Also we setup interrupt mask register (IMR) and read the various interrupt
29 * status registers (ISR).
25 *
26 * Here we setup descriptor pointers (rxdp/txdp) start/stop dma engine and
27 * handle queue setup for 5210 chipset (rest are handled on qcu.c).
28 * Also we setup interrupt mask register (IMR) and read the various interrupt
29 * status registers (ISR).
30 *
31 * TODO: Handle SISR on 5211+ and introduce a function to return the queue
32 * number that resulted the interrupt.
33 */
34
35#include "ath5k.h"
36#include "reg.h"
37#include "debug.h"
38
39
40/*********\
41* Receive *
42\*********/
43
44/**
30 */
31
32#include "ath5k.h"
33#include "reg.h"
34#include "debug.h"
35
36
37/*********\
38* Receive *
39\*********/
40
41/**
45 * ath5k_hw_start_rx_dma - Start DMA receive
46 *
42 * ath5k_hw_start_rx_dma() - Start DMA receive
47 * @ah: The &struct ath5k_hw
48 */
43 * @ah: The &struct ath5k_hw
44 */
49void ath5k_hw_start_rx_dma(struct ath5k_hw *ah)
45void
46ath5k_hw_start_rx_dma(struct ath5k_hw *ah)
50{
51 ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR);
52 ath5k_hw_reg_read(ah, AR5K_CR);
53}
54
55/**
47{
48 ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR);
49 ath5k_hw_reg_read(ah, AR5K_CR);
50}
51
52/**
56 * ath5k_hw_stop_rx_dma - Stop DMA receive
57 *
53 * ath5k_hw_stop_rx_dma() - Stop DMA receive
58 * @ah: The &struct ath5k_hw
59 */
54 * @ah: The &struct ath5k_hw
55 */
60static int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
56static int
57ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
61{
62 unsigned int i;
63
64 ath5k_hw_reg_write(ah, AR5K_CR_RXD, AR5K_CR);
65
66 /*
67 * It may take some time to disable the DMA receive unit
68 */

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74 if (!i)
75 ATH5K_DBG(ah, ATH5K_DEBUG_DMA,
76 "failed to stop RX DMA !\n");
77
78 return i ? 0 : -EBUSY;
79}
80
81/**
58{
59 unsigned int i;
60
61 ath5k_hw_reg_write(ah, AR5K_CR_RXD, AR5K_CR);
62
63 /*
64 * It may take some time to disable the DMA receive unit
65 */

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71 if (!i)
72 ATH5K_DBG(ah, ATH5K_DEBUG_DMA,
73 "failed to stop RX DMA !\n");
74
75 return i ? 0 : -EBUSY;
76}
77
78/**
82 * ath5k_hw_get_rxdp - Get RX Descriptor's address
83 *
79 * ath5k_hw_get_rxdp() - Get RX Descriptor's address
84 * @ah: The &struct ath5k_hw
85 */
80 * @ah: The &struct ath5k_hw
81 */
86u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah)
82u32
83ath5k_hw_get_rxdp(struct ath5k_hw *ah)
87{
88 return ath5k_hw_reg_read(ah, AR5K_RXDP);
89}
90
91/**
84{
85 return ath5k_hw_reg_read(ah, AR5K_RXDP);
86}
87
88/**
92 * ath5k_hw_set_rxdp - Set RX Descriptor's address
93 *
89 * ath5k_hw_set_rxdp() - Set RX Descriptor's address
94 * @ah: The &struct ath5k_hw
95 * @phys_addr: RX descriptor address
96 *
97 * Returns -EIO if rx is active
98 */
90 * @ah: The &struct ath5k_hw
91 * @phys_addr: RX descriptor address
92 *
93 * Returns -EIO if rx is active
94 */
99int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr)
95int
96ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr)
100{
101 if (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) {
102 ATH5K_DBG(ah, ATH5K_DEBUG_DMA,
103 "tried to set RXDP while rx was active !\n");
104 return -EIO;
105 }
106
107 ath5k_hw_reg_write(ah, phys_addr, AR5K_RXDP);
108 return 0;
109}
110
111
112/**********\
113* Transmit *
114\**********/
115
116/**
97{
98 if (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) {
99 ATH5K_DBG(ah, ATH5K_DEBUG_DMA,
100 "tried to set RXDP while rx was active !\n");
101 return -EIO;
102 }
103
104 ath5k_hw_reg_write(ah, phys_addr, AR5K_RXDP);
105 return 0;
106}
107
108
109/**********\
110* Transmit *
111\**********/
112
113/**
117 * ath5k_hw_start_tx_dma - Start DMA transmit for a specific queue
118 *
114 * ath5k_hw_start_tx_dma() - Start DMA transmit for a specific queue
119 * @ah: The &struct ath5k_hw
120 * @queue: The hw queue number
121 *
122 * Start DMA transmit for a specific queue and since 5210 doesn't have
123 * QCU/DCU, set up queue parameters for 5210 here based on queue type (one
124 * queue for normal data and one queue for beacons). For queue setup
125 * on newer chips check out qcu.c. Returns -EINVAL if queue number is out
126 * of range or if queue is already disabled.
127 *
128 * NOTE: Must be called after setting up tx control descriptor for that
129 * queue (see below).
130 */
115 * @ah: The &struct ath5k_hw
116 * @queue: The hw queue number
117 *
118 * Start DMA transmit for a specific queue and since 5210 doesn't have
119 * QCU/DCU, set up queue parameters for 5210 here based on queue type (one
120 * queue for normal data and one queue for beacons). For queue setup
121 * on newer chips check out qcu.c. Returns -EINVAL if queue number is out
122 * of range or if queue is already disabled.
123 *
124 * NOTE: Must be called after setting up tx control descriptor for that
125 * queue (see below).
126 */
131int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue)
127int
128ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue)
132{
133 u32 tx_queue;
134
135 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
136
137 /* Return if queue is declared inactive */
138 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
139 return -EINVAL;

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172 /* Start queue */
173 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXE, queue);
174 }
175
176 return 0;
177}
178
179/**
129{
130 u32 tx_queue;
131
132 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
133
134 /* Return if queue is declared inactive */
135 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
136 return -EINVAL;

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169 /* Start queue */
170 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXE, queue);
171 }
172
173 return 0;
174}
175
176/**
180 * ath5k_hw_stop_tx_dma - Stop DMA transmit on a specific queue
181 *
177 * ath5k_hw_stop_tx_dma() - Stop DMA transmit on a specific queue
182 * @ah: The &struct ath5k_hw
183 * @queue: The hw queue number
184 *
185 * Stop DMA transmit on a specific hw queue and drain queue so we don't
186 * have any pending frames. Returns -EBUSY if we still have pending frames,
187 * -EINVAL if queue number is out of range or inactive.
178 * @ah: The &struct ath5k_hw
179 * @queue: The hw queue number
180 *
181 * Stop DMA transmit on a specific hw queue and drain queue so we don't
182 * have any pending frames. Returns -EBUSY if we still have pending frames,
183 * -EINVAL if queue number is out of range or inactive.
188 *
189 */
184 */
190static int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
185static int
186ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
191{
192 unsigned int i = 40;
193 u32 tx_queue, pending;
194
195 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
196
197 /* Return if queue is declared inactive */
198 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)

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315 }
316 }
317
318 /* TODO: Check for success on 5210 else return error */
319 return 0;
320}
321
322/**
187{
188 unsigned int i = 40;
189 u32 tx_queue, pending;
190
191 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
192
193 /* Return if queue is declared inactive */
194 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)

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311 }
312 }
313
314 /* TODO: Check for success on 5210 else return error */
315 return 0;
316}
317
318/**
323 * ath5k_hw_stop_beacon_queue - Stop beacon queue
319 * ath5k_hw_stop_beacon_queue() - Stop beacon queue
320 * @ah: The &struct ath5k_hw
321 * @queue: The queue number
324 *
322 *
325 * @ah The &struct ath5k_hw
326 * @queue The queue number
327 *
328 * Returns -EIO if queue didn't stop
329 */
323 * Returns -EIO if queue didn't stop
324 */
330int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue)
325int
326ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue)
331{
332 int ret;
333 ret = ath5k_hw_stop_tx_dma(ah, queue);
334 if (ret) {
335 ATH5K_DBG(ah, ATH5K_DEBUG_DMA,
336 "beacon queue didn't stop !\n");
337 return -EIO;
338 }
339 return 0;
340}
341
342/**
327{
328 int ret;
329 ret = ath5k_hw_stop_tx_dma(ah, queue);
330 if (ret) {
331 ATH5K_DBG(ah, ATH5K_DEBUG_DMA,
332 "beacon queue didn't stop !\n");
333 return -EIO;
334 }
335 return 0;
336}
337
338/**
343 * ath5k_hw_get_txdp - Get TX Descriptor's address for a specific queue
344 *
339 * ath5k_hw_get_txdp() - Get TX Descriptor's address for a specific queue
345 * @ah: The &struct ath5k_hw
346 * @queue: The hw queue number
347 *
348 * Get TX descriptor's address for a specific queue. For 5210 we ignore
349 * the queue number and use tx queue type since we only have 2 queues.
350 * We use TXDP0 for normal data queue and TXDP1 for beacon queue.
351 * For newer chips with QCU/DCU we just read the corresponding TXDP register.
352 *
353 * XXX: Is TXDP read and clear ?
354 */
340 * @ah: The &struct ath5k_hw
341 * @queue: The hw queue number
342 *
343 * Get TX descriptor's address for a specific queue. For 5210 we ignore
344 * the queue number and use tx queue type since we only have 2 queues.
345 * We use TXDP0 for normal data queue and TXDP1 for beacon queue.
346 * For newer chips with QCU/DCU we just read the corresponding TXDP register.
347 *
348 * XXX: Is TXDP read and clear ?
349 */
355u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue)
350u32
351ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue)
356{
357 u16 tx_reg;
358
359 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
360
361 /*
362 * Get the transmit queue descriptor pointer from the selected queue
363 */

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377 } else {
378 tx_reg = AR5K_QUEUE_TXDP(queue);
379 }
380
381 return ath5k_hw_reg_read(ah, tx_reg);
382}
383
384/**
352{
353 u16 tx_reg;
354
355 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
356
357 /*
358 * Get the transmit queue descriptor pointer from the selected queue
359 */

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373 } else {
374 tx_reg = AR5K_QUEUE_TXDP(queue);
375 }
376
377 return ath5k_hw_reg_read(ah, tx_reg);
378}
379
380/**
385 * ath5k_hw_set_txdp - Set TX Descriptor's address for a specific queue
386 *
381 * ath5k_hw_set_txdp() - Set TX Descriptor's address for a specific queue
387 * @ah: The &struct ath5k_hw
388 * @queue: The hw queue number
382 * @ah: The &struct ath5k_hw
383 * @queue: The hw queue number
384 * @phys_addr: The physical address
389 *
390 * Set TX descriptor's address for a specific queue. For 5210 we ignore
391 * the queue number and we use tx queue type since we only have 2 queues
392 * so as above we use TXDP0 for normal data queue and TXDP1 for beacon queue.
393 * For newer chips with QCU/DCU we just set the corresponding TXDP register.
394 * Returns -EINVAL if queue type is invalid for 5210 and -EIO if queue is still
395 * active.
396 */
385 *
386 * Set TX descriptor's address for a specific queue. For 5210 we ignore
387 * the queue number and we use tx queue type since we only have 2 queues
388 * so as above we use TXDP0 for normal data queue and TXDP1 for beacon queue.
389 * For newer chips with QCU/DCU we just set the corresponding TXDP register.
390 * Returns -EINVAL if queue type is invalid for 5210 and -EIO if queue is still
391 * active.
392 */
397int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)
393int
394ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)
398{
399 u16 tx_reg;
400
401 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
402
403 /*
404 * Set the transmit queue descriptor pointer register by type
405 * on 5210

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430
431 /* Set descriptor pointer */
432 ath5k_hw_reg_write(ah, phys_addr, tx_reg);
433
434 return 0;
435}
436
437/**
395{
396 u16 tx_reg;
397
398 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
399
400 /*
401 * Set the transmit queue descriptor pointer register by type
402 * on 5210

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427
428 /* Set descriptor pointer */
429 ath5k_hw_reg_write(ah, phys_addr, tx_reg);
430
431 return 0;
432}
433
434/**
438 * ath5k_hw_update_tx_triglevel - Update tx trigger level
439 *
435 * ath5k_hw_update_tx_triglevel() - Update tx trigger level
440 * @ah: The &struct ath5k_hw
441 * @increase: Flag to force increase of trigger level
442 *
443 * This function increases/decreases the tx trigger level for the tx fifo
444 * buffer (aka FIFO threshold) that is used to indicate when PCU flushes
445 * the buffer and transmits its data. Lowering this results sending small
446 * frames more quickly but can lead to tx underruns, raising it a lot can
436 * @ah: The &struct ath5k_hw
437 * @increase: Flag to force increase of trigger level
438 *
439 * This function increases/decreases the tx trigger level for the tx fifo
440 * buffer (aka FIFO threshold) that is used to indicate when PCU flushes
441 * the buffer and transmits its data. Lowering this results sending small
442 * frames more quickly but can lead to tx underruns, raising it a lot can
447 * result other problems (i think bmiss is related). Right now we start with
448 * the lowest possible (64Bytes) and if we get tx underrun we increase it using
449 * the increase flag. Returns -EIO if we have reached maximum/minimum.
443 * result other problems. Right now we start with the lowest possible
444 * (64Bytes) and if we get tx underrun we increase it using the increase
445 * flag. Returns -EIO if we have reached maximum/minimum.
450 *
451 * XXX: Link this with tx DMA size ?
446 *
447 * XXX: Link this with tx DMA size ?
452 * XXX: Use it to save interrupts ?
448 * XXX2: Use it to save interrupts ?
453 */
449 */
454int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase)
450int
451ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase)
455{
456 u32 trigger_level, imr;
457 int ret = -EIO;
458
459 /*
460 * Disable interrupts by setting the mask
461 */
462 imr = ath5k_hw_set_imr(ah, ah->ah_imr & ~AR5K_INT_GLOBAL);

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492}
493
494
495/*******************\
496* Interrupt masking *
497\*******************/
498
499/**
452{
453 u32 trigger_level, imr;
454 int ret = -EIO;
455
456 /*
457 * Disable interrupts by setting the mask
458 */
459 imr = ath5k_hw_set_imr(ah, ah->ah_imr & ~AR5K_INT_GLOBAL);

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489}
490
491
492/*******************\
493* Interrupt masking *
494\*******************/
495
496/**
500 * ath5k_hw_is_intr_pending - Check if we have pending interrupts
501 *
497 * ath5k_hw_is_intr_pending() - Check if we have pending interrupts
502 * @ah: The &struct ath5k_hw
503 *
504 * Check if we have pending interrupts to process. Returns 1 if we
505 * have pending interrupts and 0 if we haven't.
506 */
498 * @ah: The &struct ath5k_hw
499 *
500 * Check if we have pending interrupts to process. Returns 1 if we
501 * have pending interrupts and 0 if we haven't.
502 */
507bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah)
503bool
504ath5k_hw_is_intr_pending(struct ath5k_hw *ah)
508{
509 return ath5k_hw_reg_read(ah, AR5K_INTPEND) == 1 ? 1 : 0;
510}
511
512/**
505{
506 return ath5k_hw_reg_read(ah, AR5K_INTPEND) == 1 ? 1 : 0;
507}
508
509/**
513 * ath5k_hw_get_isr - Get interrupt status
514 *
510 * ath5k_hw_get_isr() - Get interrupt status
515 * @ah: The @struct ath5k_hw
516 * @interrupt_mask: Driver's interrupt mask used to filter out
517 * interrupts in sw.
518 *
519 * This function is used inside our interrupt handler to determine the reason
520 * for the interrupt by reading Primary Interrupt Status Register. Returns an
521 * abstract interrupt status mask which is mostly ISR with some uncommon bits
522 * being mapped on some standard non hw-specific positions
523 * (check out &ath5k_int).
524 *
525 * NOTE: We do write-to-clear, so the active PISR/SISR bits at the time this
526 * function gets called are cleared on return.
527 */
511 * @ah: The @struct ath5k_hw
512 * @interrupt_mask: Driver's interrupt mask used to filter out
513 * interrupts in sw.
514 *
515 * This function is used inside our interrupt handler to determine the reason
516 * for the interrupt by reading Primary Interrupt Status Register. Returns an
517 * abstract interrupt status mask which is mostly ISR with some uncommon bits
518 * being mapped on some standard non hw-specific positions
519 * (check out &ath5k_int).
520 *
521 * NOTE: We do write-to-clear, so the active PISR/SISR bits at the time this
522 * function gets called are cleared on return.
523 */
528int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
524int
525ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
529{
530 u32 data = 0;
531
532 /*
533 * Read interrupt status from Primary Interrupt
534 * Register.
535 *
536 * Note: PISR/SISR Not available on 5210

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691
692 /* Below interrupts are unlikely to happen */
693
694 /* HIU = Host Interface Unit (PCI etc)
695 * Can be one of MCABT, SSERR, DPERR from SISR2 */
696 if (unlikely(pisr & (AR5K_ISR_HIUERR)))
697 *interrupt_mask |= AR5K_INT_FATAL;
698
526{
527 u32 data = 0;
528
529 /*
530 * Read interrupt status from Primary Interrupt
531 * Register.
532 *
533 * Note: PISR/SISR Not available on 5210

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688
689 /* Below interrupts are unlikely to happen */
690
691 /* HIU = Host Interface Unit (PCI etc)
692 * Can be one of MCABT, SSERR, DPERR from SISR2 */
693 if (unlikely(pisr & (AR5K_ISR_HIUERR)))
694 *interrupt_mask |= AR5K_INT_FATAL;
695
699
700 /*Beacon Not Ready*/
701 if (unlikely(pisr & (AR5K_ISR_BNR)))
702 *interrupt_mask |= AR5K_INT_BNR;
703
696 /*Beacon Not Ready*/
697 if (unlikely(pisr & (AR5K_ISR_BNR)))
698 *interrupt_mask |= AR5K_INT_BNR;
699
704 /* Doppler chirp received */
705 if (unlikely(pisr & (AR5K_ISR_RXDOPPLER)))
706 *interrupt_mask |= AR5K_INT_RX_DOPPLER;
707
708 /* A queue got CBR overrun */
709 if (unlikely(pisr & (AR5K_ISR_QCBRORN))) {
710 *interrupt_mask |= AR5K_INT_QCBRORN;
711 ah->ah_txq_isr_qcborn |= AR5K_REG_MS(sisr3,
712 AR5K_SISR3_QCBRORN);
713 }
714
715 /* A queue got CBR underrun */

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735 */
736 if (unlikely(*interrupt_mask == 0 && net_ratelimit()))
737 ATH5K_PRINTF("ISR: 0x%08x IMR: 0x%08x\n", data, ah->ah_imr);
738
739 return 0;
740}
741
742/**
700 /* A queue got CBR overrun */
701 if (unlikely(pisr & (AR5K_ISR_QCBRORN))) {
702 *interrupt_mask |= AR5K_INT_QCBRORN;
703 ah->ah_txq_isr_qcborn |= AR5K_REG_MS(sisr3,
704 AR5K_SISR3_QCBRORN);
705 }
706
707 /* A queue got CBR underrun */

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727 */
728 if (unlikely(*interrupt_mask == 0 && net_ratelimit()))
729 ATH5K_PRINTF("ISR: 0x%08x IMR: 0x%08x\n", data, ah->ah_imr);
730
731 return 0;
732}
733
734/**
743 * ath5k_hw_set_imr - Set interrupt mask
744 *
735 * ath5k_hw_set_imr() - Set interrupt mask
745 * @ah: The &struct ath5k_hw
746 * @new_mask: The new interrupt mask to be set
747 *
748 * Set the interrupt mask in hw to save interrupts. We do that by mapping
749 * ath5k_int bits to hw-specific bits to remove abstraction and writing
750 * Interrupt Mask Register.
751 */
736 * @ah: The &struct ath5k_hw
737 * @new_mask: The new interrupt mask to be set
738 *
739 * Set the interrupt mask in hw to save interrupts. We do that by mapping
740 * ath5k_int bits to hw-specific bits to remove abstraction and writing
741 * Interrupt Mask Register.
742 */
752enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask)
743enum ath5k_int
744ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask)
753{
754 enum ath5k_int old_mask, int_mask;
755
756 old_mask = ah->ah_imr;
757
758 /*
759 * Disable card interrupts to prevent any race conditions
760 * (they will be re-enabled afterwards if AR5K_INT GLOBAL

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797 simr2 |= AR5K_SISR2_BCN_TIMEOUT;
798 if (new_mask & AR5K_INT_CAB_TIMEOUT)
799 simr2 |= AR5K_SISR2_CAB_TIMEOUT;
800
801 /*Beacon Not Ready*/
802 if (new_mask & AR5K_INT_BNR)
803 int_mask |= AR5K_INT_BNR;
804
745{
746 enum ath5k_int old_mask, int_mask;
747
748 old_mask = ah->ah_imr;
749
750 /*
751 * Disable card interrupts to prevent any race conditions
752 * (they will be re-enabled afterwards if AR5K_INT GLOBAL

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789 simr2 |= AR5K_SISR2_BCN_TIMEOUT;
790 if (new_mask & AR5K_INT_CAB_TIMEOUT)
791 simr2 |= AR5K_SISR2_CAB_TIMEOUT;
792
793 /*Beacon Not Ready*/
794 if (new_mask & AR5K_INT_BNR)
795 int_mask |= AR5K_INT_BNR;
796
805 /* RX doppler chirp */
806 if (new_mask & AR5K_INT_RX_DOPPLER)
807 int_mask |= AR5K_IMR_RXDOPPLER;
808
809 /* Note: Per queue interrupt masks
810 * are set via ath5k_hw_reset_tx_queue() (qcu.c) */
811 ath5k_hw_reg_write(ah, int_mask, AR5K_PIMR);
812 ath5k_hw_reg_write(ah, simr2, AR5K_SIMR2);
813
814 } else {
815 /* Fatal interrupt abstraction for 5210 */
816 if (new_mask & AR5K_INT_FATAL)

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839}
840
841
842/********************\
843 Init/Stop functions
844\********************/
845
846/**
797 /* Note: Per queue interrupt masks
798 * are set via ath5k_hw_reset_tx_queue() (qcu.c) */
799 ath5k_hw_reg_write(ah, int_mask, AR5K_PIMR);
800 ath5k_hw_reg_write(ah, simr2, AR5K_SIMR2);
801
802 } else {
803 /* Fatal interrupt abstraction for 5210 */
804 if (new_mask & AR5K_INT_FATAL)

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827}
828
829
830/********************\
831 Init/Stop functions
832\********************/
833
834/**
847 * ath5k_hw_dma_init - Initialize DMA unit
848 *
835 * ath5k_hw_dma_init() - Initialize DMA unit
849 * @ah: The &struct ath5k_hw
850 *
851 * Set DMA size and pre-enable interrupts
852 * (driver handles tx/rx buffer setup and
853 * dma start/stop)
854 *
855 * XXX: Save/restore RXDP/TXDP registers ?
856 */
836 * @ah: The &struct ath5k_hw
837 *
838 * Set DMA size and pre-enable interrupts
839 * (driver handles tx/rx buffer setup and
840 * dma start/stop)
841 *
842 * XXX: Save/restore RXDP/TXDP registers ?
843 */
857void ath5k_hw_dma_init(struct ath5k_hw *ah)
844void
845ath5k_hw_dma_init(struct ath5k_hw *ah)
858{
859 /*
860 * Set Rx/Tx DMA Configuration
861 *
862 * Set standard DMA size (128). Note that
863 * a DMA size of 512 causes rx overruns and tx errors
864 * on pci-e cards (tested on 5424 but since rx overruns
865 * also occur on 5416/5418 with madwifi we set 128

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878
879 /* Pre-enable interrupts on 5211/5212*/
880 if (ah->ah_version != AR5K_AR5210)
881 ath5k_hw_set_imr(ah, ah->ah_imr);
882
883}
884
885/**
846{
847 /*
848 * Set Rx/Tx DMA Configuration
849 *
850 * Set standard DMA size (128). Note that
851 * a DMA size of 512 causes rx overruns and tx errors
852 * on pci-e cards (tested on 5424 but since rx overruns
853 * also occur on 5416/5418 with madwifi we set 128

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866
867 /* Pre-enable interrupts on 5211/5212*/
868 if (ah->ah_version != AR5K_AR5210)
869 ath5k_hw_set_imr(ah, ah->ah_imr);
870
871}
872
873/**
886 * ath5k_hw_dma_stop - stop DMA unit
887 *
874 * ath5k_hw_dma_stop() - stop DMA unit
888 * @ah: The &struct ath5k_hw
889 *
890 * Stop tx/rx DMA and interrupts. Returns
891 * -EBUSY if tx or rx dma failed to stop.
892 *
893 * XXX: Sometimes DMA unit hangs and we have
894 * stuck frames on tx queues, only a reset
895 * can fix that.
896 */
875 * @ah: The &struct ath5k_hw
876 *
877 * Stop tx/rx DMA and interrupts. Returns
878 * -EBUSY if tx or rx dma failed to stop.
879 *
880 * XXX: Sometimes DMA unit hangs and we have
881 * stuck frames on tx queues, only a reset
882 * can fix that.
883 */
897int ath5k_hw_dma_stop(struct ath5k_hw *ah)
884int
885ath5k_hw_dma_stop(struct ath5k_hw *ah)
898{
899 int i, qmax, err;
900 err = 0;
901
902 /* Disable interrupts */
903 ath5k_hw_set_imr(ah, 0);
904
905 /* Stop rx dma */

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887 int i, qmax, err;
888 err = 0;
889
890 /* Disable interrupts */
891 ath5k_hw_set_imr(ah, 0);
892
893 /* Stop rx dma */

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