desc.c (d4bbf7e7759afc172e2bfbc5c416324590049cdd) desc.c (c47faa364cfb249d5d7670fb7293a6f9acd8aa9e)
1/*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.

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21 Hardware Descriptor Functions
22\******************************/
23
24#include "ath5k.h"
25#include "reg.h"
26#include "debug.h"
27
28
1/*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.

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21 Hardware Descriptor Functions
22\******************************/
23
24#include "ath5k.h"
25#include "reg.h"
26#include "debug.h"
27
28
29/**
30 * DOC: Hardware descriptor functions
31 *
32 * Here we handle the processing of the low-level hw descriptors
33 * that hw reads and writes via DMA for each TX and RX attempt (that means
34 * we can also have descriptors for failed TX/RX tries). We have two kind of
35 * descriptors for RX and TX, control descriptors tell the hw how to send or
36 * receive a packet where to read/write it from/to etc and status descriptors
37 * that contain information about how the packet was sent or received (errors
38 * included).
39 *
40 * Descriptor format is not exactly the same for each MAC chip version so we
41 * have function pointers on &struct ath5k_hw we initialize at runtime based on
42 * the chip used.
43 */
44
45
29/************************\
30* TX Control descriptors *
31\************************/
32
46/************************\
47* TX Control descriptors *
48\************************/
49
33/*
34 * Initialize the 2-word tx control descriptor on 5210/5211
50/**
51 * ath5k_hw_setup_2word_tx_desc() - Initialize a 2-word tx control descriptor
52 * @ah: The &struct ath5k_hw
53 * @desc: The &struct ath5k_desc
54 * @pkt_len: Frame length in bytes
55 * @hdr_len: Header length in bytes (only used on AR5210)
56 * @padsize: Any padding we've added to the frame length
57 * @type: One of enum ath5k_pkt_type
58 * @tx_power: Tx power in 0.5dB steps
59 * @tx_rate0: HW idx for transmission rate
60 * @tx_tries0: Max number of retransmissions
61 * @key_index: Index on key table to use for encryption
62 * @antenna_mode: Which antenna to use (0 for auto)
63 * @flags: One of AR5K_TXDESC_* flags (desc.h)
64 * @rtscts_rate: HW idx for RTS/CTS transmission rate
65 * @rtscts_duration: What to put on duration field on the header of RTS/CTS
66 *
67 * Internal function to initialize a 2-Word TX control descriptor
68 * found on AR5210 and AR5211 MACs chips.
69 *
70 * Returns 0 on success or -EINVAL on false input
35 */
36static int
71 */
72static int
37ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
38 unsigned int pkt_len, unsigned int hdr_len, int padsize,
39 enum ath5k_pkt_type type,
40 unsigned int tx_power, unsigned int tx_rate0, unsigned int tx_tries0,
41 unsigned int key_index, unsigned int antenna_mode, unsigned int flags,
42 unsigned int rtscts_rate, unsigned int rtscts_duration)
73ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah,
74 struct ath5k_desc *desc,
75 unsigned int pkt_len, unsigned int hdr_len,
76 int padsize,
77 enum ath5k_pkt_type type,
78 unsigned int tx_power,
79 unsigned int tx_rate0, unsigned int tx_tries0,
80 unsigned int key_index,
81 unsigned int antenna_mode,
82 unsigned int flags,
83 unsigned int rtscts_rate, unsigned int rtscts_duration)
43{
44 u32 frame_type;
45 struct ath5k_hw_2w_tx_ctl *tx_ctl;
46 unsigned int frame_len;
47
48 tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
49
50 /*

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167 if ((ah->ah_version == AR5K_AR5210) &&
168 (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)))
169 tx_ctl->tx_control_1 |= rtscts_duration &
170 AR5K_2W_TX_DESC_CTL1_RTS_DURATION_5210;
171
172 return 0;
173}
174
84{
85 u32 frame_type;
86 struct ath5k_hw_2w_tx_ctl *tx_ctl;
87 unsigned int frame_len;
88
89 tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
90
91 /*

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208 if ((ah->ah_version == AR5K_AR5210) &&
209 (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)))
210 tx_ctl->tx_control_1 |= rtscts_duration &
211 AR5K_2W_TX_DESC_CTL1_RTS_DURATION_5210;
212
213 return 0;
214}
215
175/*
176 * Initialize the 4-word tx control descriptor on 5212
216/**
217 * ath5k_hw_setup_4word_tx_desc() - Initialize a 4-word tx control descriptor
218 * @ah: The &struct ath5k_hw
219 * @desc: The &struct ath5k_desc
220 * @pkt_len: Frame length in bytes
221 * @hdr_len: Header length in bytes (only used on AR5210)
222 * @padsize: Any padding we've added to the frame length
223 * @type: One of enum ath5k_pkt_type
224 * @tx_power: Tx power in 0.5dB steps
225 * @tx_rate0: HW idx for transmission rate
226 * @tx_tries0: Max number of retransmissions
227 * @key_index: Index on key table to use for encryption
228 * @antenna_mode: Which antenna to use (0 for auto)
229 * @flags: One of AR5K_TXDESC_* flags (desc.h)
230 * @rtscts_rate: HW idx for RTS/CTS transmission rate
231 * @rtscts_duration: What to put on duration field on the header of RTS/CTS
232 *
233 * Internal function to initialize a 4-Word TX control descriptor
234 * found on AR5212 and later MACs chips.
235 *
236 * Returns 0 on success or -EINVAL on false input
177 */
237 */
178static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
179 struct ath5k_desc *desc, unsigned int pkt_len, unsigned int hdr_len,
180 int padsize,
181 enum ath5k_pkt_type type, unsigned int tx_power, unsigned int tx_rate0,
182 unsigned int tx_tries0, unsigned int key_index,
183 unsigned int antenna_mode, unsigned int flags,
184 unsigned int rtscts_rate,
185 unsigned int rtscts_duration)
238static int
239ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
240 struct ath5k_desc *desc,
241 unsigned int pkt_len, unsigned int hdr_len,
242 int padsize,
243 enum ath5k_pkt_type type,
244 unsigned int tx_power,
245 unsigned int tx_rate0, unsigned int tx_tries0,
246 unsigned int key_index,
247 unsigned int antenna_mode,
248 unsigned int flags,
249 unsigned int rtscts_rate, unsigned int rtscts_duration)
186{
187 struct ath5k_hw_4w_tx_ctl *tx_ctl;
188 unsigned int frame_len;
189
190 /*
191 * Use local variables for these to reduce load/store access on
192 * uncached memory
193 */

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287 tx_ctl->tx_control_0 = txctl0;
288 tx_ctl->tx_control_1 = txctl1;
289 tx_ctl->tx_control_2 = txctl2;
290 tx_ctl->tx_control_3 = txctl3;
291
292 return 0;
293}
294
250{
251 struct ath5k_hw_4w_tx_ctl *tx_ctl;
252 unsigned int frame_len;
253
254 /*
255 * Use local variables for these to reduce load/store access on
256 * uncached memory
257 */

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351 tx_ctl->tx_control_0 = txctl0;
352 tx_ctl->tx_control_1 = txctl1;
353 tx_ctl->tx_control_2 = txctl2;
354 tx_ctl->tx_control_3 = txctl3;
355
356 return 0;
357}
358
295/*
296 * Initialize a 4-word multi rate retry tx control descriptor on 5212
359/**
360 * ath5k_hw_setup_mrr_tx_desc() - Initialize an MRR tx control descriptor
361 * @ah: The &struct ath5k_hw
362 * @desc: The &struct ath5k_desc
363 * @tx_rate1: HW idx for rate used on transmission series 1
364 * @tx_tries1: Max number of retransmissions for transmission series 1
365 * @tx_rate2: HW idx for rate used on transmission series 2
366 * @tx_tries2: Max number of retransmissions for transmission series 2
367 * @tx_rate3: HW idx for rate used on transmission series 3
368 * @tx_tries3: Max number of retransmissions for transmission series 3
369 *
370 * Multi rate retry (MRR) tx control descriptors are available only on AR5212
371 * MACs, they are part of the normal 4-word tx control descriptor (see above)
372 * but we handle them through a separate function for better abstraction.
373 *
374 * Returns 0 on success or -EINVAL on invalid input
297 */
298int
375 */
376int
299ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
300 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2,
301 u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3)
377ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah,
378 struct ath5k_desc *desc,
379 u_int tx_rate1, u_int tx_tries1,
380 u_int tx_rate2, u_int tx_tries2,
381 u_int tx_rate3, u_int tx_tries3)
302{
303 struct ath5k_hw_4w_tx_ctl *tx_ctl;
304
305 /* no mrr support for cards older than 5212 */
306 if (ah->ah_version < AR5K_AR5212)
307 return 0;
308
309 /*

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345 return 0;
346}
347
348
349/***********************\
350* TX Status descriptors *
351\***********************/
352
382{
383 struct ath5k_hw_4w_tx_ctl *tx_ctl;
384
385 /* no mrr support for cards older than 5212 */
386 if (ah->ah_version < AR5K_AR5212)
387 return 0;
388
389 /*

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425 return 0;
426}
427
428
429/***********************\
430* TX Status descriptors *
431\***********************/
432
353/*
354 * Process the tx status descriptor on 5210/5211
433/**
434 * ath5k_hw_proc_2word_tx_status() - Process a tx status descriptor on 5210/1
435 * @ah: The &struct ath5k_hw
436 * @desc: The &struct ath5k_desc
437 * @ts: The &struct ath5k_tx_status
355 */
438 */
356static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
357 struct ath5k_desc *desc, struct ath5k_tx_status *ts)
439static int
440ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
441 struct ath5k_desc *desc,
442 struct ath5k_tx_status *ts)
358{
359 struct ath5k_hw_2w_tx_ctl *tx_ctl;
360 struct ath5k_hw_tx_status *tx_status;
361
362 tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
363 tx_status = &desc->ud.ds_tx5210.tx_stat;
364
365 /* No frame has been send or error */

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394
395 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
396 ts->ts_status |= AR5K_TXERR_FILT;
397 }
398
399 return 0;
400}
401
443{
444 struct ath5k_hw_2w_tx_ctl *tx_ctl;
445 struct ath5k_hw_tx_status *tx_status;
446
447 tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
448 tx_status = &desc->ud.ds_tx5210.tx_stat;
449
450 /* No frame has been send or error */

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479
480 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
481 ts->ts_status |= AR5K_TXERR_FILT;
482 }
483
484 return 0;
485}
486
402/*
403 * Process a tx status descriptor on 5212
487/**
488 * ath5k_hw_proc_4word_tx_status() - Process a tx status descriptor on 5212
489 * @ah: The &struct ath5k_hw
490 * @desc: The &struct ath5k_desc
491 * @ts: The &struct ath5k_tx_status
404 */
492 */
405static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
406 struct ath5k_desc *desc, struct ath5k_tx_status *ts)
493static int
494ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
495 struct ath5k_desc *desc,
496 struct ath5k_tx_status *ts)
407{
408 struct ath5k_hw_4w_tx_ctl *tx_ctl;
409 struct ath5k_hw_tx_status *tx_status;
410 u32 txstat0, txstat1;
411
412 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
413 tx_status = &desc->ud.ds_tx5212.tx_stat;
414

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455 return 0;
456}
457
458
459/****************\
460* RX Descriptors *
461\****************/
462
497{
498 struct ath5k_hw_4w_tx_ctl *tx_ctl;
499 struct ath5k_hw_tx_status *tx_status;
500 u32 txstat0, txstat1;
501
502 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
503 tx_status = &desc->ud.ds_tx5212.tx_stat;
504

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545 return 0;
546}
547
548
549/****************\
550* RX Descriptors *
551\****************/
552
463/*
464 * Initialize an rx control descriptor
553/**
554 * ath5k_hw_setup_rx_desc() - Initialize an rx control descriptor
555 * @ah: The &struct ath5k_hw
556 * @desc: The &struct ath5k_desc
557 * @size: RX buffer length in bytes
558 * @flags: One of AR5K_RXDESC_* flags
465 */
559 */
466int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
467 u32 size, unsigned int flags)
560int
561ath5k_hw_setup_rx_desc(struct ath5k_hw *ah,
562 struct ath5k_desc *desc,
563 u32 size, unsigned int flags)
468{
469 struct ath5k_hw_rx_ctl *rx_ctl;
470
471 rx_ctl = &desc->ud.ds_rx.rx_ctl;
472
473 /*
474 * Clear the descriptor
475 * If we don't clean the status descriptor,

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486 rx_ctl->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN;
487
488 if (flags & AR5K_RXDESC_INTREQ)
489 rx_ctl->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ;
490
491 return 0;
492}
493
564{
565 struct ath5k_hw_rx_ctl *rx_ctl;
566
567 rx_ctl = &desc->ud.ds_rx.rx_ctl;
568
569 /*
570 * Clear the descriptor
571 * If we don't clean the status descriptor,

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582 rx_ctl->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN;
583
584 if (flags & AR5K_RXDESC_INTREQ)
585 rx_ctl->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ;
586
587 return 0;
588}
589
494/*
495 * Process the rx status descriptor on 5210/5211
590/**
591 * ath5k_hw_proc_5210_rx_status() - Process the rx status descriptor on 5210/1
592 * @ah: The &struct ath5k_hw
593 * @desc: The &struct ath5k_desc
594 * @rs: The &struct ath5k_rx_status
595 *
596 * Internal function used to process an RX status descriptor
597 * on AR5210/5211 MAC.
598 *
599 * Returns 0 on success or -EINPROGRESS in case we haven't received the who;e
600 * frame yet.
496 */
601 */
497static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah,
498 struct ath5k_desc *desc, struct ath5k_rx_status *rs)
602static int
603ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah,
604 struct ath5k_desc *desc,
605 struct ath5k_rx_status *rs)
499{
500 struct ath5k_hw_rx_status *rx_status;
501
502 rx_status = &desc->ud.ds_rx.rx_stat;
503
504 /* No frame received / not ready */
505 if (unlikely(!(rx_status->rx_status_1 &
506 AR5K_5210_RX_DESC_STATUS1_DONE)))

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569 if (rx_status->rx_status_1 &
570 AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
571 rs->rs_status |= AR5K_RXERR_DECRYPT;
572 }
573
574 return 0;
575}
576
606{
607 struct ath5k_hw_rx_status *rx_status;
608
609 rx_status = &desc->ud.ds_rx.rx_stat;
610
611 /* No frame received / not ready */
612 if (unlikely(!(rx_status->rx_status_1 &
613 AR5K_5210_RX_DESC_STATUS1_DONE)))

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676 if (rx_status->rx_status_1 &
677 AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
678 rs->rs_status |= AR5K_RXERR_DECRYPT;
679 }
680
681 return 0;
682}
683
577/*
578 * Process the rx status descriptor on 5212
684/**
685 * ath5k_hw_proc_5212_rx_status() - Process the rx status descriptor on 5212
686 * @ah: The &struct ath5k_hw
687 * @desc: The &struct ath5k_desc
688 * @rs: The &struct ath5k_rx_status
689 *
690 * Internal function used to process an RX status descriptor
691 * on AR5212 and later MAC.
692 *
693 * Returns 0 on success or -EINPROGRESS in case we haven't received the who;e
694 * frame yet.
579 */
695 */
580static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah,
581 struct ath5k_desc *desc,
582 struct ath5k_rx_status *rs)
696static int
697ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah,
698 struct ath5k_desc *desc,
699 struct ath5k_rx_status *rs)
583{
584 struct ath5k_hw_rx_status *rx_status;
585 u32 rxstat0, rxstat1;
586
587 rx_status = &desc->ud.ds_rx.rx_stat;
588 rxstat1 = ACCESS_ONCE(rx_status->rx_status_1);
589
590 /* No frame received / not ready */

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641 return 0;
642}
643
644
645/********\
646* Attach *
647\********/
648
700{
701 struct ath5k_hw_rx_status *rx_status;
702 u32 rxstat0, rxstat1;
703
704 rx_status = &desc->ud.ds_rx.rx_stat;
705 rxstat1 = ACCESS_ONCE(rx_status->rx_status_1);
706
707 /* No frame received / not ready */

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758 return 0;
759}
760
761
762/********\
763* Attach *
764\********/
765
649/*
650 * Init function pointers inside ath5k_hw struct
766/**
767 * ath5k_hw_init_desc_functions() - Init function pointers inside ah
768 * @ah: The &struct ath5k_hw
769 *
770 * Maps the internal descriptor functions to the function pointers on ah, used
771 * from above. This is used as an abstraction layer to handle the various chips
772 * the same way.
651 */
773 */
652int ath5k_hw_init_desc_functions(struct ath5k_hw *ah)
774int
775ath5k_hw_init_desc_functions(struct ath5k_hw *ah)
653{
654 if (ah->ah_version == AR5K_AR5212) {
655 ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc;
656 ah->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status;
657 ah->ah_proc_rx_desc = ath5k_hw_proc_5212_rx_status;
658 } else if (ah->ah_version <= AR5K_AR5211) {
659 ah->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc;
660 ah->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status;
661 ah->ah_proc_rx_desc = ath5k_hw_proc_5210_rx_status;
662 } else
663 return -ENOTSUPP;
664 return 0;
665}
776{
777 if (ah->ah_version == AR5K_AR5212) {
778 ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc;
779 ah->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status;
780 ah->ah_proc_rx_desc = ath5k_hw_proc_5212_rx_status;
781 } else if (ah->ah_version <= AR5K_AR5211) {
782 ah->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc;
783 ah->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status;
784 ah->ah_proc_rx_desc = ath5k_hw_proc_5210_rx_status;
785 } else
786 return -ENOTSUPP;
787 return 0;
788}