ath5k.h (ce169aca0d823d38465127023e3d571816e6666c) ath5k.h (c47faa364cfb249d5d7670fb7293a6f9acd8aa9e)
1/*
2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *

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256#define AR5K_SWITCH_SETTLING 5760
257#define AR5K_SWITCH_SETTLING_TURBO 7168
258
259#define AR5K_AGC_SETTLING 28
260/* 38 on 5210 but shouldn't matter */
261#define AR5K_AGC_SETTLING_TURBO 37
262
263
1/*
2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *

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256#define AR5K_SWITCH_SETTLING 5760
257#define AR5K_SWITCH_SETTLING_TURBO 7168
258
259#define AR5K_AGC_SETTLING 28
260/* 38 on 5210 but shouldn't matter */
261#define AR5K_AGC_SETTLING_TURBO 37
262
263
264/* GENERIC CHIPSET DEFINITIONS */
265
264
266/* MAC Chips */
265/*****************************\
266* GENERIC CHIPSET DEFINITIONS *
267\*****************************/
268
269/**
270 * enum ath5k_version - MAC Chips
271 * @AR5K_AR5210: AR5210 (Crete)
272 * @AR5K_AR5211: AR5211 (Oahu/Maui)
273 * @AR5K_AR5212: AR5212 (Venice) and newer
274 */
267enum ath5k_version {
268 AR5K_AR5210 = 0,
269 AR5K_AR5211 = 1,
270 AR5K_AR5212 = 2,
271};
272
275enum ath5k_version {
276 AR5K_AR5210 = 0,
277 AR5K_AR5211 = 1,
278 AR5K_AR5212 = 2,
279};
280
273/* PHY Chips */
281/**
282 * enum ath5k_radio - PHY Chips
283 * @AR5K_RF5110: RF5110 (Fez)
284 * @AR5K_RF5111: RF5111 (Sombrero)
285 * @AR5K_RF5112: RF2112/5112(A) (Derby/Derby2)
286 * @AR5K_RF2413: RF2413/2414 (Griffin/Griffin-Lite)
287 * @AR5K_RF5413: RF5413/5414/5424 (Eagle/Condor)
288 * @AR5K_RF2316: RF2315/2316 (Cobra SoC)
289 * @AR5K_RF2317: RF2317 (Spider SoC)
290 * @AR5K_RF2425: RF2425/2417 (Swan/Nalla)
291 */
274enum ath5k_radio {
275 AR5K_RF5110 = 0,
276 AR5K_RF5111 = 1,
277 AR5K_RF5112 = 2,
278 AR5K_RF2413 = 3,
279 AR5K_RF5413 = 4,
280 AR5K_RF2316 = 5,
281 AR5K_RF2317 = 6,

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297#define AR5K_SREV_AR5312_R2 0x52 /* AP31 */
298#define AR5K_SREV_AR5212_V4 0x54 /* ??? */
299#define AR5K_SREV_AR5213 0x55 /* ??? */
300#define AR5K_SREV_AR5312_R7 0x57 /* AP30 */
301#define AR5K_SREV_AR2313_R8 0x58 /* AP43 */
302#define AR5K_SREV_AR5213A 0x59 /* Hainan */
303#define AR5K_SREV_AR2413 0x78 /* Griffin lite */
304#define AR5K_SREV_AR2414 0x70 /* Griffin */
292enum ath5k_radio {
293 AR5K_RF5110 = 0,
294 AR5K_RF5111 = 1,
295 AR5K_RF5112 = 2,
296 AR5K_RF2413 = 3,
297 AR5K_RF5413 = 4,
298 AR5K_RF2316 = 5,
299 AR5K_RF2317 = 6,

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315#define AR5K_SREV_AR5312_R2 0x52 /* AP31 */
316#define AR5K_SREV_AR5212_V4 0x54 /* ??? */
317#define AR5K_SREV_AR5213 0x55 /* ??? */
318#define AR5K_SREV_AR5312_R7 0x57 /* AP30 */
319#define AR5K_SREV_AR2313_R8 0x58 /* AP43 */
320#define AR5K_SREV_AR5213A 0x59 /* Hainan */
321#define AR5K_SREV_AR2413 0x78 /* Griffin lite */
322#define AR5K_SREV_AR2414 0x70 /* Griffin */
305#define AR5K_SREV_AR2315_R6 0x86 /* AP51-Light */
306#define AR5K_SREV_AR2315_R7 0x87 /* AP51-Full */
323#define AR5K_SREV_AR2315_R6 0x86 /* AP51-Light */
324#define AR5K_SREV_AR2315_R7 0x87 /* AP51-Full */
307#define AR5K_SREV_AR5424 0x90 /* Condor */
325#define AR5K_SREV_AR5424 0x90 /* Condor */
308#define AR5K_SREV_AR2317_R1 0x90 /* AP61-Light */
309#define AR5K_SREV_AR2317_R2 0x91 /* AP61-Full */
326#define AR5K_SREV_AR2317_R1 0x90 /* AP61-Light */
327#define AR5K_SREV_AR2317_R2 0x91 /* AP61-Full */
310#define AR5K_SREV_AR5413 0xa4 /* Eagle lite */
311#define AR5K_SREV_AR5414 0xa0 /* Eagle */
312#define AR5K_SREV_AR2415 0xb0 /* Talon */
313#define AR5K_SREV_AR5416 0xc0 /* PCI-E */
314#define AR5K_SREV_AR5418 0xca /* PCI-E */
315#define AR5K_SREV_AR2425 0xe0 /* Swan */
316#define AR5K_SREV_AR2417 0xf0 /* Nala */
317

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338#define AR5K_SREV_PHY_5212A 0x42
339#define AR5K_SREV_PHY_5212B 0x43
340#define AR5K_SREV_PHY_2413 0x45
341#define AR5K_SREV_PHY_5413 0x61
342#define AR5K_SREV_PHY_2425 0x70
343
344/* TODO add support to mac80211 for vendor-specific rates and modes */
345
328#define AR5K_SREV_AR5413 0xa4 /* Eagle lite */
329#define AR5K_SREV_AR5414 0xa0 /* Eagle */
330#define AR5K_SREV_AR2415 0xb0 /* Talon */
331#define AR5K_SREV_AR5416 0xc0 /* PCI-E */
332#define AR5K_SREV_AR5418 0xca /* PCI-E */
333#define AR5K_SREV_AR2425 0xe0 /* Swan */
334#define AR5K_SREV_AR2417 0xf0 /* Nala */
335

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356#define AR5K_SREV_PHY_5212A 0x42
357#define AR5K_SREV_PHY_5212B 0x43
358#define AR5K_SREV_PHY_2413 0x45
359#define AR5K_SREV_PHY_5413 0x61
360#define AR5K_SREV_PHY_2425 0x70
361
362/* TODO add support to mac80211 for vendor-specific rates and modes */
363
346/*
364/**
365 * DOC: Atheros XR
366 *
347 * Some of this information is based on Documentation from:
348 *
349 * http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG
350 *
367 * Some of this information is based on Documentation from:
368 *
369 * http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG
370 *
351 * Modulation for Atheros' eXtended Range - range enhancing extension that is
352 * supposed to double the distance an Atheros client device can keep a
353 * connection with an Atheros access point. This is achieved by increasing
354 * the receiver sensitivity up to, -105dBm, which is about 20dB above what
355 * the 802.11 specifications demand. In addition, new (proprietary) data rates
356 * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
371 * Atheros' eXtended Range - range enhancing extension is a modulation scheme
372 * that is supposed to double the link distance between an Atheros XR-enabled
373 * client device with an Atheros XR-enabled access point. This is achieved
374 * by increasing the receiver sensitivity up to, -105dBm, which is about 20dB
375 * above what the 802.11 specifications demand. In addition, new (proprietary)
376 * data rates are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
357 *
358 * Please note that can you either use XR or TURBO but you cannot use both,
359 * they are exclusive.
360 *
377 *
378 * Please note that can you either use XR or TURBO but you cannot use both,
379 * they are exclusive.
380 *
381 * Also note that we do not plan to support XR mode at least for now. You can
382 * get a mode similar to XR by using 5MHz bwmode.
361 */
383 */
362#define MODULATION_XR 0x00000200
363/*
364 * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a
365 * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s
366 * signaling rate achieved through the bonding of two 54Mbit/s 802.11g
367 * channels. To use this feature your Access Point must also support it.
384
385
386/**
387 * DOC: Atheros SuperAG
388 *
389 * In addition to XR we have another modulation scheme called TURBO mode
390 * that is supposed to provide a throughput transmission speed up to 40Mbit/s
391 * -60Mbit/s at a 108Mbit/s signaling rate achieved through the bonding of two
392 * 54Mbit/s 802.11g channels. To use this feature both ends must support it.
368 * There is also a distinction between "static" and "dynamic" turbo modes:
369 *
370 * - Static: is the dumb version: devices set to this mode stick to it until
371 * the mode is turned off.
393 * There is also a distinction between "static" and "dynamic" turbo modes:
394 *
395 * - Static: is the dumb version: devices set to this mode stick to it until
396 * the mode is turned off.
397 *
372 * - Dynamic: is the intelligent version, the network decides itself if it
373 * is ok to use turbo. As soon as traffic is detected on adjacent channels
374 * (which would get used in turbo mode), or when a non-turbo station joins
375 * the network, turbo mode won't be used until the situation changes again.
376 * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which
377 * monitors the used radio band in order to decide whether turbo mode may
378 * be used or not.
379 *
380 * This article claims Super G sticks to bonding of channels 5 and 6 for
381 * USA:
382 *
383 * http://www.pcworld.com/article/id,113428-page,1/article.html
384 *
398 * - Dynamic: is the intelligent version, the network decides itself if it
399 * is ok to use turbo. As soon as traffic is detected on adjacent channels
400 * (which would get used in turbo mode), or when a non-turbo station joins
401 * the network, turbo mode won't be used until the situation changes again.
402 * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which
403 * monitors the used radio band in order to decide whether turbo mode may
404 * be used or not.
405 *
406 * This article claims Super G sticks to bonding of channels 5 and 6 for
407 * USA:
408 *
409 * http://www.pcworld.com/article/id,113428-page,1/article.html
410 *
385 * The channel bonding seems to be driver specific though. In addition to
386 * deciding what channels will be used, these "Turbo" modes are accomplished
387 * by also enabling the following features:
411 * The channel bonding seems to be driver specific though.
388 *
412 *
413 * In addition to TURBO modes we also have the following features for even
414 * greater speed-up:
415 *
389 * - Bursting: allows multiple frames to be sent at once, rather than pausing
390 * after each frame. Bursting is a standards-compliant feature that can be
391 * used with any Access Point.
416 * - Bursting: allows multiple frames to be sent at once, rather than pausing
417 * after each frame. Bursting is a standards-compliant feature that can be
418 * used with any Access Point.
419 *
392 * - Fast frames: increases the amount of information that can be sent per
393 * frame, also resulting in a reduction of transmission overhead. It is a
394 * proprietary feature that needs to be supported by the Access Point.
420 * - Fast frames: increases the amount of information that can be sent per
421 * frame, also resulting in a reduction of transmission overhead. It is a
422 * proprietary feature that needs to be supported by the Access Point.
423 *
395 * - Compression: data frames are compressed in real time using a Lempel Ziv
396 * algorithm. This is done transparently. Once this feature is enabled,
397 * compression and decompression takes place inside the chipset, without
398 * putting additional load on the host CPU.
399 *
424 * - Compression: data frames are compressed in real time using a Lempel Ziv
425 * algorithm. This is done transparently. Once this feature is enabled,
426 * compression and decompression takes place inside the chipset, without
427 * putting additional load on the host CPU.
428 *
429 * As with XR we also don't plan to support SuperAG features for now. You can
430 * get a mode similar to TURBO by using 40MHz bwmode.
400 */
431 */
401#define MODULATION_TURBO 0x00000080
402
432
433
434/**
435 * enum ath5k_driver_mode - PHY operation mode
436 * @AR5K_MODE_11A: 802.11a
437 * @AR5K_MODE_11B: 802.11b
438 * @AR5K_MODE_11G: 801.11g
439 * @AR5K_MODE_MAX: Used for boundary checks
440 *
441 * Do not change the order here, we use these as
442 * array indices and it also maps EEPROM structures.
443 */
403enum ath5k_driver_mode {
404 AR5K_MODE_11A = 0,
405 AR5K_MODE_11B = 1,
406 AR5K_MODE_11G = 2,
407 AR5K_MODE_MAX = 3
408};
409
444enum ath5k_driver_mode {
445 AR5K_MODE_11A = 0,
446 AR5K_MODE_11B = 1,
447 AR5K_MODE_11G = 2,
448 AR5K_MODE_MAX = 3
449};
450
451/**
452 * enum ath5k_ant_mode - Antenna operation mode
453 * @AR5K_ANTMODE_DEFAULT: Default antenna setup
454 * @AR5K_ANTMODE_FIXED_A: Only antenna A is present
455 * @AR5K_ANTMODE_FIXED_B: Only antenna B is present
456 * @AR5K_ANTMODE_SINGLE_AP: STA locked on a single ap
457 * @AR5K_ANTMODE_SECTOR_AP: AP with tx antenna set on tx desc
458 * @AR5K_ANTMODE_SECTOR_STA: STA with tx antenna set on tx desc
459 * @AR5K_ANTMODE_DEBUG: Debug mode -A -> Rx, B-> Tx-
460 * @AR5K_ANTMODE_MAX: Used for boundary checks
461 *
462 * For more infos on antenna control check out phy.c
463 */
410enum ath5k_ant_mode {
464enum ath5k_ant_mode {
411 AR5K_ANTMODE_DEFAULT = 0, /* default antenna setup */
412 AR5K_ANTMODE_FIXED_A = 1, /* only antenna A is present */
413 AR5K_ANTMODE_FIXED_B = 2, /* only antenna B is present */
414 AR5K_ANTMODE_SINGLE_AP = 3, /* sta locked on a single ap */
415 AR5K_ANTMODE_SECTOR_AP = 4, /* AP with tx antenna set on tx desc */
416 AR5K_ANTMODE_SECTOR_STA = 5, /* STA with tx antenna set on tx desc */
417 AR5K_ANTMODE_DEBUG = 6, /* Debug mode -A -> Rx, B-> Tx- */
465 AR5K_ANTMODE_DEFAULT = 0,
466 AR5K_ANTMODE_FIXED_A = 1,
467 AR5K_ANTMODE_FIXED_B = 2,
468 AR5K_ANTMODE_SINGLE_AP = 3,
469 AR5K_ANTMODE_SECTOR_AP = 4,
470 AR5K_ANTMODE_SECTOR_STA = 5,
471 AR5K_ANTMODE_DEBUG = 6,
418 AR5K_ANTMODE_MAX,
419};
420
472 AR5K_ANTMODE_MAX,
473};
474
475/**
476 * enum ath5k_bw_mode - Bandwidth operation mode
477 * @AR5K_BWMODE_DEFAULT: 20MHz, default operation
478 * @AR5K_BWMODE_5MHZ: Quarter rate
479 * @AR5K_BWMODE_10MHZ: Half rate
480 * @AR5K_BWMODE_40MHZ: Turbo
481 */
421enum ath5k_bw_mode {
482enum ath5k_bw_mode {
422 AR5K_BWMODE_DEFAULT = 0, /* 20MHz, default operation */
423 AR5K_BWMODE_5MHZ = 1, /* Quarter rate */
424 AR5K_BWMODE_10MHZ = 2, /* Half rate */
425 AR5K_BWMODE_40MHZ = 3 /* Turbo */
483 AR5K_BWMODE_DEFAULT = 0,
484 AR5K_BWMODE_5MHZ = 1,
485 AR5K_BWMODE_10MHZ = 2,
486 AR5K_BWMODE_40MHZ = 3
426};
427
487};
488
489
490
428/****************\
429 TX DEFINITIONS
430\****************/
431
491/****************\
492 TX DEFINITIONS
493\****************/
494
432/*
433 * TX Status descriptor
495/**
496 * struct ath5k_tx_status - TX Status descriptor
497 * @ts_seqnum: Sequence number
498 * @ts_tstamp: Timestamp
499 * @ts_status: Status code
500 * @ts_final_idx: Final transmission series index
501 * @ts_final_retry: Final retry count
502 * @ts_rssi: RSSI for received ACK
503 * @ts_shortretry: Short retry count
504 * @ts_virtcol: Virtual collision count
505 * @ts_antenna: Antenna used
506 *
507 * TX status descriptor gets filled by the hw
508 * on each transmission attempt.
434 */
435struct ath5k_tx_status {
436 u16 ts_seqnum;
437 u16 ts_tstamp;
438 u8 ts_status;
439 u8 ts_final_idx;
440 u8 ts_final_retry;
441 s8 ts_rssi;

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448#define AR5K_TXERR_XRETRY 0x01
449#define AR5K_TXERR_FILT 0x02
450#define AR5K_TXERR_FIFO 0x04
451
452/**
453 * enum ath5k_tx_queue - Queue types used to classify tx queues.
454 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
455 * @AR5K_TX_QUEUE_DATA: A normal data queue
509 */
510struct ath5k_tx_status {
511 u16 ts_seqnum;
512 u16 ts_tstamp;
513 u8 ts_status;
514 u8 ts_final_idx;
515 u8 ts_final_retry;
516 s8 ts_rssi;

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523#define AR5K_TXERR_XRETRY 0x01
524#define AR5K_TXERR_FILT 0x02
525#define AR5K_TXERR_FIFO 0x04
526
527/**
528 * enum ath5k_tx_queue - Queue types used to classify tx queues.
529 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
530 * @AR5K_TX_QUEUE_DATA: A normal data queue
456 * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue
457 * @AR5K_TX_QUEUE_BEACON: The beacon queue
458 * @AR5K_TX_QUEUE_CAB: The after-beacon queue
459 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
460 */
461enum ath5k_tx_queue {
462 AR5K_TX_QUEUE_INACTIVE = 0,
463 AR5K_TX_QUEUE_DATA,
531 * @AR5K_TX_QUEUE_BEACON: The beacon queue
532 * @AR5K_TX_QUEUE_CAB: The after-beacon queue
533 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
534 */
535enum ath5k_tx_queue {
536 AR5K_TX_QUEUE_INACTIVE = 0,
537 AR5K_TX_QUEUE_DATA,
464 AR5K_TX_QUEUE_XR_DATA,
465 AR5K_TX_QUEUE_BEACON,
466 AR5K_TX_QUEUE_CAB,
467 AR5K_TX_QUEUE_UAPSD,
468};
469
470#define AR5K_NUM_TX_QUEUES 10
471#define AR5K_NUM_TX_QUEUES_NOQCU 2
472
538 AR5K_TX_QUEUE_BEACON,
539 AR5K_TX_QUEUE_CAB,
540 AR5K_TX_QUEUE_UAPSD,
541};
542
543#define AR5K_NUM_TX_QUEUES 10
544#define AR5K_NUM_TX_QUEUES_NOQCU 2
545
473/*
474 * Queue syb-types to classify normal data queues.
546/**
547 * enum ath5k_tx_queue_subtype - Queue sub-types to classify normal data queues
548 * @AR5K_WME_AC_BK: Background traffic
549 * @AR5K_WME_AC_BE: Best-effort (normal) traffic
550 * @AR5K_WME_AC_VI: Video traffic
551 * @AR5K_WME_AC_VO: Voice traffic
552 *
475 * These are the 4 Access Categories as defined in
476 * WME spec. 0 is the lowest priority and 4 is the
477 * highest. Normal data that hasn't been classified
478 * goes to the Best Effort AC.
479 */
480enum ath5k_tx_queue_subtype {
553 * These are the 4 Access Categories as defined in
554 * WME spec. 0 is the lowest priority and 4 is the
555 * highest. Normal data that hasn't been classified
556 * goes to the Best Effort AC.
557 */
558enum ath5k_tx_queue_subtype {
481 AR5K_WME_AC_BK = 0, /*Background traffic*/
482 AR5K_WME_AC_BE, /*Best-effort (normal) traffic*/
483 AR5K_WME_AC_VI, /*Video traffic*/
484 AR5K_WME_AC_VO, /*Voice traffic*/
559 AR5K_WME_AC_BK = 0,
560 AR5K_WME_AC_BE,
561 AR5K_WME_AC_VI,
562 AR5K_WME_AC_VO,
485};
486
563};
564
487/*
488 * Queue ID numbers as returned by the hw functions, each number
489 * represents a hw queue. If hw does not support hw queues
565/**
566 * enum ath5k_tx_queue_id - Queue ID numbers as returned by the hw functions
567 * @AR5K_TX_QUEUE_ID_NOQCU_DATA: Data queue on AR5210 (no QCU available)
568 * @AR5K_TX_QUEUE_ID_NOQCU_BEACON: Beacon queue on AR5210 (no QCU available)
569 * @AR5K_TX_QUEUE_ID_DATA_MIN: Data queue min index
570 * @AR5K_TX_QUEUE_ID_DATA_MAX: Data queue max index
571 * @AR5K_TX_QUEUE_ID_CAB: Content after beacon queue
572 * @AR5K_TX_QUEUE_ID_BEACON: Beacon queue
573 * @AR5K_TX_QUEUE_ID_UAPSD: Urgent Automatic Power Save Delivery,
574 * @AR5K_TX_QUEUE_ID_XR_DATA: XR Data queue
575 *
576 * Each number represents a hw queue. If hw does not support hw queues
490 * (eg 5210) all data goes in one queue. These match
577 * (eg 5210) all data goes in one queue. These match
491 * d80211 definitions (net80211/MadWiFi don't use them).
578 * mac80211 definitions.
492 */
493enum ath5k_tx_queue_id {
494 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0,
495 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1,
579 */
580enum ath5k_tx_queue_id {
581 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0,
582 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1,
496 AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/
497 AR5K_TX_QUEUE_ID_DATA_MAX = 3, /*IEEE80211_TX_QUEUE_DATA3*/
498 AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/
499 AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/
500 AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/
583 AR5K_TX_QUEUE_ID_DATA_MIN = 0,
584 AR5K_TX_QUEUE_ID_DATA_MAX = 3,
585 AR5K_TX_QUEUE_ID_CAB = 6,
586 AR5K_TX_QUEUE_ID_BEACON = 7,
501 AR5K_TX_QUEUE_ID_UAPSD = 8,
587 AR5K_TX_QUEUE_ID_UAPSD = 8,
502 AR5K_TX_QUEUE_ID_XR_DATA = 9,
503};
504
505/*
506 * Flags to set hw queue's parameters...
507 */
508#define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */
509#define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */
510#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */

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515#define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */
516#define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */
517#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */
518#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/
519#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */
520#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */
521#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/
522
588};
589
590/*
591 * Flags to set hw queue's parameters...
592 */
593#define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */
594#define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */
595#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */

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600#define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */
601#define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */
602#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */
603#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/
604#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */
605#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */
606#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/
607
523/*
524 * Data transmit queue state. One of these exists for each
525 * hardware transmit queue. Packets sent to us from above
526 * are assigned to queues based on their priority. Not all
527 * devices support a complete set of hardware transmit queues.
528 * For those devices the array sc_ac2q will map multiple
529 * priorities to fewer hardware queues (typically all to one
530 * hardware queue).
608/**
609 * struct ath5k_txq - Transmit queue state
610 * @qnum: Hardware q number
611 * @link: Link ptr in last TX desc
612 * @q: Transmit queue (&struct list_head)
613 * @lock: Lock on q and link
614 * @setup: Is the queue configured
615 * @txq_len:Number of queued buffers
616 * @txq_max: Max allowed num of queued buffers
617 * @txq_poll_mark: Used to check if queue got stuck
618 * @txq_stuck: Queue stuck counter
619 *
620 * One of these exists for each hardware transmit queue.
621 * Packets sent to us from above are assigned to queues based
622 * on their priority. Not all devices support a complete set
623 * of hardware transmit queues. For those devices the array
624 * sc_ac2q will map multiple priorities to fewer hardware queues
625 * (typically all to one hardware queue).
531 */
532struct ath5k_txq {
626 */
627struct ath5k_txq {
533 unsigned int qnum; /* hardware q number */
534 u32 *link; /* link ptr in last TX desc */
535 struct list_head q; /* transmit queue */
536 spinlock_t lock; /* lock on q and link */
628 unsigned int qnum;
629 u32 *link;
630 struct list_head q;
631 spinlock_t lock;
537 bool setup;
632 bool setup;
538 int txq_len; /* number of queued buffers */
539 int txq_max; /* max allowed num of queued buffers */
633 int txq_len;
634 int txq_max;
540 bool txq_poll_mark;
635 bool txq_poll_mark;
541 unsigned int txq_stuck; /* informational counter */
636 unsigned int txq_stuck;
542};
543
637};
638
544/*
545 * A struct to hold tx queue's parameters
639/**
640 * struct ath5k_txq_info - A struct to hold TX queue's parameters
641 * @tqi_type: One of enum ath5k_tx_queue
642 * @tqi_subtype: One of enum ath5k_tx_queue_subtype
643 * @tqi_flags: TX queue flags (see above)
644 * @tqi_aifs: Arbitrated Inter-frame Space
645 * @tqi_cw_min: Minimum Contention Window
646 * @tqi_cw_max: Maximum Contention Window
647 * @tqi_cbr_period: Constant bit rate period
648 * @tqi_ready_time: Time queue waits after an event when RDYTIME is enabled
546 */
547struct ath5k_txq_info {
548 enum ath5k_tx_queue tqi_type;
549 enum ath5k_tx_queue_subtype tqi_subtype;
649 */
650struct ath5k_txq_info {
651 enum ath5k_tx_queue tqi_type;
652 enum ath5k_tx_queue_subtype tqi_subtype;
550 u16 tqi_flags; /* Tx queue flags (see above) */
551 u8 tqi_aifs; /* Arbitrated Interframe Space */
552 u16 tqi_cw_min; /* Minimum Contention Window */
553 u16 tqi_cw_max; /* Maximum Contention Window */
554 u32 tqi_cbr_period; /* Constant bit rate period */
653 u16 tqi_flags;
654 u8 tqi_aifs;
655 u16 tqi_cw_min;
656 u16 tqi_cw_max;
657 u32 tqi_cbr_period;
555 u32 tqi_cbr_overflow_limit;
556 u32 tqi_burst_time;
658 u32 tqi_cbr_overflow_limit;
659 u32 tqi_burst_time;
557 u32 tqi_ready_time; /* Time queue waits after an event */
660 u32 tqi_ready_time;
558};
559
661};
662
560/*
561 * Transmit packet types.
562 * used on tx control descriptor
663/**
664 * enum ath5k_pkt_type - Transmit packet types
665 * @AR5K_PKT_TYPE_NORMAL: Normal data
666 * @AR5K_PKT_TYPE_ATIM: ATIM
667 * @AR5K_PKT_TYPE_PSPOLL: PS-Poll
668 * @AR5K_PKT_TYPE_BEACON: Beacon
669 * @AR5K_PKT_TYPE_PROBE_RESP: Probe response
670 * @AR5K_PKT_TYPE_PIFS: PIFS
671 * Used on tx control descriptor
563 */
564enum ath5k_pkt_type {
565 AR5K_PKT_TYPE_NORMAL = 0,
566 AR5K_PKT_TYPE_ATIM = 1,
567 AR5K_PKT_TYPE_PSPOLL = 2,
568 AR5K_PKT_TYPE_BEACON = 3,
569 AR5K_PKT_TYPE_PROBE_RESP = 4,
570 AR5K_PKT_TYPE_PIFS = 5,

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577 ((0 & 1) << ((_v) + 6)) | \
578 (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \
579)
580
581#define AR5K_TXPOWER_CCK(_r, _v) ( \
582 (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \
583)
584
672 */
673enum ath5k_pkt_type {
674 AR5K_PKT_TYPE_NORMAL = 0,
675 AR5K_PKT_TYPE_ATIM = 1,
676 AR5K_PKT_TYPE_PSPOLL = 2,
677 AR5K_PKT_TYPE_BEACON = 3,
678 AR5K_PKT_TYPE_PROBE_RESP = 4,
679 AR5K_PKT_TYPE_PIFS = 5,

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686 ((0 & 1) << ((_v) + 6)) | \
687 (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \
688)
689
690#define AR5K_TXPOWER_CCK(_r, _v) ( \
691 (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \
692)
693
585/*
586 * DMA size definitions (2^(n+2))
587 */
588enum ath5k_dmasize {
589 AR5K_DMASIZE_4B = 0,
590 AR5K_DMASIZE_8B,
591 AR5K_DMASIZE_16B,
592 AR5K_DMASIZE_32B,
593 AR5K_DMASIZE_64B,
594 AR5K_DMASIZE_128B,
595 AR5K_DMASIZE_256B,
596 AR5K_DMASIZE_512B
597};
598
599
600/****************\
601 RX DEFINITIONS
602\****************/
603
694
695
696/****************\
697 RX DEFINITIONS
698\****************/
699
604/*
605 * RX Status descriptor
700/**
701 * struct ath5k_rx_status - RX Status descriptor
702 * @rs_datalen: Data length
703 * @rs_tstamp: Timestamp
704 * @rs_status: Status code
705 * @rs_phyerr: PHY error mask
706 * @rs_rssi: RSSI in 0.5dbm units
707 * @rs_keyix: Index to the key used for decrypting
708 * @rs_rate: Rate used to decode the frame
709 * @rs_antenna: Antenna used to receive the frame
710 * @rs_more: Indicates this is a frame fragment (Fast frames)
606 */
607struct ath5k_rx_status {
608 u16 rs_datalen;
609 u16 rs_tstamp;
610 u8 rs_status;
611 u8 rs_phyerr;
612 s8 rs_rssi;
613 u8 rs_keyix;

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639 *
640 * TSF is a 64bit value in usec (microseconds).
641 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
642 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
643 */
644#define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
645
646
711 */
712struct ath5k_rx_status {
713 u16 rs_datalen;
714 u16 rs_tstamp;
715 u8 rs_status;
716 u8 rs_phyerr;
717 s8 rs_rssi;
718 u8 rs_keyix;

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744 *
745 * TSF is a 64bit value in usec (microseconds).
746 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
747 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
748 */
749#define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
750
751
752
647/*******************************\
648 GAIN OPTIMIZATION DEFINITIONS
649\*******************************/
650
753/*******************************\
754 GAIN OPTIMIZATION DEFINITIONS
755\*******************************/
756
757/**
758 * enum ath5k_rfgain - RF Gain optimization engine state
759 * @AR5K_RFGAIN_INACTIVE: Engine disabled
760 * @AR5K_RFGAIN_ACTIVE: Probe active
761 * @AR5K_RFGAIN_READ_REQUESTED: Probe requested
762 * @AR5K_RFGAIN_NEED_CHANGE: Gain_F needs change
763 */
651enum ath5k_rfgain {
652 AR5K_RFGAIN_INACTIVE = 0,
653 AR5K_RFGAIN_ACTIVE,
654 AR5K_RFGAIN_READ_REQUESTED,
655 AR5K_RFGAIN_NEED_CHANGE,
656};
657
764enum ath5k_rfgain {
765 AR5K_RFGAIN_INACTIVE = 0,
766 AR5K_RFGAIN_ACTIVE,
767 AR5K_RFGAIN_READ_REQUESTED,
768 AR5K_RFGAIN_NEED_CHANGE,
769};
770
771/**
772 * struct ath5k_gain - RF Gain optimization engine state data
773 * @g_step_idx: Current step index
774 * @g_current: Current gain
775 * @g_target: Target gain
776 * @g_low: Low gain boundary
777 * @g_high: High gain boundary
778 * @g_f_corr: Gain_F correction
779 * @g_state: One of enum ath5k_rfgain
780 */
658struct ath5k_gain {
659 u8 g_step_idx;
660 u8 g_current;
661 u8 g_target;
662 u8 g_low;
663 u8 g_high;
664 u8 g_f_corr;
665 u8 g_state;
666};
667
781struct ath5k_gain {
782 u8 g_step_idx;
783 u8 g_current;
784 u8 g_target;
785 u8 g_low;
786 u8 g_high;
787 u8 g_f_corr;
788 u8 g_state;
789};
790
791
792
668/********************\
669 COMMON DEFINITIONS
670\********************/
671
672#define AR5K_SLOT_TIME_9 396
673#define AR5K_SLOT_TIME_20 880
674#define AR5K_SLOT_TIME_MAX 0xffff
675
793/********************\
794 COMMON DEFINITIONS
795\********************/
796
797#define AR5K_SLOT_TIME_9 396
798#define AR5K_SLOT_TIME_20 880
799#define AR5K_SLOT_TIME_MAX 0xffff
800
676/*
677 * The following structure is used to map 2GHz channels to
678 * 5GHz Atheros channels.
801/**
802 * struct ath5k_athchan_2ghz - 2GHz to 5GHZ map for RF5111
803 * @a2_flags: Channel flags (internal)
804 * @a2_athchan: HW channel number (internal)
805 *
806 * This structure is used to map 2GHz channels to
807 * 5GHz Atheros channels on 2111 frequency converter
808 * that comes together with RF5111
679 * TODO: Clean up
680 */
681struct ath5k_athchan_2ghz {
682 u32 a2_flags;
683 u16 a2_athchan;
684};
685
809 * TODO: Clean up
810 */
811struct ath5k_athchan_2ghz {
812 u32 a2_flags;
813 u16 a2_athchan;
814};
815
816/**
817 * enum ath5k_dmasize - DMA size definitions (2^(n+2))
818 * @AR5K_DMASIZE_4B: 4Bytes
819 * @AR5K_DMASIZE_8B: 8Bytes
820 * @AR5K_DMASIZE_16B: 16Bytes
821 * @AR5K_DMASIZE_32B: 32Bytes
822 * @AR5K_DMASIZE_64B: 64Bytes (Default)
823 * @AR5K_DMASIZE_128B: 128Bytes
824 * @AR5K_DMASIZE_256B: 256Bytes
825 * @AR5K_DMASIZE_512B: 512Bytes
826 *
827 * These are used to set DMA burst size on hw
828 *
829 * Note: Some platforms can't handle more than 4Bytes
830 * be careful on embedded boards.
831 */
832enum ath5k_dmasize {
833 AR5K_DMASIZE_4B = 0,
834 AR5K_DMASIZE_8B,
835 AR5K_DMASIZE_16B,
836 AR5K_DMASIZE_32B,
837 AR5K_DMASIZE_64B,
838 AR5K_DMASIZE_128B,
839 AR5K_DMASIZE_256B,
840 AR5K_DMASIZE_512B
841};
686
842
843
844
687/******************\
688 RATE DEFINITIONS
689\******************/
690
691/**
845/******************\
846 RATE DEFINITIONS
847\******************/
848
849/**
850 * DOC: Rate codes
851 *
692 * Seems the ar5xxx hardware supports up to 32 rates, indexed by 1-32.
693 *
694 * The rate code is used to get the RX rate or set the TX rate on the
695 * hardware descriptors. It is also used for internal modulation control
696 * and settings.
697 *
852 * Seems the ar5xxx hardware supports up to 32 rates, indexed by 1-32.
853 *
854 * The rate code is used to get the RX rate or set the TX rate on the
855 * hardware descriptors. It is also used for internal modulation control
856 * and settings.
857 *
698 * This is the hardware rate map we are aware of:
858 * This is the hardware rate map we are aware of (html unfriendly):
699 *
859 *
700 * rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08
701 * rate_kbps 3000 1000 ? ? ? 2000 500 48000
860 * Rate code Rate (Kbps)
861 * --------- -----------
862 * 0x01 3000 (XR)
863 * 0x02 1000 (XR)
864 * 0x03 250 (XR)
865 * 0x04 - 05 -Reserved-
866 * 0x06 2000 (XR)
867 * 0x07 500 (XR)
868 * 0x08 48000 (OFDM)
869 * 0x09 24000 (OFDM)
870 * 0x0A 12000 (OFDM)
871 * 0x0B 6000 (OFDM)
872 * 0x0C 54000 (OFDM)
873 * 0x0D 36000 (OFDM)
874 * 0x0E 18000 (OFDM)
875 * 0x0F 9000 (OFDM)
876 * 0x10 - 17 -Reserved-
877 * 0x18 11000L (CCK)
878 * 0x19 5500L (CCK)
879 * 0x1A 2000L (CCK)
880 * 0x1B 1000L (CCK)
881 * 0x1C 11000S (CCK)
882 * 0x1D 5500S (CCK)
883 * 0x1E 2000S (CCK)
884 * 0x1F -Reserved-
702 *
885 *
703 * rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10
704 * rate_kbps 24000 12000 6000 54000 36000 18000 9000 ?
886 * "S" indicates CCK rates with short preamble and "L" with long preamble.
705 *
887 *
706 * rate_code 17 18 19 20 21 22 23 24
707 * rate_kbps ? ? ? ? ? ? ? 11000
708 *
709 * rate_code 25 26 27 28 29 30 31 32
710 * rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ?
711 *
712 * "S" indicates CCK rates with short preamble.
713 *
714 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the
888 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the
715 * lowest 4 bits, so they are the same as below with a 0xF mask.
889 * lowest 4 bits, so they are the same as above with a 0xF mask.
716 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M).
717 * We handle this in ath5k_setup_bands().
718 */
719#define AR5K_MAX_RATES 32
720
721/* B */
722#define ATH5K_RATE_CODE_1M 0x1B
723#define ATH5K_RATE_CODE_2M 0x1A
724#define ATH5K_RATE_CODE_5_5M 0x19
725#define ATH5K_RATE_CODE_11M 0x18
726/* A and G */
727#define ATH5K_RATE_CODE_6M 0x0B
728#define ATH5K_RATE_CODE_9M 0x0F
729#define ATH5K_RATE_CODE_12M 0x0A
730#define ATH5K_RATE_CODE_18M 0x0E
731#define ATH5K_RATE_CODE_24M 0x09
732#define ATH5K_RATE_CODE_36M 0x0D
733#define ATH5K_RATE_CODE_48M 0x08
734#define ATH5K_RATE_CODE_54M 0x0C
890 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M).
891 * We handle this in ath5k_setup_bands().
892 */
893#define AR5K_MAX_RATES 32
894
895/* B */
896#define ATH5K_RATE_CODE_1M 0x1B
897#define ATH5K_RATE_CODE_2M 0x1A
898#define ATH5K_RATE_CODE_5_5M 0x19
899#define ATH5K_RATE_CODE_11M 0x18
900/* A and G */
901#define ATH5K_RATE_CODE_6M 0x0B
902#define ATH5K_RATE_CODE_9M 0x0F
903#define ATH5K_RATE_CODE_12M 0x0A
904#define ATH5K_RATE_CODE_18M 0x0E
905#define ATH5K_RATE_CODE_24M 0x09
906#define ATH5K_RATE_CODE_36M 0x0D
907#define ATH5K_RATE_CODE_48M 0x08
908#define ATH5K_RATE_CODE_54M 0x0C
735/* XR */
736#define ATH5K_RATE_CODE_XR_500K 0x07
737#define ATH5K_RATE_CODE_XR_1M 0x02
738#define ATH5K_RATE_CODE_XR_2M 0x06
739#define ATH5K_RATE_CODE_XR_3M 0x01
740
909
741/* adding this flag to rate_code enables short preamble */
910/* Adding this flag to rate_code on B rates
911 * enables short preamble */
742#define AR5K_SET_SHORT_PREAMBLE 0x04
743
744/*
745 * Crypto definitions
746 */
747
748#define AR5K_KEYCACHE_SIZE 8
749extern int ath5k_modparam_nohwcrypt;

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763} while (0)
764
765/*
766 * Hardware interrupt abstraction
767 */
768
769/**
770 * enum ath5k_int - Hardware interrupt masks helpers
912#define AR5K_SET_SHORT_PREAMBLE 0x04
913
914/*
915 * Crypto definitions
916 */
917
918#define AR5K_KEYCACHE_SIZE 8
919extern int ath5k_modparam_nohwcrypt;

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933} while (0)
934
935/*
936 * Hardware interrupt abstraction
937 */
938
939/**
940 * enum ath5k_int - Hardware interrupt masks helpers
941 * @AR5K_INT_RXOK: Frame successfully received
942 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor
943 * @AR5K_INT_RXERR: Frame reception failed
944 * @AR5K_INT_RXNOFRM: No frame received within a specified time period
945 * @AR5K_INT_RXEOL: Reached "End Of List", means we need more RX descriptors
946 * @AR5K_INT_RXORN: Indicates we got RX FIFO overrun. Note that Rx overrun is
947 * not always fatal, on some chips we can continue operation
948 * without resetting the card, that's why %AR5K_INT_FATAL is not
949 * common for all chips.
950 * @AR5K_INT_RX_ALL: Mask to identify all RX related interrupts
771 *
951 *
772 * @AR5K_INT_RX: mask to identify received frame interrupts, of type
773 * AR5K_ISR_RXOK or AR5K_ISR_RXERR
774 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?)
775 * @AR5K_INT_RXNOFRM: No frame received (?)
776 * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The
777 * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's
778 * LinkPtr is NULL. For more details, refer to:
779 * http://www.freepatentsonline.com/20030225739.html
780 * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors).
781 * Note that Rx overrun is not always fatal, on some chips we can continue
782 * operation without resetting the card, that's why int_fatal is not
783 * common for all chips.
784 * @AR5K_INT_TX: mask to identify received frame interrupts, of type
785 * AR5K_ISR_TXOK or AR5K_ISR_TXERR
786 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?)
787 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold
788 * We currently do increments on interrupt by
789 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2
952 * @AR5K_INT_TXOK: Frame transmission success
953 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor
954 * @AR5K_INT_TXERR: Frame transmission failure
955 * @AR5K_INT_TXEOL: Received End Of List for VEOL (Virtual End Of List). The
956 * Queue Control Unit (QCU) signals an EOL interrupt only if a
957 * descriptor's LinkPtr is NULL. For more details, refer to:
958 * "http://www.freepatentsonline.com/20030225739.html"
959 * @AR5K_INT_TXNOFRM: No frame was transmitted within a specified time period
960 * @AR5K_INT_TXURN: Indicates we got TX FIFO underrun. In such case we should
961 * increase the TX trigger threshold.
962 * @AR5K_INT_TX_ALL: Mask to identify all TX related interrupts
963 *
790 * @AR5K_INT_MIB: Indicates the either Management Information Base counters or
964 * @AR5K_INT_MIB: Indicates the either Management Information Base counters or
791 * one of the PHY error counters reached the maximum value and should be
792 * read and cleared.
965 * one of the PHY error counters reached the maximum value and
966 * should be read and cleared.
967 * @AR5K_INT_SWI: Software triggered interrupt.
793 * @AR5K_INT_RXPHY: RX PHY Error
794 * @AR5K_INT_RXKCM: RX Key cache miss
795 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
968 * @AR5K_INT_RXPHY: RX PHY Error
969 * @AR5K_INT_RXKCM: RX Key cache miss
970 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
796 * beacon that must be handled in software. The alternative is if you
797 * have VEOL support, in that case you let the hardware deal with things.
971 * beacon that must be handled in software. The alternative is if
972 * you have VEOL support, in that case you let the hardware deal
973 * with things.
974 * @AR5K_INT_BRSSI: Beacon received with an RSSI value below our threshold
798 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
975 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
799 * beacons from the AP have associated with, we should probably try to
800 * reassociate. When in IBSS mode this might mean we have not received
801 * any beacons from any local stations. Note that every station in an
802 * IBSS schedules to send beacons at the Target Beacon Transmission Time
803 * (TBTT) with a random backoff.
804 * @AR5K_INT_BNR: Beacon Not Ready interrupt - ??
805 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now
806 * until properly handled
807 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA
808 * errors. These types of errors we can enable seem to be of type
809 * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR.
976 * beacons from the AP have associated with, we should probably
977 * try to reassociate. When in IBSS mode this might mean we have
978 * not received any beacons from any local stations. Note that
979 * every station in an IBSS schedules to send beacons at the
980 * Target Beacon Transmission Time (TBTT) with a random backoff.
981 * @AR5K_INT_BNR: Beacon queue got triggered (DMA beacon alert) while empty.
982 * @AR5K_INT_TIM: Beacon with local station's TIM bit set
983 * @AR5K_INT_DTIM: Beacon with DTIM bit and zero DTIM count received
984 * @AR5K_INT_DTIM_SYNC: DTIM sync lost
985 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill switches connected to
986 * our GPIO pins.
987 * @AR5K_INT_BCN_TIMEOUT: Beacon timeout, we waited after TBTT but got noting
988 * @AR5K_INT_CAB_TIMEOUT: We waited for CAB traffic after the beacon but got
989 * nothing or an incomplete CAB frame sequence.
990 * @AR5K_INT_QCBRORN: A queue got it's CBR counter expired
991 * @AR5K_INT_QCBRURN: A queue got triggered wile empty
992 * @AR5K_INT_QTRIG: A queue got triggered
993 *
994 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by bus/DMA
995 * errors. Indicates we need to reset the card.
810 * @AR5K_INT_GLOBAL: Used to clear and set the IER
996 * @AR5K_INT_GLOBAL: Used to clear and set the IER
811 * @AR5K_INT_NOCARD: signals the card has been removed
812 * @AR5K_INT_COMMON: common interrupts shared among MACs with the same
813 * bit value
997 * @AR5K_INT_NOCARD: Signals the card has been removed
998 * @AR5K_INT_COMMON: Common interrupts shared among MACs with the same
999 * bit value
814 *
815 * These are mapped to take advantage of some common bits
816 * between the MACs, to be able to set intr properties
817 * easier. Some of them are not used yet inside hw.c. Most map
818 * to the respective hw interrupt value as they are common among different
819 * MACs.
820 */
821enum ath5k_int {

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841 AR5K_INT_FATAL = 0x00080000, /* Non common */
842 AR5K_INT_BNR = 0x00100000, /* Non common */
843 AR5K_INT_TIM = 0x00200000, /* Non common */
844 AR5K_INT_DTIM = 0x00400000, /* Non common */
845 AR5K_INT_DTIM_SYNC = 0x00800000, /* Non common */
846 AR5K_INT_GPIO = 0x01000000,
847 AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */
848 AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */
1000 *
1001 * These are mapped to take advantage of some common bits
1002 * between the MACs, to be able to set intr properties
1003 * easier. Some of them are not used yet inside hw.c. Most map
1004 * to the respective hw interrupt value as they are common among different
1005 * MACs.
1006 */
1007enum ath5k_int {

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1027 AR5K_INT_FATAL = 0x00080000, /* Non common */
1028 AR5K_INT_BNR = 0x00100000, /* Non common */
1029 AR5K_INT_TIM = 0x00200000, /* Non common */
1030 AR5K_INT_DTIM = 0x00400000, /* Non common */
1031 AR5K_INT_DTIM_SYNC = 0x00800000, /* Non common */
1032 AR5K_INT_GPIO = 0x01000000,
1033 AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */
1034 AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */
849 AR5K_INT_RX_DOPPLER = 0x08000000, /* Non common */
850 AR5K_INT_QCBRORN = 0x10000000, /* Non common */
851 AR5K_INT_QCBRURN = 0x20000000, /* Non common */
852 AR5K_INT_QTRIG = 0x40000000, /* Non common */
1035 AR5K_INT_QCBRORN = 0x08000000, /* Non common */
1036 AR5K_INT_QCBRURN = 0x10000000, /* Non common */
1037 AR5K_INT_QTRIG = 0x20000000, /* Non common */
853 AR5K_INT_GLOBAL = 0x80000000,
854
855 AR5K_INT_TX_ALL = AR5K_INT_TXOK
856 | AR5K_INT_TXDESC
857 | AR5K_INT_TXERR
858 | AR5K_INT_TXNOFRM
859 | AR5K_INT_TXEOL
860 | AR5K_INT_TXURN,

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886 | AR5K_INT_BRSSI
887 | AR5K_INT_BMISS
888 | AR5K_INT_GPIO
889 | AR5K_INT_GLOBAL,
890
891 AR5K_INT_NOCARD = 0xffffffff
892};
893
1038 AR5K_INT_GLOBAL = 0x80000000,
1039
1040 AR5K_INT_TX_ALL = AR5K_INT_TXOK
1041 | AR5K_INT_TXDESC
1042 | AR5K_INT_TXERR
1043 | AR5K_INT_TXNOFRM
1044 | AR5K_INT_TXEOL
1045 | AR5K_INT_TXURN,

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1071 | AR5K_INT_BRSSI
1072 | AR5K_INT_BMISS
1073 | AR5K_INT_GPIO
1074 | AR5K_INT_GLOBAL,
1075
1076 AR5K_INT_NOCARD = 0xffffffff
1077};
1078
894/* mask which calibration is active at the moment */
1079/**
1080 * enum ath5k_calibration_mask - Mask which calibration is active at the moment
1081 * @AR5K_CALIBRATION_FULL: Full calibration (AGC + SHORT)
1082 * @AR5K_CALIBRATION_SHORT: Short calibration (NF + I/Q)
1083 * @AR5K_CALIBRATION_NF: Noise Floor calibration
1084 * @AR5K_CALIBRATION_ANI: Adaptive Noise Immunity
1085 */
895enum ath5k_calibration_mask {
896 AR5K_CALIBRATION_FULL = 0x01,
897 AR5K_CALIBRATION_SHORT = 0x02,
898 AR5K_CALIBRATION_NF = 0x04,
899 AR5K_CALIBRATION_ANI = 0x08,
900};
901
1086enum ath5k_calibration_mask {
1087 AR5K_CALIBRATION_FULL = 0x01,
1088 AR5K_CALIBRATION_SHORT = 0x02,
1089 AR5K_CALIBRATION_NF = 0x04,
1090 AR5K_CALIBRATION_ANI = 0x08,
1091};
1092
902/*
903 * Power management
1093/**
1094 * enum ath5k_power_mode - Power management modes
1095 * @AR5K_PM_UNDEFINED: Undefined
1096 * @AR5K_PM_AUTO: Allow card to sleep if possible
1097 * @AR5K_PM_AWAKE: Force card to wake up
1098 * @AR5K_PM_FULL_SLEEP: Force card to full sleep (DANGEROUS)
1099 * @AR5K_PM_NETWORK_SLEEP: Allow to sleep for a specified duration
1100 *
1101 * Currently only PM_AWAKE is used, FULL_SLEEP and NETWORK_SLEEP/AUTO
1102 * are also known to have problems on some cards. This is not a big
1103 * problem though because we can have almost the same effect as
1104 * FULL_SLEEP by putting card on warm reset (it's almost powered down).
904 */
905enum ath5k_power_mode {
906 AR5K_PM_UNDEFINED = 0,
907 AR5K_PM_AUTO,
908 AR5K_PM_AWAKE,
909 AR5K_PM_FULL_SLEEP,
910 AR5K_PM_NETWORK_SLEEP,
911};

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1339void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
1340/* Receive (DRU) start/stop functions */
1341void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
1342void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
1343/* Beacon control functions */
1344u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
1345void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64);
1346void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
1105 */
1106enum ath5k_power_mode {
1107 AR5K_PM_UNDEFINED = 0,
1108 AR5K_PM_AUTO,
1109 AR5K_PM_AWAKE,
1110 AR5K_PM_FULL_SLEEP,
1111 AR5K_PM_NETWORK_SLEEP,
1112};

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1540void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
1541/* Receive (DRU) start/stop functions */
1542void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
1543void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
1544/* Beacon control functions */
1545u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
1546void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64);
1547void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
1347void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval);
1548void ath5k_hw_init_beacon_timers(struct ath5k_hw *ah, u32 next_beacon,
1549 u32 interval);
1348bool ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval);
1349/* Init function */
1550bool ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval);
1551/* Init function */
1350void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1351 u8 mode);
1552void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode);
1352
1353/* Queue Control Unit, DFS Control Unit Functions */
1354int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
1355 struct ath5k_txq_info *queue_info);
1356int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
1357 const struct ath5k_txq_info *queue_info);
1358int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
1359 enum ath5k_tx_queue queue_type,

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1554/* Queue Control Unit, DFS Control Unit Functions */
1555int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
1556 struct ath5k_txq_info *queue_info);
1557int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
1558 const struct ath5k_txq_info *queue_info);
1559int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
1560 enum ath5k_tx_queue queue_type,

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