ani.c (d4bbf7e7759afc172e2bfbc5c416324590049cdd) ani.c (c47faa364cfb249d5d7670fb7293a6f9acd8aa9e)
1/*
2 * Copyright (C) 2010 Bruno Randolf <br1@einfach.org>
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

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22/**
23 * DOC: Basic ANI Operation
24 *
25 * Adaptive Noise Immunity (ANI) controls five noise immunity parameters
26 * depending on the amount of interference in the environment, increasing
27 * or reducing sensitivity as necessary.
28 *
29 * The parameters are:
1/*
2 * Copyright (C) 2010 Bruno Randolf <br1@einfach.org>
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

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22/**
23 * DOC: Basic ANI Operation
24 *
25 * Adaptive Noise Immunity (ANI) controls five noise immunity parameters
26 * depending on the amount of interference in the environment, increasing
27 * or reducing sensitivity as necessary.
28 *
29 * The parameters are:
30 *
30 * - "noise immunity"
31 * - "noise immunity"
32 *
31 * - "spur immunity"
33 * - "spur immunity"
34 *
32 * - "firstep level"
35 * - "firstep level"
36 *
33 * - "OFDM weak signal detection"
37 * - "OFDM weak signal detection"
38 *
34 * - "CCK weak signal detection"
35 *
36 * Basically we look at the amount of ODFM and CCK timing errors we get and then
37 * raise or lower immunity accordingly by setting one or more of these
38 * parameters.
39 * - "CCK weak signal detection"
40 *
41 * Basically we look at the amount of ODFM and CCK timing errors we get and then
42 * raise or lower immunity accordingly by setting one or more of these
43 * parameters.
44 *
39 * Newer chipsets have PHY error counters in hardware which will generate a MIB
40 * interrupt when they overflow. Older hardware has too enable PHY error frames
41 * by setting a RX flag and then count every single PHY error. When a specified
42 * threshold of errors has been reached we will raise immunity.
43 * Also we regularly check the amount of errors and lower or raise immunity as
44 * necessary.
45 */
46
47
45 * Newer chipsets have PHY error counters in hardware which will generate a MIB
46 * interrupt when they overflow. Older hardware has too enable PHY error frames
47 * by setting a RX flag and then count every single PHY error. When a specified
48 * threshold of errors has been reached we will raise immunity.
49 * Also we regularly check the amount of errors and lower or raise immunity as
50 * necessary.
51 */
52
53
48/*** ANI parameter control ***/
54/***********************\
55* ANI parameter control *
56\***********************/
49
50/**
51 * ath5k_ani_set_noise_immunity_level() - Set noise immunity level
57
58/**
59 * ath5k_ani_set_noise_immunity_level() - Set noise immunity level
52 *
60 * @ah: The &struct ath5k_hw
53 * @level: level between 0 and @ATH5K_ANI_MAX_NOISE_IMM_LVL
54 */
55void
56ath5k_ani_set_noise_immunity_level(struct ath5k_hw *ah, int level)
57{
58 /* TODO:
59 * ANI documents suggest the following five levels to use, but the HAL
60 * and ath9k use only the last two levels, making this

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86 AR5K_PHY_AGCCOARSE_HI, hi[level]);
87 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SIG,
88 AR5K_PHY_SIG_FIRPWR, fr[level]);
89
90 ah->ani_state.noise_imm_level = level;
91 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "new level %d", level);
92}
93
61 * @level: level between 0 and @ATH5K_ANI_MAX_NOISE_IMM_LVL
62 */
63void
64ath5k_ani_set_noise_immunity_level(struct ath5k_hw *ah, int level)
65{
66 /* TODO:
67 * ANI documents suggest the following five levels to use, but the HAL
68 * and ath9k use only the last two levels, making this

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94 AR5K_PHY_AGCCOARSE_HI, hi[level]);
95 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SIG,
96 AR5K_PHY_SIG_FIRPWR, fr[level]);
97
98 ah->ani_state.noise_imm_level = level;
99 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "new level %d", level);
100}
101
94
95/**
96 * ath5k_ani_set_spur_immunity_level() - Set spur immunity level
102/**
103 * ath5k_ani_set_spur_immunity_level() - Set spur immunity level
97 *
104 * @ah: The &struct ath5k_hw
98 * @level: level between 0 and @max_spur_level (the maximum level is dependent
105 * @level: level between 0 and @max_spur_level (the maximum level is dependent
99 * on the chip revision).
106 * on the chip revision).
100 */
101void
102ath5k_ani_set_spur_immunity_level(struct ath5k_hw *ah, int level)
103{
104 static const int val[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
105
106 if (level < 0 || level >= ARRAY_SIZE(val) ||
107 level > ah->ani_state.max_spur_level) {

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112
113 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
114 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1, val[level]);
115
116 ah->ani_state.spur_level = level;
117 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "new level %d", level);
118}
119
107 */
108void
109ath5k_ani_set_spur_immunity_level(struct ath5k_hw *ah, int level)
110{
111 static const int val[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
112
113 if (level < 0 || level >= ARRAY_SIZE(val) ||
114 level > ah->ani_state.max_spur_level) {

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119
120 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
121 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1, val[level]);
122
123 ah->ani_state.spur_level = level;
124 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "new level %d", level);
125}
126
120
121/**
122 * ath5k_ani_set_firstep_level() - Set "firstep" level
127/**
128 * ath5k_ani_set_firstep_level() - Set "firstep" level
123 *
129 * @ah: The &struct ath5k_hw
124 * @level: level between 0 and @ATH5K_ANI_MAX_FIRSTEP_LVL
125 */
126void
127ath5k_ani_set_firstep_level(struct ath5k_hw *ah, int level)
128{
129 static const int val[] = { 0, 4, 8 };
130
131 if (level < 0 || level >= ARRAY_SIZE(val)) {
132 ATH5K_ERR(ah, "firstep level %d out of range", level);
133 return;
134 }
135
136 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SIG,
137 AR5K_PHY_SIG_FIRSTEP, val[level]);
138
139 ah->ani_state.firstep_level = level;
140 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "new level %d", level);
141}
142
130 * @level: level between 0 and @ATH5K_ANI_MAX_FIRSTEP_LVL
131 */
132void
133ath5k_ani_set_firstep_level(struct ath5k_hw *ah, int level)
134{
135 static const int val[] = { 0, 4, 8 };
136
137 if (level < 0 || level >= ARRAY_SIZE(val)) {
138 ATH5K_ERR(ah, "firstep level %d out of range", level);
139 return;
140 }
141
142 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SIG,
143 AR5K_PHY_SIG_FIRSTEP, val[level]);
144
145 ah->ani_state.firstep_level = level;
146 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "new level %d", level);
147}
148
143
144/**
149/**
145 * ath5k_ani_set_ofdm_weak_signal_detection() - Control OFDM weak signal
146 * detection
147 *
150 * ath5k_ani_set_ofdm_weak_signal_detection() - Set OFDM weak signal detection
151 * @ah: The &struct ath5k_hw
148 * @on: turn on or off
149 */
150void
151ath5k_ani_set_ofdm_weak_signal_detection(struct ath5k_hw *ah, bool on)
152{
153 static const int m1l[] = { 127, 50 };
154 static const int m2l[] = { 127, 40 };
155 static const int m1[] = { 127, 0x4d };

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177 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR,
178 AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN);
179
180 ah->ani_state.ofdm_weak_sig = on;
181 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "turned %s",
182 on ? "on" : "off");
183}
184
152 * @on: turn on or off
153 */
154void
155ath5k_ani_set_ofdm_weak_signal_detection(struct ath5k_hw *ah, bool on)
156{
157 static const int m1l[] = { 127, 50 };
158 static const int m2l[] = { 127, 40 };
159 static const int m1[] = { 127, 0x4d };

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181 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR,
182 AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN);
183
184 ah->ani_state.ofdm_weak_sig = on;
185 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "turned %s",
186 on ? "on" : "off");
187}
188
185
186/**
189/**
187 * ath5k_ani_set_cck_weak_signal_detection() - control CCK weak signal detection
188 *
190 * ath5k_ani_set_cck_weak_signal_detection() - Set CCK weak signal detection
191 * @ah: The &struct ath5k_hw
189 * @on: turn on or off
190 */
191void
192ath5k_ani_set_cck_weak_signal_detection(struct ath5k_hw *ah, bool on)
193{
194 static const int val[] = { 8, 6 };
195 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_CCK_CROSSCORR,
196 AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR, val[on]);
197 ah->ani_state.cck_weak_sig = on;
198 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "turned %s",
199 on ? "on" : "off");
200}
201
202
192 * @on: turn on or off
193 */
194void
195ath5k_ani_set_cck_weak_signal_detection(struct ath5k_hw *ah, bool on)
196{
197 static const int val[] = { 8, 6 };
198 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_CCK_CROSSCORR,
199 AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR, val[on]);
200 ah->ani_state.cck_weak_sig = on;
201 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "turned %s",
202 on ? "on" : "off");
203}
204
205
203/*** ANI algorithm ***/
206/***************\
207* ANI algorithm *
208\***************/
204
205/**
206 * ath5k_ani_raise_immunity() - Increase noise immunity
209
210/**
211 * ath5k_ani_raise_immunity() - Increase noise immunity
207 *
212 * @ah: The &struct ath5k_hw
213 * @as: The &struct ath5k_ani_state
208 * @ofdm_trigger: If this is true we are called because of too many OFDM errors,
214 * @ofdm_trigger: If this is true we are called because of too many OFDM errors,
209 * the algorithm will tune more parameters then.
215 * the algorithm will tune more parameters then.
210 *
211 * Try to raise noise immunity (=decrease sensitivity) in several steps
212 * depending on the average RSSI of the beacons we received.
213 */
214static void
215ath5k_ani_raise_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as,
216 bool ofdm_trigger)
217{

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285
286 /* TODO: why not?:
287 if (as->cck_weak_sig == true) {
288 ath5k_ani_set_cck_weak_signal_detection(ah, false);
289 }
290 */
291}
292
216 *
217 * Try to raise noise immunity (=decrease sensitivity) in several steps
218 * depending on the average RSSI of the beacons we received.
219 */
220static void
221ath5k_ani_raise_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as,
222 bool ofdm_trigger)
223{

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291
292 /* TODO: why not?:
293 if (as->cck_weak_sig == true) {
294 ath5k_ani_set_cck_weak_signal_detection(ah, false);
295 }
296 */
297}
298
293
294/**
295 * ath5k_ani_lower_immunity() - Decrease noise immunity
299/**
300 * ath5k_ani_lower_immunity() - Decrease noise immunity
301 * @ah: The &struct ath5k_hw
302 * @as: The &struct ath5k_ani_state
296 *
297 * Try to lower noise immunity (=increase sensitivity) in several steps
298 * depending on the average RSSI of the beacons we received.
299 */
300static void
301ath5k_ani_lower_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as)
302{
303 int rssi = ewma_read(&ah->ah_beacon_rssi_avg);

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347
348 /* finally, reduce noise immunity */
349 if (as->noise_imm_level > 0) {
350 ath5k_ani_set_noise_immunity_level(ah, as->noise_imm_level - 1);
351 return;
352 }
353}
354
303 *
304 * Try to lower noise immunity (=increase sensitivity) in several steps
305 * depending on the average RSSI of the beacons we received.
306 */
307static void
308ath5k_ani_lower_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as)
309{
310 int rssi = ewma_read(&ah->ah_beacon_rssi_avg);

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354
355 /* finally, reduce noise immunity */
356 if (as->noise_imm_level > 0) {
357 ath5k_ani_set_noise_immunity_level(ah, as->noise_imm_level - 1);
358 return;
359 }
360}
361
355
356/**
357 * ath5k_hw_ani_get_listen_time() - Update counters and return listening time
362/**
363 * ath5k_hw_ani_get_listen_time() - Update counters and return listening time
364 * @ah: The &struct ath5k_hw
365 * @as: The &struct ath5k_ani_state
358 *
359 * Return an approximation of the time spent "listening" in milliseconds (ms)
360 * since the last call of this function.
361 * Save a snapshot of the counter values for debugging/statistics.
362 */
363static int
364ath5k_hw_ani_get_listen_time(struct ath5k_hw *ah, struct ath5k_ani_state *as)
365{

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374 /* clears common->cc_ani */
375 listen = ath_hw_get_listen_time(common);
376
377 spin_unlock_bh(&common->cc_lock);
378
379 return listen;
380}
381
366 *
367 * Return an approximation of the time spent "listening" in milliseconds (ms)
368 * since the last call of this function.
369 * Save a snapshot of the counter values for debugging/statistics.
370 */
371static int
372ath5k_hw_ani_get_listen_time(struct ath5k_hw *ah, struct ath5k_ani_state *as)
373{

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382 /* clears common->cc_ani */
383 listen = ath_hw_get_listen_time(common);
384
385 spin_unlock_bh(&common->cc_lock);
386
387 return listen;
388}
389
382
383/**
384 * ath5k_ani_save_and_clear_phy_errors() - Clear and save PHY error counters
390/**
391 * ath5k_ani_save_and_clear_phy_errors() - Clear and save PHY error counters
392 * @ah: The &struct ath5k_hw
393 * @as: The &struct ath5k_ani_state
385 *
386 * Clear the PHY error counters as soon as possible, since this might be called
387 * from a MIB interrupt and we want to make sure we don't get interrupted again.
388 * Add the count of CCK and OFDM errors to our internal state, so it can be used
389 * by the algorithm later.
390 *
391 * Will be called from interrupt and tasklet context.
392 * Returns 0 if both counters are zero.

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424 }
425 if (cck_err > 0) {
426 as->cck_errors += cck_err;
427 as->sum_cck_errors += cck_err;
428 }
429 return 1;
430}
431
394 *
395 * Clear the PHY error counters as soon as possible, since this might be called
396 * from a MIB interrupt and we want to make sure we don't get interrupted again.
397 * Add the count of CCK and OFDM errors to our internal state, so it can be used
398 * by the algorithm later.
399 *
400 * Will be called from interrupt and tasklet context.
401 * Returns 0 if both counters are zero.

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433 }
434 if (cck_err > 0) {
435 as->cck_errors += cck_err;
436 as->sum_cck_errors += cck_err;
437 }
438 return 1;
439}
440
432
433/**
434 * ath5k_ani_period_restart() - Restart ANI period
441/**
442 * ath5k_ani_period_restart() - Restart ANI period
443 * @ah: The &struct ath5k_hw
444 * @as: The &struct ath5k_ani_state
435 *
436 * Just reset counters, so they are clear for the next "ani period".
437 */
438static void
439ath5k_ani_period_restart(struct ath5k_hw *ah, struct ath5k_ani_state *as)
440{
441 /* keep last values for debugging */
442 as->last_ofdm_errors = as->ofdm_errors;
443 as->last_cck_errors = as->cck_errors;
444 as->last_listen = as->listen_time;
445
446 as->ofdm_errors = 0;
447 as->cck_errors = 0;
448 as->listen_time = 0;
449}
450
445 *
446 * Just reset counters, so they are clear for the next "ani period".
447 */
448static void
449ath5k_ani_period_restart(struct ath5k_hw *ah, struct ath5k_ani_state *as)
450{
451 /* keep last values for debugging */
452 as->last_ofdm_errors = as->ofdm_errors;
453 as->last_cck_errors = as->cck_errors;
454 as->last_listen = as->listen_time;
455
456 as->ofdm_errors = 0;
457 as->cck_errors = 0;
458 as->listen_time = 0;
459}
460
451
452/**
453 * ath5k_ani_calibration() - The main ANI calibration function
461/**
462 * ath5k_ani_calibration() - The main ANI calibration function
463 * @ah: The &struct ath5k_hw
454 *
455 * We count OFDM and CCK errors relative to the time where we did not send or
456 * receive ("listen" time) and raise or lower immunity accordingly.
457 * This is called regularly (every second) from the calibration timer, but also
458 * when an error threshold has been reached.
459 *
460 * In order to synchronize access from different contexts, this should be
461 * called only indirectly by scheduling the ANI tasklet!

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504 if (as->ofdm_errors <= ofdm_low && as->cck_errors <= cck_low)
505 ath5k_ani_lower_immunity(ah, as);
506
507 ath5k_ani_period_restart(ah, as);
508 }
509}
510
511
464 *
465 * We count OFDM and CCK errors relative to the time where we did not send or
466 * receive ("listen" time) and raise or lower immunity accordingly.
467 * This is called regularly (every second) from the calibration timer, but also
468 * when an error threshold has been reached.
469 *
470 * In order to synchronize access from different contexts, this should be
471 * called only indirectly by scheduling the ANI tasklet!

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514 if (as->ofdm_errors <= ofdm_low && as->cck_errors <= cck_low)
515 ath5k_ani_lower_immunity(ah, as);
516
517 ath5k_ani_period_restart(ah, as);
518 }
519}
520
521
512/*** INTERRUPT HANDLER ***/
522/*******************\
523* Interrupt handler *
524\*******************/
513
514/**
515 * ath5k_ani_mib_intr() - Interrupt handler for ANI MIB counters
525
526/**
527 * ath5k_ani_mib_intr() - Interrupt handler for ANI MIB counters
528 * @ah: The &struct ath5k_hw
516 *
517 * Just read & reset the registers quickly, so they don't generate more
518 * interrupts, save the counters and schedule the tasklet to decide whether
519 * to raise immunity or not.
520 *
521 * We just need to handle PHY error counters, ath5k_hw_update_mib_counters()
522 * should take care of all "normal" MIB interrupts.
523 */

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544 if (ath5k_ani_save_and_clear_phy_errors(ah, as) == 0)
545 return;
546
547 if (as->ofdm_errors > ATH5K_ANI_OFDM_TRIG_HIGH ||
548 as->cck_errors > ATH5K_ANI_CCK_TRIG_HIGH)
549 tasklet_schedule(&ah->ani_tasklet);
550}
551
529 *
530 * Just read & reset the registers quickly, so they don't generate more
531 * interrupts, save the counters and schedule the tasklet to decide whether
532 * to raise immunity or not.
533 *
534 * We just need to handle PHY error counters, ath5k_hw_update_mib_counters()
535 * should take care of all "normal" MIB interrupts.
536 */

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557 if (ath5k_ani_save_and_clear_phy_errors(ah, as) == 0)
558 return;
559
560 if (as->ofdm_errors > ATH5K_ANI_OFDM_TRIG_HIGH ||
561 as->cck_errors > ATH5K_ANI_CCK_TRIG_HIGH)
562 tasklet_schedule(&ah->ani_tasklet);
563}
564
552
553/**
565/**
554 * ath5k_ani_phy_error_report() - Used by older HW to report PHY errors
566 * ath5k_ani_phy_error_report - Used by older HW to report PHY errors
555 *
567 *
568 * @ah: The &struct ath5k_hw
569 * @phyerr: One of enum ath5k_phy_error_code
570 *
556 * This is used by hardware without PHY error counters to report PHY errors
557 * on a frame-by-frame basis, instead of the interrupt.
558 */
559void
560ath5k_ani_phy_error_report(struct ath5k_hw *ah,
561 enum ath5k_phy_error_code phyerr)
562{
563 struct ath5k_ani_state *as = &ah->ani_state;

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569 } else if (phyerr == AR5K_RX_PHY_ERROR_CCK_TIMING) {
570 as->cck_errors++;
571 if (as->cck_errors > ATH5K_ANI_CCK_TRIG_HIGH)
572 tasklet_schedule(&ah->ani_tasklet);
573 }
574}
575
576
571 * This is used by hardware without PHY error counters to report PHY errors
572 * on a frame-by-frame basis, instead of the interrupt.
573 */
574void
575ath5k_ani_phy_error_report(struct ath5k_hw *ah,
576 enum ath5k_phy_error_code phyerr)
577{
578 struct ath5k_ani_state *as = &ah->ani_state;

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584 } else if (phyerr == AR5K_RX_PHY_ERROR_CCK_TIMING) {
585 as->cck_errors++;
586 if (as->cck_errors > ATH5K_ANI_CCK_TRIG_HIGH)
587 tasklet_schedule(&ah->ani_tasklet);
588 }
589}
590
591
577/*** INIT ***/
592/****************\
593* Initialization *
594\****************/
578
579/**
580 * ath5k_enable_phy_err_counters() - Enable PHY error counters
595
596/**
597 * ath5k_enable_phy_err_counters() - Enable PHY error counters
598 * @ah: The &struct ath5k_hw
581 *
582 * Enable PHY error counters for OFDM and CCK timing errors.
583 */
584static void
585ath5k_enable_phy_err_counters(struct ath5k_hw *ah)
586{
587 ath5k_hw_reg_write(ah, ATH5K_PHYERR_CNT_MAX - ATH5K_ANI_OFDM_TRIG_HIGH,
588 AR5K_PHYERR_CNT1);
589 ath5k_hw_reg_write(ah, ATH5K_PHYERR_CNT_MAX - ATH5K_ANI_CCK_TRIG_HIGH,
590 AR5K_PHYERR_CNT2);
591 ath5k_hw_reg_write(ah, AR5K_PHY_ERR_FIL_OFDM, AR5K_PHYERR_CNT1_MASK);
592 ath5k_hw_reg_write(ah, AR5K_PHY_ERR_FIL_CCK, AR5K_PHYERR_CNT2_MASK);
593
594 /* not in use */
595 ath5k_hw_reg_write(ah, 0, AR5K_OFDM_FIL_CNT);
596 ath5k_hw_reg_write(ah, 0, AR5K_CCK_FIL_CNT);
597}
598
599 *
600 * Enable PHY error counters for OFDM and CCK timing errors.
601 */
602static void
603ath5k_enable_phy_err_counters(struct ath5k_hw *ah)
604{
605 ath5k_hw_reg_write(ah, ATH5K_PHYERR_CNT_MAX - ATH5K_ANI_OFDM_TRIG_HIGH,
606 AR5K_PHYERR_CNT1);
607 ath5k_hw_reg_write(ah, ATH5K_PHYERR_CNT_MAX - ATH5K_ANI_CCK_TRIG_HIGH,
608 AR5K_PHYERR_CNT2);
609 ath5k_hw_reg_write(ah, AR5K_PHY_ERR_FIL_OFDM, AR5K_PHYERR_CNT1_MASK);
610 ath5k_hw_reg_write(ah, AR5K_PHY_ERR_FIL_CCK, AR5K_PHYERR_CNT2_MASK);
611
612 /* not in use */
613 ath5k_hw_reg_write(ah, 0, AR5K_OFDM_FIL_CNT);
614 ath5k_hw_reg_write(ah, 0, AR5K_CCK_FIL_CNT);
615}
616
599
600/**
601 * ath5k_disable_phy_err_counters() - Disable PHY error counters
617/**
618 * ath5k_disable_phy_err_counters() - Disable PHY error counters
619 * @ah: The &struct ath5k_hw
602 *
603 * Disable PHY error counters for OFDM and CCK timing errors.
604 */
605static void
606ath5k_disable_phy_err_counters(struct ath5k_hw *ah)
607{
608 ath5k_hw_reg_write(ah, 0, AR5K_PHYERR_CNT1);
609 ath5k_hw_reg_write(ah, 0, AR5K_PHYERR_CNT2);
610 ath5k_hw_reg_write(ah, 0, AR5K_PHYERR_CNT1_MASK);
611 ath5k_hw_reg_write(ah, 0, AR5K_PHYERR_CNT2_MASK);
612
613 /* not in use */
614 ath5k_hw_reg_write(ah, 0, AR5K_OFDM_FIL_CNT);
615 ath5k_hw_reg_write(ah, 0, AR5K_CCK_FIL_CNT);
616}
617
620 *
621 * Disable PHY error counters for OFDM and CCK timing errors.
622 */
623static void
624ath5k_disable_phy_err_counters(struct ath5k_hw *ah)
625{
626 ath5k_hw_reg_write(ah, 0, AR5K_PHYERR_CNT1);
627 ath5k_hw_reg_write(ah, 0, AR5K_PHYERR_CNT2);
628 ath5k_hw_reg_write(ah, 0, AR5K_PHYERR_CNT1_MASK);
629 ath5k_hw_reg_write(ah, 0, AR5K_PHYERR_CNT2_MASK);
630
631 /* not in use */
632 ath5k_hw_reg_write(ah, 0, AR5K_OFDM_FIL_CNT);
633 ath5k_hw_reg_write(ah, 0, AR5K_CCK_FIL_CNT);
634}
635
618
619/**
620 * ath5k_ani_init() - Initialize ANI
636/**
637 * ath5k_ani_init() - Initialize ANI
621 * @mode: Which mode to use (auto, manual high, manual low, off)
638 * @ah: The &struct ath5k_hw
639 * @mode: One of enum ath5k_ani_mode
622 *
623 * Initialize ANI according to mode.
624 */
625void
626ath5k_ani_init(struct ath5k_hw *ah, enum ath5k_ani_mode mode)
627{
628 /* ANI is only possible on 5212 and newer */
629 if (ah->ah_version < AR5K_AR5212)

--- 60 unchanged lines hidden (view full) ---

690 ath5k_hw_set_rx_filter(ah, ath5k_hw_get_rx_filter(ah) &
691 ~AR5K_RX_FILTER_PHYERR);
692 }
693
694 ah->ani_state.ani_mode = mode;
695}
696
697
640 *
641 * Initialize ANI according to mode.
642 */
643void
644ath5k_ani_init(struct ath5k_hw *ah, enum ath5k_ani_mode mode)
645{
646 /* ANI is only possible on 5212 and newer */
647 if (ah->ah_version < AR5K_AR5212)

--- 60 unchanged lines hidden (view full) ---

708 ath5k_hw_set_rx_filter(ah, ath5k_hw_get_rx_filter(ah) &
709 ~AR5K_RX_FILTER_PHYERR);
710 }
711
712 ah->ani_state.ani_mode = mode;
713}
714
715
698/*** DEBUG ***/
716/**************\
717* Debug output *
718\**************/
699
700#ifdef CONFIG_ATH5K_DEBUG
701
719
720#ifdef CONFIG_ATH5K_DEBUG
721
722/**
723 * ath5k_ani_print_counters() - Print ANI counters
724 * @ah: The &struct ath5k_hw
725 *
726 * Used for debugging ANI
727 */
702void
703ath5k_ani_print_counters(struct ath5k_hw *ah)
704{
705 /* clears too */
706 printk(KERN_NOTICE "ACK fail\t%d\n",
707 ath5k_hw_reg_read(ah, AR5K_ACK_FAIL));
708 printk(KERN_NOTICE "RTS fail\t%d\n",
709 ath5k_hw_reg_read(ah, AR5K_RTS_FAIL));

--- 26 unchanged lines hidden --- 		728void
729ath5k_ani_print_counters(struct ath5k_hw *ah)
730{
731 /* clears too */
732 printk(KERN_NOTICE "ACK fail\t%d\n",
733 ath5k_hw_reg_read(ah, AR5K_ACK_FAIL));
734 printk(KERN_NOTICE "RTS fail\t%d\n",
735 ath5k_hw_reg_read(ah, AR5K_RTS_FAIL));

--- 26 unchanged lines hidden ---