hal.h (ca0df43d211039dded5a8f8553356414c9a74731) hal.h (480c9df5778774117546f6389be1a8dc8cc935db)
1/* SPDX-License-Identifier: BSD-3-Clause-Clear */
2/*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7#ifndef ATH12K_HAL_H
8#define ATH12K_HAL_H

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265
266#define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN BIT(1)
267#define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW1_EN BIT(2)
268#define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN BIT(3)
269#define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN BIT(4)
270#define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN BIT(5)
271#define HAL_WBM_SW_COOKIE_CONV_CFG_GLOBAL_EN BIT(8)
272
1/* SPDX-License-Identifier: BSD-3-Clause-Clear */
2/*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7#ifndef ATH12K_HAL_H
8#define ATH12K_HAL_H

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265
266#define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN BIT(1)
267#define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW1_EN BIT(2)
268#define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN BIT(3)
269#define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN BIT(4)
270#define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN BIT(5)
271#define HAL_WBM_SW_COOKIE_CONV_CFG_GLOBAL_EN BIT(8)
272
273/* TCL ring feild mask and offset */
273/* TCL ring field mask and offset */
274#define HAL_TCL1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8)
275#define HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0)
276#define HAL_TCL1_RING_ID_ENTRY_SIZE GENMASK(7, 0)
277#define HAL_TCL1_RING_MISC_MSI_RING_ID_DISABLE BIT(0)
278#define HAL_TCL1_RING_MISC_MSI_LOOPCNT_DISABLE BIT(1)
279#define HAL_TCL1_RING_MISC_MSI_SWAP BIT(3)
280#define HAL_TCL1_RING_MISC_HOST_FW_SWAP BIT(4)
281#define HAL_TCL1_RING_MISC_DATA_TLV_SWAP BIT(5)

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291#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP1 GENMASK(5, 3)
292#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP2 GENMASK(8, 6)
293#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP3 GENMASK(11, 9)
294#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP4 GENMASK(14, 12)
295#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP5 GENMASK(17, 15)
296#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP6 GENMASK(20, 18)
297#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP7 GENMASK(23, 21)
298
274#define HAL_TCL1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8)
275#define HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0)
276#define HAL_TCL1_RING_ID_ENTRY_SIZE GENMASK(7, 0)
277#define HAL_TCL1_RING_MISC_MSI_RING_ID_DISABLE BIT(0)
278#define HAL_TCL1_RING_MISC_MSI_LOOPCNT_DISABLE BIT(1)
279#define HAL_TCL1_RING_MISC_MSI_SWAP BIT(3)
280#define HAL_TCL1_RING_MISC_HOST_FW_SWAP BIT(4)
281#define HAL_TCL1_RING_MISC_DATA_TLV_SWAP BIT(5)

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291#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP1 GENMASK(5, 3)
292#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP2 GENMASK(8, 6)
293#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP3 GENMASK(11, 9)
294#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP4 GENMASK(14, 12)
295#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP5 GENMASK(17, 15)
296#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP6 GENMASK(20, 18)
297#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP7 GENMASK(23, 21)
298
299/* REO ring feild mask and offset */
299/* REO ring field mask and offset */
300#define HAL_REO1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8)
301#define HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0)
302#define HAL_REO1_RING_ID_RING_ID GENMASK(15, 8)
303#define HAL_REO1_RING_ID_ENTRY_SIZE GENMASK(7, 0)
304#define HAL_REO1_RING_MISC_MSI_SWAP BIT(3)
305#define HAL_REO1_RING_MISC_HOST_FW_SWAP BIT(4)
306#define HAL_REO1_RING_MISC_DATA_TLV_SWAP BIT(5)
307#define HAL_REO1_RING_MISC_SRNG_ENABLE BIT(6)

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733 u32 low_threshold;
734
735 /* tail pointer at access end */
736 u32 last_tp;
737 } src_ring;
738 } u;
739};
740
300#define HAL_REO1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8)
301#define HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0)
302#define HAL_REO1_RING_ID_RING_ID GENMASK(15, 8)
303#define HAL_REO1_RING_ID_ENTRY_SIZE GENMASK(7, 0)
304#define HAL_REO1_RING_MISC_MSI_SWAP BIT(3)
305#define HAL_REO1_RING_MISC_HOST_FW_SWAP BIT(4)
306#define HAL_REO1_RING_MISC_DATA_TLV_SWAP BIT(5)
307#define HAL_REO1_RING_MISC_SRNG_ENABLE BIT(6)

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733 u32 low_threshold;
734
735 /* tail pointer at access end */
736 u32 last_tp;
737 } src_ring;
738 } u;
739};
740
741/* Interrupt mitigation - Batch threshold in terms of numer of frames */
741/* Interrupt mitigation - Batch threshold in terms of number of frames */
742#define HAL_SRNG_INT_BATCH_THRESHOLD_TX 256
743#define HAL_SRNG_INT_BATCH_THRESHOLD_RX 128
744#define HAL_SRNG_INT_BATCH_THRESHOLD_OTHER 1
745
746/* Interrupt mitigation - timer threshold in us */
747#define HAL_SRNG_INT_TIMER_THRESHOLD_TX 1000
748#define HAL_SRNG_INT_TIMER_THRESHOLD_RX 500
749#define HAL_SRNG_INT_TIMER_THRESHOLD_OTHER 256

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808#define HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER BIT(2)
809#define HAL_REO_CMD_FLG_FLUSH_RELEASE_BLOCKING BIT(3)
810#define HAL_REO_CMD_FLG_FLUSH_NO_INVAL BIT(4)
811#define HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS BIT(5)
812#define HAL_REO_CMD_FLG_FLUSH_ALL BIT(6)
813#define HAL_REO_CMD_FLG_UNBLK_RESOURCE BIT(7)
814#define HAL_REO_CMD_FLG_UNBLK_CACHE BIT(8)
815
742#define HAL_SRNG_INT_BATCH_THRESHOLD_TX 256
743#define HAL_SRNG_INT_BATCH_THRESHOLD_RX 128
744#define HAL_SRNG_INT_BATCH_THRESHOLD_OTHER 1
745
746/* Interrupt mitigation - timer threshold in us */
747#define HAL_SRNG_INT_TIMER_THRESHOLD_TX 1000
748#define HAL_SRNG_INT_TIMER_THRESHOLD_RX 500
749#define HAL_SRNG_INT_TIMER_THRESHOLD_OTHER 256

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808#define HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER BIT(2)
809#define HAL_REO_CMD_FLG_FLUSH_RELEASE_BLOCKING BIT(3)
810#define HAL_REO_CMD_FLG_FLUSH_NO_INVAL BIT(4)
811#define HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS BIT(5)
812#define HAL_REO_CMD_FLG_FLUSH_ALL BIT(6)
813#define HAL_REO_CMD_FLG_UNBLK_RESOURCE BIT(7)
814#define HAL_REO_CMD_FLG_UNBLK_CACHE BIT(8)
815
816/* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO0_UPD_* feilds */
816/* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO0_UPD_* fields */
817#define HAL_REO_CMD_UPD0_RX_QUEUE_NUM BIT(8)
818#define HAL_REO_CMD_UPD0_VLD BIT(9)
819#define HAL_REO_CMD_UPD0_ALDC BIT(10)
820#define HAL_REO_CMD_UPD0_DIS_DUP_DETECTION BIT(11)
821#define HAL_REO_CMD_UPD0_SOFT_REORDER_EN BIT(12)
822#define HAL_REO_CMD_UPD0_AC BIT(13)
823#define HAL_REO_CMD_UPD0_BAR BIT(14)
824#define HAL_REO_CMD_UPD0_RETRY BIT(15)

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833#define HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG BIT(24)
834#define HAL_REO_CMD_UPD0_SVLD BIT(25)
835#define HAL_REO_CMD_UPD0_SSN BIT(26)
836#define HAL_REO_CMD_UPD0_SEQ_2K_ERR BIT(27)
837#define HAL_REO_CMD_UPD0_PN_ERR BIT(28)
838#define HAL_REO_CMD_UPD0_PN_VALID BIT(29)
839#define HAL_REO_CMD_UPD0_PN BIT(30)
840
817#define HAL_REO_CMD_UPD0_RX_QUEUE_NUM BIT(8)
818#define HAL_REO_CMD_UPD0_VLD BIT(9)
819#define HAL_REO_CMD_UPD0_ALDC BIT(10)
820#define HAL_REO_CMD_UPD0_DIS_DUP_DETECTION BIT(11)
821#define HAL_REO_CMD_UPD0_SOFT_REORDER_EN BIT(12)
822#define HAL_REO_CMD_UPD0_AC BIT(13)
823#define HAL_REO_CMD_UPD0_BAR BIT(14)
824#define HAL_REO_CMD_UPD0_RETRY BIT(15)

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833#define HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG BIT(24)
834#define HAL_REO_CMD_UPD0_SVLD BIT(25)
835#define HAL_REO_CMD_UPD0_SSN BIT(26)
836#define HAL_REO_CMD_UPD0_SEQ_2K_ERR BIT(27)
837#define HAL_REO_CMD_UPD0_PN_ERR BIT(28)
838#define HAL_REO_CMD_UPD0_PN_VALID BIT(29)
839#define HAL_REO_CMD_UPD0_PN BIT(30)
840
841/* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO1_* feilds */
841/* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO1_* fields */
842#define HAL_REO_CMD_UPD1_VLD BIT(16)
843#define HAL_REO_CMD_UPD1_ALDC GENMASK(18, 17)
844#define HAL_REO_CMD_UPD1_DIS_DUP_DETECTION BIT(19)
845#define HAL_REO_CMD_UPD1_SOFT_REORDER_EN BIT(20)
846#define HAL_REO_CMD_UPD1_AC GENMASK(22, 21)
847#define HAL_REO_CMD_UPD1_BAR BIT(23)
848#define HAL_REO_CMD_UPD1_RETRY BIT(24)
849#define HAL_REO_CMD_UPD1_CHECK_2K_MODE BIT(25)
850#define HAL_REO_CMD_UPD1_OOR_MODE BIT(26)
851#define HAL_REO_CMD_UPD1_PN_CHECK BIT(27)
852#define HAL_REO_CMD_UPD1_EVEN_PN BIT(28)
853#define HAL_REO_CMD_UPD1_UNEVEN_PN BIT(29)
854#define HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE BIT(30)
855#define HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG BIT(31)
856
842#define HAL_REO_CMD_UPD1_VLD BIT(16)
843#define HAL_REO_CMD_UPD1_ALDC GENMASK(18, 17)
844#define HAL_REO_CMD_UPD1_DIS_DUP_DETECTION BIT(19)
845#define HAL_REO_CMD_UPD1_SOFT_REORDER_EN BIT(20)
846#define HAL_REO_CMD_UPD1_AC GENMASK(22, 21)
847#define HAL_REO_CMD_UPD1_BAR BIT(23)
848#define HAL_REO_CMD_UPD1_RETRY BIT(24)
849#define HAL_REO_CMD_UPD1_CHECK_2K_MODE BIT(25)
850#define HAL_REO_CMD_UPD1_OOR_MODE BIT(26)
851#define HAL_REO_CMD_UPD1_PN_CHECK BIT(27)
852#define HAL_REO_CMD_UPD1_EVEN_PN BIT(28)
853#define HAL_REO_CMD_UPD1_UNEVEN_PN BIT(29)
854#define HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE BIT(30)
855#define HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG BIT(31)
856
857/* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO2_* feilds */
857/* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO2_* fields */
858#define HAL_REO_CMD_UPD2_SVLD BIT(10)
859#define HAL_REO_CMD_UPD2_SSN GENMASK(22, 11)
860#define HAL_REO_CMD_UPD2_SEQ_2K_ERR BIT(23)
861#define HAL_REO_CMD_UPD2_PN_ERR BIT(24)
862
863struct ath12k_hal_reo_cmd {
864 u32 addr_lo;
865 u32 flag;

--- 277 unchanged lines hidden --- 		858#define HAL_REO_CMD_UPD2_SVLD BIT(10)
859#define HAL_REO_CMD_UPD2_SSN GENMASK(22, 11)
860#define HAL_REO_CMD_UPD2_SEQ_2K_ERR BIT(23)
861#define HAL_REO_CMD_UPD2_PN_ERR BIT(24)
862
863struct ath12k_hal_reo_cmd {
864 u32 addr_lo;
865 u32 flag;

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