national.c (b746a1a2860f4a918f32d10dc569115d282aaf2f) national.c (6571b4555dc94908f13d811898cddc5c0fa8bd71)
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * drivers/net/phy/national.c
4 *
5 * Driver for National Semiconductor PHYs
6 *
7 * Author: Stuart Menefy <stuart.menefy@st.com>
8 * Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>

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84
85 /* Clear the interrupt status bit by writing a “1”
86 * to the corresponding bit in INT_CLEAR (2:0 are reserved) */
87 ret = phy_write(phydev, DP83865_INT_CLEAR, ret & ~0x7);
88
89 return ret;
90}
91
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * drivers/net/phy/national.c
4 *
5 * Driver for National Semiconductor PHYs
6 *
7 * Author: Stuart Menefy <stuart.menefy@st.com>
8 * Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>

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84
85 /* Clear the interrupt status bit by writing a “1”
86 * to the corresponding bit in INT_CLEAR (2:0 are reserved) */
87 ret = phy_write(phydev, DP83865_INT_CLEAR, ret & ~0x7);
88
89 return ret;
90}
91
92static irqreturn_t ns_handle_interrupt(struct phy_device *phydev)
93{
94 int irq_status;
95
96 irq_status = phy_read(phydev, DP83865_INT_STATUS);
97 if (irq_status < 0) {
98 phy_error(phydev);
99 return IRQ_NONE;
100 }
101
102 if (!(irq_status & DP83865_INT_MASK_DEFAULT))
103 return IRQ_NONE;
104
105 /* clear the interrupt */
106 phy_write(phydev, DP83865_INT_CLEAR, irq_status & ~0x7);
107
108 phy_trigger_machine(phydev);
109
110 return IRQ_HANDLED;
111}
112
92static void ns_giga_speed_fallback(struct phy_device *phydev, int mode)
93{
94 int bmcr = phy_read(phydev, MII_BMCR);
95
96 phy_write(phydev, MII_BMCR, (bmcr | BMCR_PDOWN));
97
98 /* Enable 8 bit expended memory read/write (no auto increment) */
99 phy_write(phydev, NS_EXP_MEM_CTL, 0);

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130static struct phy_driver dp83865_driver[] = { {
131 .phy_id = DP83865_PHY_ID,
132 .phy_id_mask = 0xfffffff0,
133 .name = "NatSemi DP83865",
134 /* PHY_GBIT_FEATURES */
135 .config_init = ns_config_init,
136 .ack_interrupt = ns_ack_interrupt,
137 .config_intr = ns_config_intr,
113static void ns_giga_speed_fallback(struct phy_device *phydev, int mode)
114{
115 int bmcr = phy_read(phydev, MII_BMCR);
116
117 phy_write(phydev, MII_BMCR, (bmcr | BMCR_PDOWN));
118
119 /* Enable 8 bit expended memory read/write (no auto increment) */
120 phy_write(phydev, NS_EXP_MEM_CTL, 0);

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151static struct phy_driver dp83865_driver[] = { {
152 .phy_id = DP83865_PHY_ID,
153 .phy_id_mask = 0xfffffff0,
154 .name = "NatSemi DP83865",
155 /* PHY_GBIT_FEATURES */
156 .config_init = ns_config_init,
157 .ack_interrupt = ns_ack_interrupt,
158 .config_intr = ns_config_intr,
159 .handle_interrupt = ns_handle_interrupt,
138} };
139
140module_phy_driver(dp83865_driver);
141
142MODULE_DESCRIPTION("NatSemi PHY driver");
143MODULE_AUTHOR("Stuart Menefy");
144MODULE_LICENSE("GPL");
145
146static struct mdio_device_id __maybe_unused ns_tbl[] = {
147 { DP83865_PHY_ID, 0xfffffff0 },
148 { }
149};
150
151MODULE_DEVICE_TABLE(mdio, ns_tbl);
160} };
161
162module_phy_driver(dp83865_driver);
163
164MODULE_DESCRIPTION("NatSemi PHY driver");
165MODULE_AUTHOR("Stuart Menefy");
166MODULE_LICENSE("GPL");
167
168static struct mdio_device_id __maybe_unused ns_tbl[] = {
169 { DP83865_PHY_ID, 0xfffffff0 },
170 { }
171};
172
173MODULE_DEVICE_TABLE(mdio, ns_tbl);