micrel.c (6f84981772535e670e4e2df051a672af229b6694) micrel.c (a8f1a19d27ef9b13574195ae1571158529473541)
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * drivers/net/phy/micrel.c
4 *
5 * Driver for Micrel PHYs
6 *
7 * Author: David J. Choi
8 *

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263 { "phy_idle_errors", 10, 8 },
264};
265
266struct kszphy_type {
267 u32 led_mode_reg;
268 u16 interrupt_level_mask;
269 u16 cable_diag_reg;
270 unsigned long pair_mask;
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * drivers/net/phy/micrel.c
4 *
5 * Driver for Micrel PHYs
6 *
7 * Author: David J. Choi
8 *

--- 254 unchanged lines hidden (view full) ---

263 { "phy_idle_errors", 10, 8 },
264};
265
266struct kszphy_type {
267 u32 led_mode_reg;
268 u16 interrupt_level_mask;
269 u16 cable_diag_reg;
270 unsigned long pair_mask;
271 u16 disable_dll_tx_bit;
272 u16 disable_dll_rx_bit;
273 u16 disable_dll_mask;
271 bool has_broadcast_disable;
272 bool has_nand_tree_disable;
273 bool has_rmii_ref_clk_sel;
274};
275
276/* Shared structure between the PHYs of the same package. */
277struct lan8814_shared_priv {
278 struct phy_device *phydev;

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359static const struct kszphy_type ks8737_type = {
360 .interrupt_level_mask = BIT(14),
361};
362
363static const struct kszphy_type ksz9021_type = {
364 .interrupt_level_mask = BIT(14),
365};
366
274 bool has_broadcast_disable;
275 bool has_nand_tree_disable;
276 bool has_rmii_ref_clk_sel;
277};
278
279/* Shared structure between the PHYs of the same package. */
280struct lan8814_shared_priv {
281 struct phy_device *phydev;

--- 80 unchanged lines hidden (view full) ---

362static const struct kszphy_type ks8737_type = {
363 .interrupt_level_mask = BIT(14),
364};
365
366static const struct kszphy_type ksz9021_type = {
367 .interrupt_level_mask = BIT(14),
368};
369
370static const struct kszphy_type ksz9131_type = {
371 .interrupt_level_mask = BIT(14),
372 .disable_dll_tx_bit = BIT(12),
373 .disable_dll_rx_bit = BIT(12),
374 .disable_dll_mask = BIT_MASK(12),
375};
376
377static const struct kszphy_type lan8841_type = {
378 .disable_dll_tx_bit = BIT(14),
379 .disable_dll_rx_bit = BIT(14),
380 .disable_dll_mask = BIT_MASK(14),
381};
382
367static int kszphy_extended_write(struct phy_device *phydev,
368 u32 regnum, u16 val)
369{
370 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
371 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
372}
373
374static int kszphy_extended_read(struct phy_device *phydev,

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1167 }
1168
1169 return phy_write_mmd(phydev, 2, reg, newval);
1170}
1171
1172#define KSZ9131RN_MMD_COMMON_CTRL_REG 2
1173#define KSZ9131RN_RXC_DLL_CTRL 76
1174#define KSZ9131RN_TXC_DLL_CTRL 77
383static int kszphy_extended_write(struct phy_device *phydev,
384 u32 regnum, u16 val)
385{
386 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
387 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
388}
389
390static int kszphy_extended_read(struct phy_device *phydev,

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1183 }
1184
1185 return phy_write_mmd(phydev, 2, reg, newval);
1186}
1187
1188#define KSZ9131RN_MMD_COMMON_CTRL_REG 2
1189#define KSZ9131RN_RXC_DLL_CTRL 76
1190#define KSZ9131RN_TXC_DLL_CTRL 77
1175#define KSZ9131RN_DLL_CTRL_BYPASS BIT_MASK(12)
1176#define KSZ9131RN_DLL_ENABLE_DELAY 0
1191#define KSZ9131RN_DLL_ENABLE_DELAY 0
1177#define KSZ9131RN_DLL_DISABLE_DELAY BIT(12)
1178
1179static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
1180{
1192
1193static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
1194{
1195 const struct kszphy_type *type = phydev->drv->driver_data;
1181 u16 rxcdll_val, txcdll_val;
1182 int ret;
1183
1184 switch (phydev->interface) {
1185 case PHY_INTERFACE_MODE_RGMII:
1196 u16 rxcdll_val, txcdll_val;
1197 int ret;
1198
1199 switch (phydev->interface) {
1200 case PHY_INTERFACE_MODE_RGMII:
1186 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
1187 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
1201 rxcdll_val = type->disable_dll_rx_bit;
1202 txcdll_val = type->disable_dll_tx_bit;
1188 break;
1189 case PHY_INTERFACE_MODE_RGMII_ID:
1190 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1191 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1192 break;
1193 case PHY_INTERFACE_MODE_RGMII_RXID:
1194 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1203 break;
1204 case PHY_INTERFACE_MODE_RGMII_ID:
1205 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1206 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1207 break;
1208 case PHY_INTERFACE_MODE_RGMII_RXID:
1209 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1195 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
1210 txcdll_val = type->disable_dll_tx_bit;
1196 break;
1197 case PHY_INTERFACE_MODE_RGMII_TXID:
1211 break;
1212 case PHY_INTERFACE_MODE_RGMII_TXID:
1198 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
1213 rxcdll_val = type->disable_dll_rx_bit;
1199 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1200 break;
1201 default:
1202 return 0;
1203 }
1204
1205 ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1214 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1215 break;
1216 default:
1217 return 0;
1218 }
1219
1220 ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1206 KSZ9131RN_RXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
1221 KSZ9131RN_RXC_DLL_CTRL, type->disable_dll_mask,
1207 rxcdll_val);
1208 if (ret < 0)
1209 return ret;
1210
1211 return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1222 rxcdll_val);
1223 if (ret < 0)
1224 return ret;
1225
1226 return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1212 KSZ9131RN_TXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
1227 KSZ9131RN_TXC_DLL_CTRL, type->disable_dll_mask,
1213 txcdll_val);
1214}
1215
1216/* Silicon Errata DS80000693B
1217 *
1218 * When LEDs are configured in Individual Mode, LED1 is ON in a no-link
1219 * condition. Workaround is to set register 0x1e, bit 9, this way LED1 behaves
1220 * according to the datasheet (off if there is no link).

--- 862 unchanged lines hidden (view full) ---

2083}
2084
2085static int ksz886x_cable_test_get_status(struct phy_device *phydev,
2086 bool *finished)
2087{
2088 const struct kszphy_type *type = phydev->drv->driver_data;
2089 unsigned long pair_mask = type->pair_mask;
2090 int retries = 20;
1228 txcdll_val);
1229}
1230
1231/* Silicon Errata DS80000693B
1232 *
1233 * When LEDs are configured in Individual Mode, LED1 is ON in a no-link
1234 * condition. Workaround is to set register 0x1e, bit 9, this way LED1 behaves
1235 * according to the datasheet (off if there is no link).

--- 862 unchanged lines hidden (view full) ---

2098}
2099
2100static int ksz886x_cable_test_get_status(struct phy_device *phydev,
2101 bool *finished)
2102{
2103 const struct kszphy_type *type = phydev->drv->driver_data;
2104 unsigned long pair_mask = type->pair_mask;
2105 int retries = 20;
2091 int pair, ret;
2106 int ret = 0;
2107 int pair;
2092
2093 *finished = false;
2094
2095 /* Try harder if link partner is active */
2096 while (pair_mask && retries--) {
2097 for_each_set_bit(pair, &pair_mask, 4) {
2098 if (type->cable_diag_reg == LAN8814_CABLE_DIAG)
2099 ret = lan8814_cable_test_one_pair(phydev, pair);

--- 689 unchanged lines hidden (view full) ---

2789
2790 /* If other timestamps are available in the FIFO,
2791 * process them.
2792 */
2793 reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
2794 } while (PTP_CAP_INFO_RX_TS_CNT_GET_(reg) > 0);
2795}
2796
2108
2109 *finished = false;
2110
2111 /* Try harder if link partner is active */
2112 while (pair_mask && retries--) {
2113 for_each_set_bit(pair, &pair_mask, 4) {
2114 if (type->cable_diag_reg == LAN8814_CABLE_DIAG)
2115 ret = lan8814_cable_test_one_pair(phydev, pair);

--- 689 unchanged lines hidden (view full) ---

2805
2806 /* If other timestamps are available in the FIFO,
2807 * process them.
2808 */
2809 reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
2810 } while (PTP_CAP_INFO_RX_TS_CNT_GET_(reg) > 0);
2811}
2812
2797static void lan8814_handle_ptp_interrupt(struct phy_device *phydev)
2813static void lan8814_handle_ptp_interrupt(struct phy_device *phydev, u16 status)
2798{
2799 struct kszphy_priv *priv = phydev->priv;
2800 struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
2814{
2815 struct kszphy_priv *priv = phydev->priv;
2816 struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
2801 u16 status;
2802
2817
2803 status = lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
2804 if (status & PTP_TSU_INT_STS_PTP_TX_TS_EN_)
2805 lan8814_get_tx_ts(ptp_priv);
2806
2807 if (status & PTP_TSU_INT_STS_PTP_RX_TS_EN_)
2808 lan8814_get_rx_ts(ptp_priv);
2809
2810 if (status & PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_) {
2811 lan8814_flush_fifo(phydev, true);

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2894 return err;
2895 }
2896
2897 return 0;
2898}
2899
2900static irqreturn_t lan8814_handle_interrupt(struct phy_device *phydev)
2901{
2818 if (status & PTP_TSU_INT_STS_PTP_TX_TS_EN_)
2819 lan8814_get_tx_ts(ptp_priv);
2820
2821 if (status & PTP_TSU_INT_STS_PTP_RX_TS_EN_)
2822 lan8814_get_rx_ts(ptp_priv);
2823
2824 if (status & PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_) {
2825 lan8814_flush_fifo(phydev, true);

--- 82 unchanged lines hidden (view full) ---

2908 return err;
2909 }
2910
2911 return 0;
2912}
2913
2914static irqreturn_t lan8814_handle_interrupt(struct phy_device *phydev)
2915{
2902 int irq_status, tsu_irq_status;
2903 int ret = IRQ_NONE;
2916 int ret = IRQ_NONE;
2917 int irq_status;
2904
2905 irq_status = phy_read(phydev, LAN8814_INTS);
2906 if (irq_status < 0) {
2907 phy_error(phydev);
2908 return IRQ_NONE;
2909 }
2910
2911 if (irq_status & LAN8814_INT_LINK) {
2912 phy_trigger_machine(phydev);
2913 ret = IRQ_HANDLED;
2914 }
2915
2918
2919 irq_status = phy_read(phydev, LAN8814_INTS);
2920 if (irq_status < 0) {
2921 phy_error(phydev);
2922 return IRQ_NONE;
2923 }
2924
2925 if (irq_status & LAN8814_INT_LINK) {
2926 phy_trigger_machine(phydev);
2927 ret = IRQ_HANDLED;
2928 }
2929
2916 while (1) {
2917 tsu_irq_status = lanphy_read_page_reg(phydev, 4,
2918 LAN8814_INTR_STS_REG);
2919
2920 if (tsu_irq_status > 0 &&
2921 (tsu_irq_status & (LAN8814_INTR_STS_REG_1588_TSU0_ |
2922 LAN8814_INTR_STS_REG_1588_TSU1_ |
2923 LAN8814_INTR_STS_REG_1588_TSU2_ |
2924 LAN8814_INTR_STS_REG_1588_TSU3_))) {
2925 lan8814_handle_ptp_interrupt(phydev);
2926 ret = IRQ_HANDLED;
2927 } else {
2930 while (true) {
2931 irq_status = lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
2932 if (!irq_status)
2928 break;
2933 break;
2929 }
2934
2935 lan8814_handle_ptp_interrupt(phydev, irq_status);
2936 ret = IRQ_HANDLED;
2930 }
2931
2932 return ret;
2933}
2934
2935static int lan8814_ack_interrupt(struct phy_device *phydev)
2936{
2937 /* bit[12..0] int status, which is a read and clear register. */

--- 73 unchanged lines hidden (view full) ---

3011
3012 phydev->mii_ts = &ptp_priv->mii_ts;
3013}
3014
3015static int lan8814_ptp_probe_once(struct phy_device *phydev)
3016{
3017 struct lan8814_shared_priv *shared = phydev->shared->priv;
3018
2937 }
2938
2939 return ret;
2940}
2941
2942static int lan8814_ack_interrupt(struct phy_device *phydev)
2943{
2944 /* bit[12..0] int status, which is a read and clear register. */

--- 73 unchanged lines hidden (view full) ---

3018
3019 phydev->mii_ts = &ptp_priv->mii_ts;
3020}
3021
3022static int lan8814_ptp_probe_once(struct phy_device *phydev)
3023{
3024 struct lan8814_shared_priv *shared = phydev->shared->priv;
3025
3019 if (!IS_ENABLED(CONFIG_PTP_1588_CLOCK) ||
3020 !IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))
3021 return 0;
3022
3023 /* Initialise shared lock for clock*/
3024 mutex_init(&shared->shared_lock);
3025
3026 shared->ptp_clock_info.owner = THIS_MODULE;
3027 snprintf(shared->ptp_clock_info.name, 30, "%s", phydev->drv->name);
3028 shared->ptp_clock_info.max_adj = 31249999;
3029 shared->ptp_clock_info.n_alarm = 0;
3030 shared->ptp_clock_info.n_ext_ts = 0;
3031 shared->ptp_clock_info.n_pins = 0;
3032 shared->ptp_clock_info.pps = 0;
3033 shared->ptp_clock_info.pin_config = NULL;
3034 shared->ptp_clock_info.adjfine = lan8814_ptpci_adjfine;
3035 shared->ptp_clock_info.adjtime = lan8814_ptpci_adjtime;
3036 shared->ptp_clock_info.gettime64 = lan8814_ptpci_gettime64;
3037 shared->ptp_clock_info.settime64 = lan8814_ptpci_settime64;
3038 shared->ptp_clock_info.getcrosststamp = NULL;
3039
3040 shared->ptp_clock = ptp_clock_register(&shared->ptp_clock_info,
3041 &phydev->mdio.dev);
3026 /* Initialise shared lock for clock*/
3027 mutex_init(&shared->shared_lock);
3028
3029 shared->ptp_clock_info.owner = THIS_MODULE;
3030 snprintf(shared->ptp_clock_info.name, 30, "%s", phydev->drv->name);
3031 shared->ptp_clock_info.max_adj = 31249999;
3032 shared->ptp_clock_info.n_alarm = 0;
3033 shared->ptp_clock_info.n_ext_ts = 0;
3034 shared->ptp_clock_info.n_pins = 0;
3035 shared->ptp_clock_info.pps = 0;
3036 shared->ptp_clock_info.pin_config = NULL;
3037 shared->ptp_clock_info.adjfine = lan8814_ptpci_adjfine;
3038 shared->ptp_clock_info.adjtime = lan8814_ptpci_adjtime;
3039 shared->ptp_clock_info.gettime64 = lan8814_ptpci_gettime64;
3040 shared->ptp_clock_info.settime64 = lan8814_ptpci_settime64;
3041 shared->ptp_clock_info.getcrosststamp = NULL;
3042
3043 shared->ptp_clock = ptp_clock_register(&shared->ptp_clock_info,
3044 &phydev->mdio.dev);
3042 if (IS_ERR_OR_NULL(shared->ptp_clock)) {
3045 if (IS_ERR(shared->ptp_clock)) {
3043 phydev_err(phydev, "ptp_clock_register failed %lu\n",
3044 PTR_ERR(shared->ptp_clock));
3045 return -EINVAL;
3046 }
3047
3046 phydev_err(phydev, "ptp_clock_register failed %lu\n",
3047 PTR_ERR(shared->ptp_clock));
3048 return -EINVAL;
3049 }
3050
3051 /* Check if PHC support is missing at the configuration level */
3052 if (!shared->ptp_clock)
3053 return 0;
3054
3048 phydev_dbg(phydev, "successfully registered ptp clock\n");
3049
3050 shared->phydev = phydev;
3051
3052 /* The EP.4 is shared between all the PHYs in the package and also it
3053 * can be accessed by any of the PHYs
3054 */
3055 lanphy_write_page_reg(phydev, 4, LTC_HARD_RESET, LTC_HARD_RESET_);

--- 99 unchanged lines hidden (view full) ---

3155 return err;
3156 }
3157
3158 lan8814_ptp_init(phydev);
3159
3160 return 0;
3161}
3162
3055 phydev_dbg(phydev, "successfully registered ptp clock\n");
3056
3057 shared->phydev = phydev;
3058
3059 /* The EP.4 is shared between all the PHYs in the package and also it
3060 * can be accessed by any of the PHYs
3061 */
3062 lanphy_write_page_reg(phydev, 4, LTC_HARD_RESET, LTC_HARD_RESET_);

--- 99 unchanged lines hidden (view full) ---

3162 return err;
3163 }
3164
3165 lan8814_ptp_init(phydev);
3166
3167 return 0;
3168}
3169
3170#define LAN8841_MMD_TIMER_REG 0
3171#define LAN8841_MMD0_REGISTER_17 17
3172#define LAN8841_MMD0_REGISTER_17_DROP_OPT(x) ((x) & 0x3)
3173#define LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS BIT(3)
3174#define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG 2
3175#define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK BIT(14)
3176#define LAN8841_MMD_ANALOG_REG 28
3177#define LAN8841_ANALOG_CONTROL_1 1
3178#define LAN8841_ANALOG_CONTROL_1_PLL_TRIM(x) (((x) & 0x3) << 5)
3179#define LAN8841_ANALOG_CONTROL_10 13
3180#define LAN8841_ANALOG_CONTROL_10_PLL_DIV(x) ((x) & 0x3)
3181#define LAN8841_ANALOG_CONTROL_11 14
3182#define LAN8841_ANALOG_CONTROL_11_LDO_REF(x) (((x) & 0x7) << 12)
3183#define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT 69
3184#define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL 0xbffc
3185#define LAN8841_BTRX_POWER_DOWN 70
3186#define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A BIT(0)
3187#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_A BIT(1)
3188#define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B BIT(2)
3189#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_B BIT(3)
3190#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_C BIT(5)
3191#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_D BIT(7)
3192#define LAN8841_ADC_CHANNEL_MASK 198
3193
3194static int lan8841_config_init(struct phy_device *phydev)
3195{
3196 int ret;
3197
3198 ret = ksz9131_config_init(phydev);
3199 if (ret)
3200 return ret;
3201
3202 /* 100BT Clause 40 improvenent errata */
3203 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3204 LAN8841_ANALOG_CONTROL_1,
3205 LAN8841_ANALOG_CONTROL_1_PLL_TRIM(0x2));
3206 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3207 LAN8841_ANALOG_CONTROL_10,
3208 LAN8841_ANALOG_CONTROL_10_PLL_DIV(0x1));
3209
3210 /* 10M/100M Ethernet Signal Tuning Errata for Shorted-Center Tap
3211 * Magnetics
3212 */
3213 ret = phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3214 LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG);
3215 if (ret & LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK) {
3216 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3217 LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT,
3218 LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL);
3219 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3220 LAN8841_BTRX_POWER_DOWN,
3221 LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A |
3222 LAN8841_BTRX_POWER_DOWN_BTRX_CH_A |
3223 LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B |
3224 LAN8841_BTRX_POWER_DOWN_BTRX_CH_B |
3225 LAN8841_BTRX_POWER_DOWN_BTRX_CH_C |
3226 LAN8841_BTRX_POWER_DOWN_BTRX_CH_D);
3227 }
3228
3229 /* LDO Adjustment errata */
3230 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3231 LAN8841_ANALOG_CONTROL_11,
3232 LAN8841_ANALOG_CONTROL_11_LDO_REF(1));
3233
3234 /* 100BT RGMII latency tuning errata */
3235 phy_write_mmd(phydev, MDIO_MMD_PMAPMD,
3236 LAN8841_ADC_CHANNEL_MASK, 0x0);
3237 phy_write_mmd(phydev, LAN8841_MMD_TIMER_REG,
3238 LAN8841_MMD0_REGISTER_17,
3239 LAN8841_MMD0_REGISTER_17_DROP_OPT(2) |
3240 LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS);
3241
3242 return 0;
3243}
3244
3245#define LAN8841_OUTPUT_CTRL 25
3246#define LAN8841_OUTPUT_CTRL_INT_BUFFER BIT(14)
3247
3248static int lan8841_config_intr(struct phy_device *phydev)
3249{
3250 int err;
3251
3252 phy_modify(phydev, LAN8841_OUTPUT_CTRL,
3253 LAN8841_OUTPUT_CTRL_INT_BUFFER, 0);
3254
3255 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
3256 err = phy_read(phydev, LAN8814_INTS);
3257 if (err)
3258 return err;
3259
3260 err = phy_write(phydev, LAN8814_INTC,
3261 LAN8814_INT_LINK);
3262 } else {
3263 err = phy_write(phydev, LAN8814_INTC, 0);
3264 if (err)
3265 return err;
3266
3267 err = phy_read(phydev, LAN8814_INTS);
3268 }
3269
3270 return err;
3271}
3272
3273static irqreturn_t lan8841_handle_interrupt(struct phy_device *phydev)
3274{
3275 int irq_status;
3276
3277 irq_status = phy_read(phydev, LAN8814_INTS);
3278 if (irq_status < 0) {
3279 phy_error(phydev);
3280 return IRQ_NONE;
3281 }
3282
3283 if (irq_status & LAN8814_INT_LINK) {
3284 phy_trigger_machine(phydev);
3285 return IRQ_HANDLED;
3286 }
3287
3288 return IRQ_NONE;
3289}
3290
3291#define LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER 3
3292#define LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER_STRAP_RGMII_EN BIT(0)
3293
3294static int lan8841_probe(struct phy_device *phydev)
3295{
3296 int err;
3297
3298 err = kszphy_probe(phydev);
3299 if (err)
3300 return err;
3301
3302 if (phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3303 LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER) &
3304 LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER_STRAP_RGMII_EN)
3305 phydev->interface = PHY_INTERFACE_MODE_RGMII_RXID;
3306
3307 return 0;
3308}
3309
3163static struct phy_driver ksphy_driver[] = {
3164{
3165 .phy_id = PHY_ID_KS8737,
3166 .phy_id_mask = MICREL_PHY_ID_MASK,
3167 .name = "Micrel KS8737",
3168 /* PHY_BASIC_FEATURES */
3169 .driver_data = &ks8737_type,
3170 .probe = kszphy_probe,

--- 194 unchanged lines hidden (view full) ---

3365 .get_sset_count = kszphy_get_sset_count,
3366 .get_strings = kszphy_get_strings,
3367 .get_stats = kszphy_get_stats,
3368 .suspend = genphy_suspend,
3369 .resume = kszphy_resume,
3370 .config_intr = lan8804_config_intr,
3371 .handle_interrupt = lan8804_handle_interrupt,
3372}, {
3310static struct phy_driver ksphy_driver[] = {
3311{
3312 .phy_id = PHY_ID_KS8737,
3313 .phy_id_mask = MICREL_PHY_ID_MASK,
3314 .name = "Micrel KS8737",
3315 /* PHY_BASIC_FEATURES */
3316 .driver_data = &ks8737_type,
3317 .probe = kszphy_probe,

--- 194 unchanged lines hidden (view full) ---

3512 .get_sset_count = kszphy_get_sset_count,
3513 .get_strings = kszphy_get_strings,
3514 .get_stats = kszphy_get_stats,
3515 .suspend = genphy_suspend,
3516 .resume = kszphy_resume,
3517 .config_intr = lan8804_config_intr,
3518 .handle_interrupt = lan8804_handle_interrupt,
3519}, {
3520 .phy_id = PHY_ID_LAN8841,
3521 .phy_id_mask = MICREL_PHY_ID_MASK,
3522 .name = "Microchip LAN8841 Gigabit PHY",
3523 .driver_data = &lan8841_type,
3524 .config_init = lan8841_config_init,
3525 .probe = lan8841_probe,
3526 .soft_reset = genphy_soft_reset,
3527 .config_intr = lan8841_config_intr,
3528 .handle_interrupt = lan8841_handle_interrupt,
3529 .get_sset_count = kszphy_get_sset_count,
3530 .get_strings = kszphy_get_strings,
3531 .get_stats = kszphy_get_stats,
3532 .suspend = genphy_suspend,
3533 .resume = genphy_resume,
3534}, {
3373 .phy_id = PHY_ID_KSZ9131,
3374 .phy_id_mask = MICREL_PHY_ID_MASK,
3375 .name = "Microchip KSZ9131 Gigabit PHY",
3376 /* PHY_GBIT_FEATURES */
3377 .flags = PHY_POLL_CABLE_TEST,
3535 .phy_id = PHY_ID_KSZ9131,
3536 .phy_id_mask = MICREL_PHY_ID_MASK,
3537 .name = "Microchip KSZ9131 Gigabit PHY",
3538 /* PHY_GBIT_FEATURES */
3539 .flags = PHY_POLL_CABLE_TEST,
3378 .driver_data = &ksz9021_type,
3540 .driver_data = &ksz9131_type,
3379 .probe = kszphy_probe,
3380 .config_init = ksz9131_config_init,
3381 .config_intr = kszphy_config_intr,
3382 .config_aneg = ksz9131_config_aneg,
3383 .read_status = ksz9131_read_status,
3384 .handle_interrupt = kszphy_handle_interrupt,
3385 .get_sset_count = kszphy_get_sset_count,
3386 .get_strings = kszphy_get_strings,

--- 62 unchanged lines hidden (view full) ---

3449 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
3450 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
3451 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
3452 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
3453 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
3454 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
3455 { PHY_ID_LAN8814, MICREL_PHY_ID_MASK },
3456 { PHY_ID_LAN8804, MICREL_PHY_ID_MASK },
3541 .probe = kszphy_probe,
3542 .config_init = ksz9131_config_init,
3543 .config_intr = kszphy_config_intr,
3544 .config_aneg = ksz9131_config_aneg,
3545 .read_status = ksz9131_read_status,
3546 .handle_interrupt = kszphy_handle_interrupt,
3547 .get_sset_count = kszphy_get_sset_count,
3548 .get_strings = kszphy_get_strings,

--- 62 unchanged lines hidden (view full) ---

3611 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
3612 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
3613 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
3614 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
3615 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
3616 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
3617 { PHY_ID_LAN8814, MICREL_PHY_ID_MASK },
3618 { PHY_ID_LAN8804, MICREL_PHY_ID_MASK },
3619 { PHY_ID_LAN8841, MICREL_PHY_ID_MASK },
3457 { }
3458};
3459
3460MODULE_DEVICE_TABLE(mdio, micrel_tbl);
3620 { }
3621};
3622
3623MODULE_DEVICE_TABLE(mdio, micrel_tbl);