marvell10g.c (07fa3fa2572f2dee85beb8137f90ccf33d7206af) marvell10g.c (3c1bcc8614db10803f1f57ef0295363917448cb2)
1/*
2 * Marvell 10G 88x3310 PHY driver
3 *
4 * Based upon the ID registers, this PHY appears to be a mixture of IPs
5 * from two different companies.
6 *
7 * There appears to be several different data paths through the PHY which
8 * are automatically managed by the PHY. The following has been determined

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247static int mv3310_resume(struct phy_device *phydev)
248{
249 return mv3310_hwmon_config(phydev, true);
250}
251
252static int mv3310_config_init(struct phy_device *phydev)
253{
254 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
1/*
2 * Marvell 10G 88x3310 PHY driver
3 *
4 * Based upon the ID registers, this PHY appears to be a mixture of IPs
5 * from two different companies.
6 *
7 * There appears to be several different data paths through the PHY which
8 * are automatically managed by the PHY. The following has been determined

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247static int mv3310_resume(struct phy_device *phydev)
248{
249 return mv3310_hwmon_config(phydev, true);
250}
251
252static int mv3310_config_init(struct phy_device *phydev)
253{
254 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
255 u32 mask;
256 int val;
257
258 /* Check that the PHY interface type is compatible */
259 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
260 phydev->interface != PHY_INTERFACE_MODE_XAUI &&
261 phydev->interface != PHY_INTERFACE_MODE_RXAUI &&
262 phydev->interface != PHY_INTERFACE_MODE_10GKR)
263 return -ENODEV;

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331 if (val & MDIO_PMA_EXTABLE_10BT) {
332 __set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
333 supported);
334 __set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
335 supported);
336 }
337 }
338
255 int val;
256
257 /* Check that the PHY interface type is compatible */
258 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
259 phydev->interface != PHY_INTERFACE_MODE_XAUI &&
260 phydev->interface != PHY_INTERFACE_MODE_RXAUI &&
261 phydev->interface != PHY_INTERFACE_MODE_10GKR)
262 return -ENODEV;

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330 if (val & MDIO_PMA_EXTABLE_10BT) {
331 __set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
332 supported);
333 __set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
334 supported);
335 }
336 }
337
339 if (!ethtool_convert_link_mode_to_legacy_u32(&mask, supported))
340 phydev_warn(phydev,
341 "PHY supports (%*pb) more modes than phylib supports, some modes not supported.\n",
342 __ETHTOOL_LINK_MODE_MASK_NBITS, supported);
338 linkmode_copy(phydev->supported, supported);
339 linkmode_and(phydev->advertising, phydev->advertising,
340 phydev->supported);
343
341
344 phydev->supported &= mask;
345 phydev->advertising &= phydev->supported;
346
347 return 0;
348}
349
350static int mv3310_config_aneg(struct phy_device *phydev)
351{
352 bool changed = false;
342 return 0;
343}
344
345static int mv3310_config_aneg(struct phy_device *phydev)
346{
347 bool changed = false;
353 u32 advertising;
348 u16 reg;
354 int ret;
355
356 /* We don't support manual MDI control */
357 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
358
359 if (phydev->autoneg == AUTONEG_DISABLE) {
360 ret = genphy_c45_pma_setup_forced(phydev);
361 if (ret < 0)
362 return ret;
363
364 return genphy_c45_an_disable_aneg(phydev);
365 }
366
349 int ret;
350
351 /* We don't support manual MDI control */
352 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
353
354 if (phydev->autoneg == AUTONEG_DISABLE) {
355 ret = genphy_c45_pma_setup_forced(phydev);
356 if (ret < 0)
357 return ret;
358
359 return genphy_c45_an_disable_aneg(phydev);
360 }
361
367 phydev->advertising &= phydev->supported;
368 advertising = phydev->advertising;
362 linkmode_and(phydev->advertising, phydev->advertising,
363 phydev->supported);
369
370 ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
371 ADVERTISE_ALL | ADVERTISE_100BASE4 |
372 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
364
365 ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
366 ADVERTISE_ALL | ADVERTISE_100BASE4 |
367 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
373 ethtool_adv_to_mii_adv_t(advertising));
368 linkmode_adv_to_mii_adv_t(phydev->advertising));
374 if (ret < 0)
375 return ret;
376 if (ret > 0)
377 changed = true;
378
369 if (ret < 0)
370 return ret;
371 if (ret > 0)
372 changed = true;
373
374 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
379 ret = mv3310_modify(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,
375 ret = mv3310_modify(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,
380 ADVERTISE_1000FULL | ADVERTISE_1000HALF,
381 ethtool_adv_to_mii_ctrl1000_t(advertising));
376 ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg);
382 if (ret < 0)
383 return ret;
384 if (ret > 0)
385 changed = true;
386
387 /* 10G control register */
377 if (ret < 0)
378 return ret;
379 if (ret > 0)
380 changed = true;
381
382 /* 10G control register */
383 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
384 phydev->advertising))
385 reg = MDIO_AN_10GBT_CTRL_ADV10G;
386 else
387 reg = 0;
388
388 ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
389 ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
389 MDIO_AN_10GBT_CTRL_ADV10G,
390 advertising & ADVERTISED_10000baseT_Full ?
391 MDIO_AN_10GBT_CTRL_ADV10G : 0);
390 MDIO_AN_10GBT_CTRL_ADV10G, reg);
392 if (ret < 0)
393 return ret;
394 if (ret > 0)
395 changed = true;
396
397 if (changed)
398 ret = genphy_c45_restart_aneg(phydev);
399

--- 159 unchanged lines hidden --- 		391 if (ret < 0)
392 return ret;
393 if (ret > 0)
394 changed = true;
395
396 if (changed)
397 ret = genphy_c45_restart_aneg(phydev);
398

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