bcm63xx.c (d79e26a7efc22c4cc2cd66529cc3bd4e0ed5938a) bcm63xx.c (3c1bcc8614db10803f1f57ef0295363917448cb2)
1/*
2 * Driver for Broadcom 63xx SOCs integrated PHYs
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */

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38 return err;
39}
40
41static int bcm63xx_config_init(struct phy_device *phydev)
42{
43 int reg, err;
44
45 /* ASYM_PAUSE bit is marked RO in datasheet, so don't cheat */
1/*
2 * Driver for Broadcom 63xx SOCs integrated PHYs
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */

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38 return err;
39}
40
41static int bcm63xx_config_init(struct phy_device *phydev)
42{
43 int reg, err;
44
45 /* ASYM_PAUSE bit is marked RO in datasheet, so don't cheat */
46 phydev->supported |= SUPPORTED_Pause;
46 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
47
48 reg = phy_read(phydev, MII_BCM63XX_IR);
49 if (reg < 0)
50 return reg;
51
52 /* Mask interrupts globally. */
53 reg |= MII_BCM63XX_IR_GMASK;
54 err = phy_write(phydev, MII_BCM63XX_IR, reg);

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48 reg = phy_read(phydev, MII_BCM63XX_IR);
49 if (reg < 0)
50 return reg;
51
52 /* Mask interrupts globally. */
53 reg |= MII_BCM63XX_IR_GMASK;
54 err = phy_write(phydev, MII_BCM63XX_IR, reg);

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