ocelot.h (860dbce3d8dd90cb9e909c58fa79808766243651) ocelot.h (b596229448dd2a263cdc4906e60b1b2249777ee4)
1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2/*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7
8#ifndef _MSCC_OCELOT_H_

--- 8 unchanged lines hidden (view full) ---

17#include <linux/regmap.h>
18
19#include "ocelot_ana.h"
20#include "ocelot_dev.h"
21#include "ocelot_qsys.h"
22#include "ocelot_rew.h"
23#include "ocelot_sys.h"
24#include "ocelot_qs.h"
1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2/*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7
8#ifndef _MSCC_OCELOT_H_

--- 8 unchanged lines hidden (view full) ---

17#include <linux/regmap.h>
18
19#include "ocelot_ana.h"
20#include "ocelot_dev.h"
21#include "ocelot_qsys.h"
22#include "ocelot_rew.h"
23#include "ocelot_sys.h"
24#include "ocelot_qs.h"
25#include "ocelot_tc.h"
25
26#define PGID_AGGR 64
27#define PGID_SRC 80
28
29/* Reserved PGIDs */
30#define PGID_CPU (PGID_AGGR - 5)
31#define PGID_UC (PGID_AGGR - 4)
32#define PGID_MC (PGID_AGGR - 3)

--- 30 unchanged lines hidden (view full) ---

63#define REG(reg, offset) [reg & REG_MASK] = offset
64
65enum ocelot_target {
66 ANA = 1,
67 QS,
68 QSYS,
69 REW,
70 SYS,
26
27#define PGID_AGGR 64
28#define PGID_SRC 80
29
30/* Reserved PGIDs */
31#define PGID_CPU (PGID_AGGR - 5)
32#define PGID_UC (PGID_AGGR - 4)
33#define PGID_MC (PGID_AGGR - 3)

--- 30 unchanged lines hidden (view full) ---

64#define REG(reg, offset) [reg & REG_MASK] = offset
65
66enum ocelot_target {
67 ANA = 1,
68 QS,
69 QSYS,
70 REW,
71 SYS,
72 S2,
71 HSIO,
72 TARGET_MAX,
73};
74
75enum ocelot_reg {
76 ANA_ADVLEARN = ANA << TARGET_OFFSET,
77 ANA_VLANMASK,
78 ANA_PORT_B_DOMAIN,

--- 250 unchanged lines hidden (view full) ---

329 SYS_PTP_NXT,
330 SYS_PTP_CFG,
331 SYS_RAM_INIT,
332 SYS_CM_ADDR,
333 SYS_CM_DATA_WR,
334 SYS_CM_DATA_RD,
335 SYS_CM_OP,
336 SYS_CM_DATA,
73 HSIO,
74 TARGET_MAX,
75};
76
77enum ocelot_reg {
78 ANA_ADVLEARN = ANA << TARGET_OFFSET,
79 ANA_VLANMASK,
80 ANA_PORT_B_DOMAIN,

--- 250 unchanged lines hidden (view full) ---

331 SYS_PTP_NXT,
332 SYS_PTP_CFG,
333 SYS_RAM_INIT,
334 SYS_CM_ADDR,
335 SYS_CM_DATA_WR,
336 SYS_CM_DATA_RD,
337 SYS_CM_OP,
338 SYS_CM_DATA,
339 S2_CORE_UPDATE_CTRL = S2 << TARGET_OFFSET,
340 S2_CORE_MV_CFG,
341 S2_CACHE_ENTRY_DAT,
342 S2_CACHE_MASK_DAT,
343 S2_CACHE_ACTION_DAT,
344 S2_CACHE_CNT_DAT,
345 S2_CACHE_TG_DAT,
337};
338
339enum ocelot_regfield {
340 ANA_ADVLEARN_VLAN_CHK,
341 ANA_ADVLEARN_LEARN_MIRROR,
342 ANA_ANEVENTS_FLOOD_DISCARD,
343 ANA_ANEVENTS_MSTI_DROP,
344 ANA_ANEVENTS_ACLKILL,

--- 104 unchanged lines hidden (view full) ---

449 u16 vid;
450
451 u8 vlan_aware;
452
453 u64 *stats;
454
455 phy_interface_t phy_mode;
456 struct phy *serdes;
346};
347
348enum ocelot_regfield {
349 ANA_ADVLEARN_VLAN_CHK,
350 ANA_ADVLEARN_LEARN_MIRROR,
351 ANA_ANEVENTS_FLOOD_DISCARD,
352 ANA_ANEVENTS_MSTI_DROP,
353 ANA_ANEVENTS_ACLKILL,

--- 104 unchanged lines hidden (view full) ---

458 u16 vid;
459
460 u8 vlan_aware;
461
462 u64 *stats;
463
464 phy_interface_t phy_mode;
465 struct phy *serdes;
466
467 struct ocelot_port_tc tc;
457};
458
459u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset);
460#define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
461#define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
462#define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
463#define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0)
464

--- 37 unchanged lines hidden --- 		468};
469
470u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset);
471#define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
472#define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
473#define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
474#define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0)
475

--- 37 unchanged lines hidden ---