ocelot.h (40a1578d631a8ac1cf0ef797c435114107747859) ocelot.h (2c1d029a017f23e912f5d549ad8a2d84428a5017)
1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2/*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7
8#ifndef _MSCC_OCELOT_H_

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17#include <linux/regmap.h>
18
19#include "ocelot_ana.h"
20#include "ocelot_dev.h"
21#include "ocelot_qsys.h"
22#include "ocelot_rew.h"
23#include "ocelot_sys.h"
24#include "ocelot_qs.h"
1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2/*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7
8#ifndef _MSCC_OCELOT_H_

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17#include <linux/regmap.h>
18
19#include "ocelot_ana.h"
20#include "ocelot_dev.h"
21#include "ocelot_qsys.h"
22#include "ocelot_rew.h"
23#include "ocelot_sys.h"
24#include "ocelot_qs.h"
25#include "ocelot_tc.h"
25
26#define PGID_AGGR 64
27#define PGID_SRC 80
28
29/* Reserved PGIDs */
30#define PGID_CPU (PGID_AGGR - 5)
31#define PGID_UC (PGID_AGGR - 4)
32#define PGID_MC (PGID_AGGR - 3)

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436};
437
438struct ocelot_port {
439 struct net_device *dev;
440 struct ocelot *ocelot;
441 struct phy_device *phy;
442 void __iomem *regs;
443 u8 chip_port;
26
27#define PGID_AGGR 64
28#define PGID_SRC 80
29
30/* Reserved PGIDs */
31#define PGID_CPU (PGID_AGGR - 5)
32#define PGID_UC (PGID_AGGR - 4)
33#define PGID_MC (PGID_AGGR - 3)

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437};
438
439struct ocelot_port {
440 struct net_device *dev;
441 struct ocelot *ocelot;
442 struct phy_device *phy;
443 void __iomem *regs;
444 u8 chip_port;
445 /* Keep a track of the mc addresses added to the mac table, so that they
446 * can be removed when needed.
447 */
448 struct list_head mc;
444
445 /* Ingress default VLAN (pvid) */
446 u16 pvid;
447
448 /* Egress default VLAN (vid) */
449 u16 vid;
450
451 u8 vlan_aware;
452
453 u64 *stats;
454
455 phy_interface_t phy_mode;
456 struct phy *serdes;
449
450 /* Ingress default VLAN (pvid) */
451 u16 pvid;
452
453 /* Egress default VLAN (vid) */
454 u16 vid;
455
456 u8 vlan_aware;
457
458 u64 *stats;
459
460 phy_interface_t phy_mode;
461 struct phy *serdes;
462
463 struct ocelot_port_tc tc;
457};
458
459u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset);
460#define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
461#define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
462#define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
463#define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0)
464

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465
466u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset);
467#define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
468#define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
469#define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
470#define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0)
471

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