ocelot.c (e205ceeb253723f4e4bdce619844ed678ae48276) ocelot.c (dc3de2a294eab8b1375f96eb4cf2a1d5edfcc9ab)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7#include <linux/etherdevice.h>
8#include <linux/ethtool.h>

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16#include <linux/phy.h>
17#include <linux/ptp_clock_kernel.h>
18#include <linux/skbuff.h>
19#include <linux/iopoll.h>
20#include <net/arp.h>
21#include <net/netevent.h>
22#include <net/rtnetlink.h>
23#include <net/switchdev.h>
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7#include <linux/etherdevice.h>
8#include <linux/ethtool.h>

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16#include <linux/phy.h>
17#include <linux/ptp_clock_kernel.h>
18#include <linux/skbuff.h>
19#include <linux/iopoll.h>
20#include <net/arp.h>
21#include <net/netevent.h>
22#include <net/rtnetlink.h>
23#include <net/switchdev.h>
24#include <net/dsa.h>
24
25#include "ocelot.h"
26#include "ocelot_ace.h"
27
28#define TABLE_UPDATE_SLEEP_US 10
29#define TABLE_UPDATE_TIMEOUT_US 100000
30
31/* MAC table entry types.

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127 | ANA_AGENCTRL_LEARN_FWD_KILL
128 | ANA_AGENCTRL_LEARN_IGNORE_VLAN,
129 ANA_AGENCTRL);
130
131 /* Clear the MAC table */
132 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS);
133}
134
25
26#include "ocelot.h"
27#include "ocelot_ace.h"
28
29#define TABLE_UPDATE_SLEEP_US 10
30#define TABLE_UPDATE_TIMEOUT_US 100000
31
32/* MAC table entry types.

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128 | ANA_AGENCTRL_LEARN_FWD_KILL
129 | ANA_AGENCTRL_LEARN_IGNORE_VLAN,
130 ANA_AGENCTRL);
131
132 /* Clear the MAC table */
133 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS);
134}
135
135static void ocelot_vcap_enable(struct ocelot *ocelot, struct ocelot_port *port)
136static void ocelot_vcap_enable(struct ocelot *ocelot, int port)
136{
137 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA |
138 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa),
137{
138 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA |
139 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa),
139 ANA_PORT_VCAP_S2_CFG, port->chip_port);
140 ANA_PORT_VCAP_S2_CFG, port);
140}
141
142static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot)
143{
144 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS);
145}
146
147static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot)

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164 /* Set the vlan port members mask and issue a write command */
165 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) |
166 ANA_TABLES_VLANACCESS_CMD_WRITE,
167 ANA_TABLES_VLANACCESS);
168
169 return ocelot_vlant_wait_for_completion(ocelot);
170}
171
141}
142
143static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot)
144{
145 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS);
146}
147
148static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot)

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165 /* Set the vlan port members mask and issue a write command */
166 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) |
167 ANA_TABLES_VLANACCESS_CMD_WRITE,
168 ANA_TABLES_VLANACCESS);
169
170 return ocelot_vlant_wait_for_completion(ocelot);
171}
172
172static void ocelot_vlan_mode(struct ocelot_port *port,
173static void ocelot_vlan_mode(struct ocelot *ocelot, int port,
173 netdev_features_t features)
174{
174 netdev_features_t features)
175{
175 struct ocelot *ocelot = port->ocelot;
176 u8 p = port->chip_port;
177 u32 val;
178
179 /* Filtering */
180 val = ocelot_read(ocelot, ANA_VLANMASK);
181 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
176 u32 val;
177
178 /* Filtering */
179 val = ocelot_read(ocelot, ANA_VLANMASK);
180 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
182 val |= BIT(p);
181 val |= BIT(port);
183 else
182 else
184 val &= ~BIT(p);
183 val &= ~BIT(port);
185 ocelot_write(ocelot, val, ANA_VLANMASK);
186}
187
184 ocelot_write(ocelot, val, ANA_VLANMASK);
185}
186
188static void ocelot_vlan_port_apply(struct ocelot *ocelot,
189 struct ocelot_port *port)
187static void ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
188 bool vlan_aware)
190{
189{
190 struct ocelot_port *ocelot_port = ocelot->ports[port];
191 u32 val;
192
191 u32 val;
192
193 /* Ingress clasification (ANA_PORT_VLAN_CFG) */
194 /* Default vlan to clasify for untagged frames (may be zero) */
195 val = ANA_PORT_VLAN_CFG_VLAN_VID(port->pvid);
196 if (port->vlan_aware)
197 val |= ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
198 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1);
199
193 if (vlan_aware)
194 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
195 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1);
196 else
197 val = 0;
200 ocelot_rmw_gix(ocelot, val,
198 ocelot_rmw_gix(ocelot, val,
201 ANA_PORT_VLAN_CFG_VLAN_VID_M |
202 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
203 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M,
199 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
200 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M,
204 ANA_PORT_VLAN_CFG, port->chip_port);
201 ANA_PORT_VLAN_CFG, port);
205
202
206 /* Drop frames with multicast source address */
207 val = ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA;
208 if (port->vlan_aware && !port->vid)
203 if (vlan_aware && !ocelot_port->vid)
209 /* If port is vlan-aware and tagged, drop untagged and priority
210 * tagged frames.
211 */
204 /* If port is vlan-aware and tagged, drop untagged and priority
205 * tagged frames.
206 */
212 val |= ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA |
207 val = ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA |
208 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
209 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA;
210 else
211 val = 0;
212 ocelot_rmw_gix(ocelot, val,
213 ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA |
213 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
214 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
214 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA;
215 ocelot_write_gix(ocelot, val, ANA_PORT_DROP_CFG, port->chip_port);
215 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA,
216 ANA_PORT_DROP_CFG, port);
216
217
217 /* Egress configuration (REW_TAG_CFG): VLAN tag type to 8021Q. */
218 val = REW_TAG_CFG_TAG_TPID_CFG(0);
219
220 if (port->vlan_aware) {
221 if (port->vid)
218 if (vlan_aware) {
219 if (ocelot_port->vid)
222 /* Tag all frames except when VID == DEFAULT_VLAN */
223 val |= REW_TAG_CFG_TAG_CFG(1);
224 else
225 /* Tag all frames */
226 val |= REW_TAG_CFG_TAG_CFG(3);
220 /* Tag all frames except when VID == DEFAULT_VLAN */
221 val |= REW_TAG_CFG_TAG_CFG(1);
222 else
223 /* Tag all frames */
224 val |= REW_TAG_CFG_TAG_CFG(3);
225 } else {
226 /* Port tagging disabled. */
227 val = REW_TAG_CFG_TAG_CFG(0);
227 }
228 ocelot_rmw_gix(ocelot, val,
228 }
229 ocelot_rmw_gix(ocelot, val,
229 REW_TAG_CFG_TAG_TPID_CFG_M |
230 REW_TAG_CFG_TAG_CFG_M,
230 REW_TAG_CFG_TAG_CFG_M,
231 REW_TAG_CFG, port->chip_port);
231 REW_TAG_CFG, port);
232}
232
233
233 /* Set default VLAN and tag type to 8021Q. */
234 val = REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q) |
235 REW_PORT_VLAN_CFG_PORT_VID(port->vid);
236 ocelot_rmw_gix(ocelot, val,
237 REW_PORT_VLAN_CFG_PORT_TPID_M |
234static int ocelot_port_set_native_vlan(struct ocelot *ocelot, int port,
235 u16 vid)
236{
237 struct ocelot_port *ocelot_port = ocelot->ports[port];
238
239 if (ocelot_port->vid != vid) {
240 /* Always permit deleting the native VLAN (vid = 0) */
241 if (ocelot_port->vid && vid) {
242 dev_err(ocelot->dev,
243 "Port already has a native VLAN: %d\n",
244 ocelot_port->vid);
245 return -EBUSY;
246 }
247 ocelot_port->vid = vid;
248 }
249
250 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_VID(vid),
238 REW_PORT_VLAN_CFG_PORT_VID_M,
251 REW_PORT_VLAN_CFG_PORT_VID_M,
239 REW_PORT_VLAN_CFG, port->chip_port);
252 REW_PORT_VLAN_CFG, port);
253
254 return 0;
240}
241
255}
256
242static int ocelot_vlan_vid_add(struct net_device *dev, u16 vid, bool pvid,
243 bool untagged)
257/* Default vlan to clasify for untagged frames (may be zero) */
258static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, u16 pvid)
244{
259{
245 struct ocelot_port *port = netdev_priv(dev);
246 struct ocelot *ocelot = port->ocelot;
247 int ret;
260 struct ocelot_port *ocelot_port = ocelot->ports[port];
248
261
249 /* Add the port MAC address to with the right VLAN information */
250 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, vid,
251 ENTRYTYPE_LOCKED);
262 ocelot_rmw_gix(ocelot,
263 ANA_PORT_VLAN_CFG_VLAN_VID(pvid),
264 ANA_PORT_VLAN_CFG_VLAN_VID_M,
265 ANA_PORT_VLAN_CFG, port);
252
266
267 ocelot_port->pvid = pvid;
268}
269
270static int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
271 bool untagged)
272{
273 int ret;
274
253 /* Make the port a member of the VLAN */
275 /* Make the port a member of the VLAN */
254 ocelot->vlan_mask[vid] |= BIT(port->chip_port);
276 ocelot->vlan_mask[vid] |= BIT(port);
255 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
256 if (ret)
257 return ret;
258
259 /* Default ingress vlan classification */
260 if (pvid)
277 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
278 if (ret)
279 return ret;
280
281 /* Default ingress vlan classification */
282 if (pvid)
261 port->pvid = vid;
283 ocelot_port_set_pvid(ocelot, port, vid);
262
263 /* Untagged egress vlan clasification */
284
285 /* Untagged egress vlan clasification */
264 if (untagged && port->vid != vid) {
265 if (port->vid) {
266 dev_err(ocelot->dev,
267 "Port already has a native VLAN: %d\n",
268 port->vid);
269 return -EBUSY;
270 }
271 port->vid = vid;
286 if (untagged) {
287 ret = ocelot_port_set_native_vlan(ocelot, port, vid);
288 if (ret)
289 return ret;
272 }
273
290 }
291
274 ocelot_vlan_port_apply(ocelot, port);
292 return 0;
293}
275
294
295static int ocelot_vlan_vid_add(struct net_device *dev, u16 vid, bool pvid,
296 bool untagged)
297{
298 struct ocelot_port_private *priv = netdev_priv(dev);
299 struct ocelot_port *ocelot_port = &priv->port;
300 struct ocelot *ocelot = ocelot_port->ocelot;
301 int port = priv->chip_port;
302 int ret;
303
304 ret = ocelot_vlan_add(ocelot, port, vid, pvid, untagged);
305 if (ret)
306 return ret;
307
308 /* Add the port MAC address to with the right VLAN information */
309 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, vid,
310 ENTRYTYPE_LOCKED);
311
276 return 0;
277}
278
312 return 0;
313}
314
315static int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid)
316{
317 struct ocelot_port *ocelot_port = ocelot->ports[port];
318 int ret;
319
320 /* Stop the port from being a member of the vlan */
321 ocelot->vlan_mask[vid] &= ~BIT(port);
322 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
323 if (ret)
324 return ret;
325
326 /* Ingress */
327 if (ocelot_port->pvid == vid)
328 ocelot_port_set_pvid(ocelot, port, 0);
329
330 /* Egress */
331 if (ocelot_port->vid == vid)
332 ocelot_port_set_native_vlan(ocelot, port, 0);
333
334 return 0;
335}
336
279static int ocelot_vlan_vid_del(struct net_device *dev, u16 vid)
280{
337static int ocelot_vlan_vid_del(struct net_device *dev, u16 vid)
338{
281 struct ocelot_port *port = netdev_priv(dev);
282 struct ocelot *ocelot = port->ocelot;
339 struct ocelot_port_private *priv = netdev_priv(dev);
340 struct ocelot *ocelot = priv->port.ocelot;
341 int port = priv->chip_port;
283 int ret;
284
285 /* 8021q removes VID 0 on module unload for all interfaces
286 * with VLAN filtering feature. We need to keep it to receive
287 * untagged traffic.
288 */
289 if (vid == 0)
290 return 0;
291
342 int ret;
343
344 /* 8021q removes VID 0 on module unload for all interfaces
345 * with VLAN filtering feature. We need to keep it to receive
346 * untagged traffic.
347 */
348 if (vid == 0)
349 return 0;
350
292 /* Del the port MAC address to with the right VLAN information */
293 ocelot_mact_forget(ocelot, dev->dev_addr, vid);
294
295 /* Stop the port from being a member of the vlan */
296 ocelot->vlan_mask[vid] &= ~BIT(port->chip_port);
297 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
351 ret = ocelot_vlan_del(ocelot, port, vid);
298 if (ret)
299 return ret;
300
352 if (ret)
353 return ret;
354
301 /* Ingress */
302 if (port->pvid == vid)
303 port->pvid = 0;
355 /* Del the port MAC address to with the right VLAN information */
356 ocelot_mact_forget(ocelot, dev->dev_addr, vid);
304
357
305 /* Egress */
306 if (port->vid == vid)
307 port->vid = 0;
308
309 ocelot_vlan_port_apply(ocelot, port);
310
311 return 0;
312}
313
314static void ocelot_vlan_init(struct ocelot *ocelot)
315{
316 u16 port, vid;
317
318 /* Clear VLAN table, by default all ports are members of all VLANs */

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328
329 /* Because VLAN filtering is enabled, we need VID 0 to get untagged
330 * traffic. It is added automatically if 8021q module is loaded, but
331 * we can't rely on it since module may be not loaded.
332 */
333 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0);
334 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]);
335
358 return 0;
359}
360
361static void ocelot_vlan_init(struct ocelot *ocelot)
362{
363 u16 port, vid;
364
365 /* Clear VLAN table, by default all ports are members of all VLANs */

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375
376 /* Because VLAN filtering is enabled, we need VID 0 to get untagged
377 * traffic. It is added automatically if 8021q module is loaded, but
378 * we can't rely on it since module may be not loaded.
379 */
380 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0);
381 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]);
382
336 /* Configure the CPU port to be VLAN aware */
337 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) |
338 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
339 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1),
340 ANA_PORT_VLAN_CFG, ocelot->num_phys_ports);
341
342 /* Set vlan ingress filter mask to all ports but the CPU port by
343 * default.
344 */
383 /* Set vlan ingress filter mask to all ports but the CPU port by
384 * default.
385 */
345 ocelot_write(ocelot, GENMASK(9, 0), ANA_VLANMASK);
386 ocelot_write(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),
387 ANA_VLANMASK);
346
347 for (port = 0; port < ocelot->num_phys_ports; port++) {
348 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port);
349 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port);
350 }
351}
352
353/* Watermark encode
354 * Bit 8: Unit; 0:1, 1:16
355 * Bit 7-0: Value to be multiplied with unit
356 */
357static u16 ocelot_wm_enc(u16 value)
358{
359 if (value >= BIT(8))
360 return BIT(8) | (value / 16);
361
362 return value;
363}
364
388
389 for (port = 0; port < ocelot->num_phys_ports; port++) {
390 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port);
391 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port);
392 }
393}
394
395/* Watermark encode
396 * Bit 8: Unit; 0:1, 1:16
397 * Bit 7-0: Value to be multiplied with unit
398 */
399static u16 ocelot_wm_enc(u16 value)
400{
401 if (value >= BIT(8))
402 return BIT(8) | (value / 16);
403
404 return value;
405}
406
365static void ocelot_port_adjust_link(struct net_device *dev)
407static void ocelot_adjust_link(struct ocelot *ocelot, int port,
408 struct phy_device *phydev)
366{
409{
367 struct ocelot_port *port = netdev_priv(dev);
368 struct ocelot *ocelot = port->ocelot;
369 u8 p = port->chip_port;
410 struct ocelot_port *ocelot_port = ocelot->ports[port];
370 int speed, atop_wm, mode = 0;
371
411 int speed, atop_wm, mode = 0;
412
372 switch (dev->phydev->speed) {
413 switch (phydev->speed) {
373 case SPEED_10:
374 speed = OCELOT_SPEED_10;
375 break;
376 case SPEED_100:
377 speed = OCELOT_SPEED_100;
378 break;
379 case SPEED_1000:
380 speed = OCELOT_SPEED_1000;
381 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
382 break;
383 case SPEED_2500:
384 speed = OCELOT_SPEED_2500;
385 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
386 break;
387 default:
414 case SPEED_10:
415 speed = OCELOT_SPEED_10;
416 break;
417 case SPEED_100:
418 speed = OCELOT_SPEED_100;
419 break;
420 case SPEED_1000:
421 speed = OCELOT_SPEED_1000;
422 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
423 break;
424 case SPEED_2500:
425 speed = OCELOT_SPEED_2500;
426 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
427 break;
428 default:
388 netdev_err(dev, "Unsupported PHY speed: %d\n",
389 dev->phydev->speed);
429 dev_err(ocelot->dev, "Unsupported PHY speed on port %d: %d\n",
430 port, phydev->speed);
390 return;
391 }
392
431 return;
432 }
433
393 phy_print_status(dev->phydev);
434 phy_print_status(phydev);
394
435
395 if (!dev->phydev->link)
436 if (!phydev->link)
396 return;
397
398 /* Only full duplex supported for now */
437 return;
438
439 /* Only full duplex supported for now */
399 ocelot_port_writel(port, DEV_MAC_MODE_CFG_FDX_ENA |
440 ocelot_port_writel(ocelot_port, DEV_MAC_MODE_CFG_FDX_ENA |
400 mode, DEV_MAC_MODE_CFG);
401
402 /* Set MAC IFG Gaps
403 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
404 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
405 */
441 mode, DEV_MAC_MODE_CFG);
442
443 /* Set MAC IFG Gaps
444 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
445 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
446 */
406 ocelot_port_writel(port, DEV_MAC_IFG_CFG_TX_IFG(5), DEV_MAC_IFG_CFG);
447 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5),
448 DEV_MAC_IFG_CFG);
407
408 /* Load seed (0) and set MAC HDX late collision */
449
450 /* Load seed (0) and set MAC HDX late collision */
409 ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
451 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
410 DEV_MAC_HDX_CFG_SEED_LOAD,
411 DEV_MAC_HDX_CFG);
412 mdelay(1);
452 DEV_MAC_HDX_CFG_SEED_LOAD,
453 DEV_MAC_HDX_CFG);
454 mdelay(1);
413 ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
455 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
414 DEV_MAC_HDX_CFG);
415
456 DEV_MAC_HDX_CFG);
457
416 /* Disable HDX fast control */
417 ocelot_port_writel(port, DEV_PORT_MISC_HDX_FAST_DIS, DEV_PORT_MISC);
458 if (ocelot->ops->pcs_init)
459 ocelot->ops->pcs_init(ocelot, port);
418
460
419 /* SGMII only for now */
420 ocelot_port_writel(port, PCS1G_MODE_CFG_SGMII_MODE_ENA, PCS1G_MODE_CFG);
421 ocelot_port_writel(port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG);
422
423 /* Enable PCS */
424 ocelot_port_writel(port, PCS1G_CFG_PCS_ENA, PCS1G_CFG);
425
426 /* No aneg on SGMII */
427 ocelot_port_writel(port, 0, PCS1G_ANEG_CFG);
428
429 /* No loopback */
430 ocelot_port_writel(port, 0, PCS1G_LB_CFG);
431
432 /* Set Max Length and maximum tags allowed */
461 /* Set Max Length and maximum tags allowed */
433 ocelot_port_writel(port, VLAN_ETH_FRAME_LEN, DEV_MAC_MAXLEN_CFG);
434 ocelot_port_writel(port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
462 ocelot_port_writel(ocelot_port, VLAN_ETH_FRAME_LEN,
463 DEV_MAC_MAXLEN_CFG);
464 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
435 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
436 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
437 DEV_MAC_TAGS_CFG);
438
439 /* Enable MAC module */
465 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
466 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
467 DEV_MAC_TAGS_CFG);
468
469 /* Enable MAC module */
440 ocelot_port_writel(port, DEV_MAC_ENA_CFG_RX_ENA |
470 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA |
441 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
442
443 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of
444 * reset */
471 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
472
473 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of
474 * reset */
445 ocelot_port_writel(port, DEV_CLOCK_CFG_LINK_SPEED(speed),
475 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(speed),
446 DEV_CLOCK_CFG);
447
448 /* Set SMAC of Pause frame (00:00:00:00:00:00) */
476 DEV_CLOCK_CFG);
477
478 /* Set SMAC of Pause frame (00:00:00:00:00:00) */
449 ocelot_port_writel(port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
450 ocelot_port_writel(port, 0, DEV_MAC_FC_MAC_LOW_CFG);
479 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
480 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG);
451
452 /* No PFC */
453 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed),
481
482 /* No PFC */
483 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed),
454 ANA_PFC_PFC_CFG, p);
484 ANA_PFC_PFC_CFG, port);
455
456 /* Set Pause WM hysteresis
457 * 152 = 6 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
458 * 101 = 4 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
459 */
460 ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA |
461 SYS_PAUSE_CFG_PAUSE_STOP(101) |
485
486 /* Set Pause WM hysteresis
487 * 152 = 6 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
488 * 101 = 4 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
489 */
490 ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA |
491 SYS_PAUSE_CFG_PAUSE_STOP(101) |
462 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, p);
492 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, port);
463
464 /* Core: Enable port for frame transfer */
465 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |
466 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
467 QSYS_SWITCH_PORT_MODE_PORT_ENA,
493
494 /* Core: Enable port for frame transfer */
495 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |
496 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
497 QSYS_SWITCH_PORT_MODE_PORT_ENA,
468 QSYS_SWITCH_PORT_MODE, p);
498 QSYS_SWITCH_PORT_MODE, port);
469
470 /* Flow control */
471 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
472 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA |
473 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA |
474 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
475 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed),
499
500 /* Flow control */
501 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
502 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA |
503 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA |
504 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
505 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed),
476 SYS_MAC_FC_CFG, p);
477 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, p);
506 SYS_MAC_FC_CFG, port);
507 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);
478
479 /* Tail dropping watermark */
480 atop_wm = (ocelot->shared_queue_sz - 9 * VLAN_ETH_FRAME_LEN) / OCELOT_BUFFER_CELL_SZ;
481 ocelot_write_rix(ocelot, ocelot_wm_enc(9 * VLAN_ETH_FRAME_LEN),
508
509 /* Tail dropping watermark */
510 atop_wm = (ocelot->shared_queue_sz - 9 * VLAN_ETH_FRAME_LEN) / OCELOT_BUFFER_CELL_SZ;
511 ocelot_write_rix(ocelot, ocelot_wm_enc(9 * VLAN_ETH_FRAME_LEN),
482 SYS_ATOP, p);
512 SYS_ATOP, port);
483 ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG);
484}
485
513 ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG);
514}
515
486static int ocelot_port_open(struct net_device *dev)
516static void ocelot_port_adjust_link(struct net_device *dev)
487{
517{
488 struct ocelot_port *port = netdev_priv(dev);
489 struct ocelot *ocelot = port->ocelot;
490 int err;
518 struct ocelot_port_private *priv = netdev_priv(dev);
519 struct ocelot *ocelot = priv->port.ocelot;
520 int port = priv->chip_port;
491
521
522 ocelot_adjust_link(ocelot, port, dev->phydev);
523}
524
525static void ocelot_port_enable(struct ocelot *ocelot, int port,
526 struct phy_device *phy)
527{
492 /* Enable receiving frames on the port, and activate auto-learning of
493 * MAC addresses.
494 */
495 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO |
496 ANA_PORT_PORT_CFG_RECV_ENA |
528 /* Enable receiving frames on the port, and activate auto-learning of
529 * MAC addresses.
530 */
531 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO |
532 ANA_PORT_PORT_CFG_RECV_ENA |
497 ANA_PORT_PORT_CFG_PORTID_VAL(port->chip_port),
498 ANA_PORT_PORT_CFG, port->chip_port);
533 ANA_PORT_PORT_CFG_PORTID_VAL(port),
534 ANA_PORT_PORT_CFG, port);
535}
499
536
500 if (port->serdes) {
501 err = phy_set_mode_ext(port->serdes, PHY_MODE_ETHERNET,
502 port->phy_mode);
537static int ocelot_port_open(struct net_device *dev)
538{
539 struct ocelot_port_private *priv = netdev_priv(dev);
540 struct ocelot *ocelot = priv->port.ocelot;
541 int port = priv->chip_port;
542 int err;
543
544 if (priv->serdes) {
545 err = phy_set_mode_ext(priv->serdes, PHY_MODE_ETHERNET,
546 priv->phy_mode);
503 if (err) {
504 netdev_err(dev, "Could not set mode of SerDes\n");
505 return err;
506 }
507 }
508
547 if (err) {
548 netdev_err(dev, "Could not set mode of SerDes\n");
549 return err;
550 }
551 }
552
509 err = phy_connect_direct(dev, port->phy, &ocelot_port_adjust_link,
510 port->phy_mode);
553 err = phy_connect_direct(dev, priv->phy, &ocelot_port_adjust_link,
554 priv->phy_mode);
511 if (err) {
512 netdev_err(dev, "Could not attach to PHY\n");
513 return err;
514 }
515
555 if (err) {
556 netdev_err(dev, "Could not attach to PHY\n");
557 return err;
558 }
559
516 dev->phydev = port->phy;
560 dev->phydev = priv->phy;
517
561
518 phy_attached_info(port->phy);
519 phy_start(port->phy);
562 phy_attached_info(priv->phy);
563 phy_start(priv->phy);
564
565 ocelot_port_enable(ocelot, port, priv->phy);
566
520 return 0;
521}
522
567 return 0;
568}
569
570static void ocelot_port_disable(struct ocelot *ocelot, int port)
571{
572 struct ocelot_port *ocelot_port = ocelot->ports[port];
573
574 ocelot_port_writel(ocelot_port, 0, DEV_MAC_ENA_CFG);
575 ocelot_rmw_rix(ocelot, 0, QSYS_SWITCH_PORT_MODE_PORT_ENA,
576 QSYS_SWITCH_PORT_MODE, port);
577}
578
523static int ocelot_port_stop(struct net_device *dev)
524{
579static int ocelot_port_stop(struct net_device *dev)
580{
525 struct ocelot_port *port = netdev_priv(dev);
581 struct ocelot_port_private *priv = netdev_priv(dev);
582 struct ocelot *ocelot = priv->port.ocelot;
583 int port = priv->chip_port;
526
584
527 phy_disconnect(port->phy);
585 phy_disconnect(priv->phy);
528
529 dev->phydev = NULL;
530
586
587 dev->phydev = NULL;
588
531 ocelot_port_writel(port, 0, DEV_MAC_ENA_CFG);
532 ocelot_rmw_rix(port->ocelot, 0, QSYS_SWITCH_PORT_MODE_PORT_ENA,
533 QSYS_SWITCH_PORT_MODE, port->chip_port);
589 ocelot_port_disable(ocelot, port);
590
534 return 0;
535}
536
537/* Generate the IFH for frame injection
538 *
539 * The IFH is a 128bit-value
540 * bit 127: bypass the analyzer processing
541 * bit 56-67: destination mask

--- 9 unchanged lines hidden (view full) ---

551 ifh[2] = (0xff & info->port) << 24;
552 ifh[3] = (info->tag_type << 16) | info->vid;
553
554 return 0;
555}
556
557static int ocelot_port_xmit(struct sk_buff *skb, struct net_device *dev)
558{
591 return 0;
592}
593
594/* Generate the IFH for frame injection
595 *
596 * The IFH is a 128bit-value
597 * bit 127: bypass the analyzer processing
598 * bit 56-67: destination mask

--- 9 unchanged lines hidden (view full) ---

608 ifh[2] = (0xff & info->port) << 24;
609 ifh[3] = (info->tag_type << 16) | info->vid;
610
611 return 0;
612}
613
614static int ocelot_port_xmit(struct sk_buff *skb, struct net_device *dev)
615{
616 struct ocelot_port_private *priv = netdev_priv(dev);
559 struct skb_shared_info *shinfo = skb_shinfo(skb);
617 struct skb_shared_info *shinfo = skb_shinfo(skb);
560 struct ocelot_port *port = netdev_priv(dev);
561 struct ocelot *ocelot = port->ocelot;
562 u32 val, ifh[IFH_LEN];
618 struct ocelot_port *ocelot_port = &priv->port;
619 struct ocelot *ocelot = ocelot_port->ocelot;
563 struct frame_info info = {};
564 u8 grp = 0; /* Send everything on CPU group 0 */
565 unsigned int i, count, last;
620 struct frame_info info = {};
621 u8 grp = 0; /* Send everything on CPU group 0 */
622 unsigned int i, count, last;
623 int port = priv->chip_port;
624 u32 val, ifh[IFH_LEN];
566
567 val = ocelot_read(ocelot, QS_INJ_STATUS);
568 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))) ||
569 (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp))))
570 return NETDEV_TX_BUSY;
571
572 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
573 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp);
574
625
626 val = ocelot_read(ocelot, QS_INJ_STATUS);
627 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))) ||
628 (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp))))
629 return NETDEV_TX_BUSY;
630
631 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
632 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp);
633
575 info.port = BIT(port->chip_port);
634 info.port = BIT(port);
576 info.tag_type = IFH_TAG_TYPE_C;
577 info.vid = skb_vlan_tag_get(skb);
578
579 /* Check if timestamping is needed */
580 if (ocelot->ptp && shinfo->tx_flags & SKBTX_HW_TSTAMP) {
635 info.tag_type = IFH_TAG_TYPE_C;
636 info.vid = skb_vlan_tag_get(skb);
637
638 /* Check if timestamping is needed */
639 if (ocelot->ptp && shinfo->tx_flags & SKBTX_HW_TSTAMP) {
581 info.rew_op = port->ptp_cmd;
582 if (port->ptp_cmd == IFH_REW_OP_TWO_STEP_PTP)
583 info.rew_op |= (port->ts_id % 4) << 3;
640 info.rew_op = ocelot_port->ptp_cmd;
641 if (ocelot_port->ptp_cmd == IFH_REW_OP_TWO_STEP_PTP)
642 info.rew_op |= (ocelot_port->ts_id % 4) << 3;
584 }
585
586 ocelot_gen_ifh(ifh, &info);
587
588 for (i = 0; i < IFH_LEN; i++)
589 ocelot_write_rix(ocelot, (__force u32)cpu_to_be32(ifh[i]),
590 QS_INJ_WR, grp);
591

--- 18 unchanged lines hidden (view full) ---

610 /* Add dummy CRC */
611 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
612 skb_tx_timestamp(skb);
613
614 dev->stats.tx_packets++;
615 dev->stats.tx_bytes += skb->len;
616
617 if (ocelot->ptp && shinfo->tx_flags & SKBTX_HW_TSTAMP &&
643 }
644
645 ocelot_gen_ifh(ifh, &info);
646
647 for (i = 0; i < IFH_LEN; i++)
648 ocelot_write_rix(ocelot, (__force u32)cpu_to_be32(ifh[i]),
649 QS_INJ_WR, grp);
650

--- 18 unchanged lines hidden (view full) ---

669 /* Add dummy CRC */
670 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
671 skb_tx_timestamp(skb);
672
673 dev->stats.tx_packets++;
674 dev->stats.tx_bytes += skb->len;
675
676 if (ocelot->ptp && shinfo->tx_flags & SKBTX_HW_TSTAMP &&
618 port->ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) {
677 ocelot_port->ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) {
619 struct ocelot_skb *oskb =
620 kzalloc(sizeof(struct ocelot_skb), GFP_ATOMIC);
621
622 if (unlikely(!oskb))
623 goto out;
624
625 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
626
627 oskb->skb = skb;
678 struct ocelot_skb *oskb =
679 kzalloc(sizeof(struct ocelot_skb), GFP_ATOMIC);
680
681 if (unlikely(!oskb))
682 goto out;
683
684 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
685
686 oskb->skb = skb;
628 oskb->id = port->ts_id % 4;
629 port->ts_id++;
687 oskb->id = ocelot_port->ts_id % 4;
688 ocelot_port->ts_id++;
630
689
631 list_add_tail(&oskb->head, &port->skbs);
690 list_add_tail(&oskb->head, &ocelot_port->skbs);
632
633 return NETDEV_TX_OK;
634 }
635
636out:
637 dev_kfree_skb_any(skb);
638 return NETDEV_TX_OK;
639}

--- 22 unchanged lines hidden (view full) ---

662 ts->tv_sec--;
663
664 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
665}
666EXPORT_SYMBOL(ocelot_get_hwtimestamp);
667
668static int ocelot_mc_unsync(struct net_device *dev, const unsigned char *addr)
669{
691
692 return NETDEV_TX_OK;
693 }
694
695out:
696 dev_kfree_skb_any(skb);
697 return NETDEV_TX_OK;
698}

--- 22 unchanged lines hidden (view full) ---

721 ts->tv_sec--;
722
723 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
724}
725EXPORT_SYMBOL(ocelot_get_hwtimestamp);
726
727static int ocelot_mc_unsync(struct net_device *dev, const unsigned char *addr)
728{
670 struct ocelot_port *port = netdev_priv(dev);
729 struct ocelot_port_private *priv = netdev_priv(dev);
730 struct ocelot_port *ocelot_port = &priv->port;
731 struct ocelot *ocelot = ocelot_port->ocelot;
671
732
672 return ocelot_mact_forget(port->ocelot, addr, port->pvid);
733 return ocelot_mact_forget(ocelot, addr, ocelot_port->pvid);
673}
674
675static int ocelot_mc_sync(struct net_device *dev, const unsigned char *addr)
676{
734}
735
736static int ocelot_mc_sync(struct net_device *dev, const unsigned char *addr)
737{
677 struct ocelot_port *port = netdev_priv(dev);
738 struct ocelot_port_private *priv = netdev_priv(dev);
739 struct ocelot_port *ocelot_port = &priv->port;
740 struct ocelot *ocelot = ocelot_port->ocelot;
678
741
679 return ocelot_mact_learn(port->ocelot, PGID_CPU, addr, port->pvid,
742 return ocelot_mact_learn(ocelot, PGID_CPU, addr, ocelot_port->pvid,
680 ENTRYTYPE_LOCKED);
681}
682
683static void ocelot_set_rx_mode(struct net_device *dev)
684{
743 ENTRYTYPE_LOCKED);
744}
745
746static void ocelot_set_rx_mode(struct net_device *dev)
747{
685 struct ocelot_port *port = netdev_priv(dev);
686 struct ocelot *ocelot = port->ocelot;
687 int i;
748 struct ocelot_port_private *priv = netdev_priv(dev);
749 struct ocelot *ocelot = priv->port.ocelot;
688 u32 val;
750 u32 val;
751 int i;
689
690 /* This doesn't handle promiscuous mode because the bridge core is
691 * setting IFF_PROMISC on all slave interfaces and all frames would be
692 * forwarded to the CPU port.
693 */
694 val = GENMASK(ocelot->num_phys_ports - 1, 0);
695 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++)
696 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
697
698 __dev_mc_sync(dev, ocelot_mc_sync, ocelot_mc_unsync);
699}
700
701static int ocelot_port_get_phys_port_name(struct net_device *dev,
702 char *buf, size_t len)
703{
752
753 /* This doesn't handle promiscuous mode because the bridge core is
754 * setting IFF_PROMISC on all slave interfaces and all frames would be
755 * forwarded to the CPU port.
756 */
757 val = GENMASK(ocelot->num_phys_ports - 1, 0);
758 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++)
759 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
760
761 __dev_mc_sync(dev, ocelot_mc_sync, ocelot_mc_unsync);
762}
763
764static int ocelot_port_get_phys_port_name(struct net_device *dev,
765 char *buf, size_t len)
766{
704 struct ocelot_port *port = netdev_priv(dev);
767 struct ocelot_port_private *priv = netdev_priv(dev);
768 int port = priv->chip_port;
705 int ret;
706
769 int ret;
770
707 ret = snprintf(buf, len, "p%d", port->chip_port);
771 ret = snprintf(buf, len, "p%d", port);
708 if (ret >= len)
709 return -EINVAL;
710
711 return 0;
712}
713
714static int ocelot_port_set_mac_address(struct net_device *dev, void *p)
715{
772 if (ret >= len)
773 return -EINVAL;
774
775 return 0;
776}
777
778static int ocelot_port_set_mac_address(struct net_device *dev, void *p)
779{
716 struct ocelot_port *port = netdev_priv(dev);
717 struct ocelot *ocelot = port->ocelot;
780 struct ocelot_port_private *priv = netdev_priv(dev);
781 struct ocelot_port *ocelot_port = &priv->port;
782 struct ocelot *ocelot = ocelot_port->ocelot;
718 const struct sockaddr *addr = p;
719
720 /* Learn the new net device MAC address in the mac table. */
783 const struct sockaddr *addr = p;
784
785 /* Learn the new net device MAC address in the mac table. */
721 ocelot_mact_learn(ocelot, PGID_CPU, addr->sa_data, port->pvid,
786 ocelot_mact_learn(ocelot, PGID_CPU, addr->sa_data, ocelot_port->pvid,
722 ENTRYTYPE_LOCKED);
723 /* Then forget the previous one. */
787 ENTRYTYPE_LOCKED);
788 /* Then forget the previous one. */
724 ocelot_mact_forget(ocelot, dev->dev_addr, port->pvid);
789 ocelot_mact_forget(ocelot, dev->dev_addr, ocelot_port->pvid);
725
726 ether_addr_copy(dev->dev_addr, addr->sa_data);
727 return 0;
728}
729
730static void ocelot_get_stats64(struct net_device *dev,
731 struct rtnl_link_stats64 *stats)
732{
790
791 ether_addr_copy(dev->dev_addr, addr->sa_data);
792 return 0;
793}
794
795static void ocelot_get_stats64(struct net_device *dev,
796 struct rtnl_link_stats64 *stats)
797{
733 struct ocelot_port *port = netdev_priv(dev);
734 struct ocelot *ocelot = port->ocelot;
798 struct ocelot_port_private *priv = netdev_priv(dev);
799 struct ocelot *ocelot = priv->port.ocelot;
800 int port = priv->chip_port;
735
736 /* Configure the port to read the stats from */
801
802 /* Configure the port to read the stats from */
737 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port->chip_port),
803 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port),
738 SYS_STAT_CFG);
739
740 /* Get Rx stats */
741 stats->rx_bytes = ocelot_read(ocelot, SYS_COUNT_RX_OCTETS);
742 stats->rx_packets = ocelot_read(ocelot, SYS_COUNT_RX_SHORTS) +
743 ocelot_read(ocelot, SYS_COUNT_RX_FRAGMENTS) +
744 ocelot_read(ocelot, SYS_COUNT_RX_JABBERS) +
745 ocelot_read(ocelot, SYS_COUNT_RX_LONGS) +

--- 14 unchanged lines hidden (view full) ---

760 ocelot_read(ocelot, SYS_COUNT_TX_512_1023) +
761 ocelot_read(ocelot, SYS_COUNT_TX_1024_1526) +
762 ocelot_read(ocelot, SYS_COUNT_TX_1527_MAX);
763 stats->tx_dropped = ocelot_read(ocelot, SYS_COUNT_TX_DROPS) +
764 ocelot_read(ocelot, SYS_COUNT_TX_AGING);
765 stats->collisions = ocelot_read(ocelot, SYS_COUNT_TX_COLLISION);
766}
767
804 SYS_STAT_CFG);
805
806 /* Get Rx stats */
807 stats->rx_bytes = ocelot_read(ocelot, SYS_COUNT_RX_OCTETS);
808 stats->rx_packets = ocelot_read(ocelot, SYS_COUNT_RX_SHORTS) +
809 ocelot_read(ocelot, SYS_COUNT_RX_FRAGMENTS) +
810 ocelot_read(ocelot, SYS_COUNT_RX_JABBERS) +
811 ocelot_read(ocelot, SYS_COUNT_RX_LONGS) +

--- 14 unchanged lines hidden (view full) ---

826 ocelot_read(ocelot, SYS_COUNT_TX_512_1023) +
827 ocelot_read(ocelot, SYS_COUNT_TX_1024_1526) +
828 ocelot_read(ocelot, SYS_COUNT_TX_1527_MAX);
829 stats->tx_dropped = ocelot_read(ocelot, SYS_COUNT_TX_DROPS) +
830 ocelot_read(ocelot, SYS_COUNT_TX_AGING);
831 stats->collisions = ocelot_read(ocelot, SYS_COUNT_TX_COLLISION);
832}
833
768static int ocelot_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
769 struct net_device *dev, const unsigned char *addr,
770 u16 vid, u16 flags,
771 struct netlink_ext_ack *extack)
834static int ocelot_fdb_add(struct ocelot *ocelot, int port,
835 const unsigned char *addr, u16 vid,
836 bool vlan_aware)
772{
837{
773 struct ocelot_port *port = netdev_priv(dev);
774 struct ocelot *ocelot = port->ocelot;
838 struct ocelot_port *ocelot_port = ocelot->ports[port];
775
776 if (!vid) {
839
840 if (!vid) {
777 if (!port->vlan_aware)
841 if (!vlan_aware)
778 /* If the bridge is not VLAN aware and no VID was
779 * provided, set it to pvid to ensure the MAC entry
780 * matches incoming untagged packets
781 */
842 /* If the bridge is not VLAN aware and no VID was
843 * provided, set it to pvid to ensure the MAC entry
844 * matches incoming untagged packets
845 */
782 vid = port->pvid;
846 vid = ocelot_port->pvid;
783 else
784 /* If the bridge is VLAN aware a VID must be provided as
785 * otherwise the learnt entry wouldn't match any frame.
786 */
787 return -EINVAL;
788 }
789
847 else
848 /* If the bridge is VLAN aware a VID must be provided as
849 * otherwise the learnt entry wouldn't match any frame.
850 */
851 return -EINVAL;
852 }
853
790 return ocelot_mact_learn(ocelot, port->chip_port, addr, vid,
791 ENTRYTYPE_LOCKED);
854 return ocelot_mact_learn(ocelot, port, addr, vid, ENTRYTYPE_LOCKED);
792}
793
855}
856
794static int ocelot_fdb_del(struct ndmsg *ndm, struct nlattr *tb[],
795 struct net_device *dev,
796 const unsigned char *addr, u16 vid)
857static int ocelot_port_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
858 struct net_device *dev,
859 const unsigned char *addr,
860 u16 vid, u16 flags,
861 struct netlink_ext_ack *extack)
797{
862{
798 struct ocelot_port *port = netdev_priv(dev);
799 struct ocelot *ocelot = port->ocelot;
863 struct ocelot_port_private *priv = netdev_priv(dev);
864 struct ocelot *ocelot = priv->port.ocelot;
865 int port = priv->chip_port;
800
866
867 return ocelot_fdb_add(ocelot, port, addr, vid, priv->vlan_aware);
868}
869
870static int ocelot_fdb_del(struct ocelot *ocelot, int port,
871 const unsigned char *addr, u16 vid)
872{
801 return ocelot_mact_forget(ocelot, addr, vid);
802}
803
873 return ocelot_mact_forget(ocelot, addr, vid);
874}
875
876static int ocelot_port_fdb_del(struct ndmsg *ndm, struct nlattr *tb[],
877 struct net_device *dev,
878 const unsigned char *addr, u16 vid)
879{
880 struct ocelot_port_private *priv = netdev_priv(dev);
881 struct ocelot *ocelot = priv->port.ocelot;
882 int port = priv->chip_port;
883
884 return ocelot_fdb_del(ocelot, port, addr, vid);
885}
886
804struct ocelot_dump_ctx {
805 struct net_device *dev;
806 struct sk_buff *skb;
807 struct netlink_callback *cb;
808 int idx;
809};
810
887struct ocelot_dump_ctx {
888 struct net_device *dev;
889 struct sk_buff *skb;
890 struct netlink_callback *cb;
891 int idx;
892};
893
811static int ocelot_fdb_do_dump(struct ocelot_mact_entry *entry,
812 struct ocelot_dump_ctx *dump)
894static int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid,
895 bool is_static, void *data)
813{
896{
897 struct ocelot_dump_ctx *dump = data;
814 u32 portid = NETLINK_CB(dump->cb->skb).portid;
815 u32 seq = dump->cb->nlh->nlmsg_seq;
816 struct nlmsghdr *nlh;
817 struct ndmsg *ndm;
818
819 if (dump->idx < dump->cb->args[2])
820 goto skip;
821

--- 4 unchanged lines hidden (view full) ---

826
827 ndm = nlmsg_data(nlh);
828 ndm->ndm_family = AF_BRIDGE;
829 ndm->ndm_pad1 = 0;
830 ndm->ndm_pad2 = 0;
831 ndm->ndm_flags = NTF_SELF;
832 ndm->ndm_type = 0;
833 ndm->ndm_ifindex = dump->dev->ifindex;
898 u32 portid = NETLINK_CB(dump->cb->skb).portid;
899 u32 seq = dump->cb->nlh->nlmsg_seq;
900 struct nlmsghdr *nlh;
901 struct ndmsg *ndm;
902
903 if (dump->idx < dump->cb->args[2])
904 goto skip;
905

--- 4 unchanged lines hidden (view full) ---

910
911 ndm = nlmsg_data(nlh);
912 ndm->ndm_family = AF_BRIDGE;
913 ndm->ndm_pad1 = 0;
914 ndm->ndm_pad2 = 0;
915 ndm->ndm_flags = NTF_SELF;
916 ndm->ndm_type = 0;
917 ndm->ndm_ifindex = dump->dev->ifindex;
834 ndm->ndm_state = NUD_REACHABLE;
918 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
835
919
836 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, entry->mac))
920 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr))
837 goto nla_put_failure;
838
921 goto nla_put_failure;
922
839 if (entry->vid && nla_put_u16(dump->skb, NDA_VLAN, entry->vid))
923 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid))
840 goto nla_put_failure;
841
842 nlmsg_end(dump->skb, nlh);
843
844skip:
845 dump->idx++;
846 return 0;
847
848nla_put_failure:
849 nlmsg_cancel(dump->skb, nlh);
850 return -EMSGSIZE;
851}
852
924 goto nla_put_failure;
925
926 nlmsg_end(dump->skb, nlh);
927
928skip:
929 dump->idx++;
930 return 0;
931
932nla_put_failure:
933 nlmsg_cancel(dump->skb, nlh);
934 return -EMSGSIZE;
935}
936
853static inline int ocelot_mact_read(struct ocelot_port *port, int row, int col,
854 struct ocelot_mact_entry *entry)
937static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col,
938 struct ocelot_mact_entry *entry)
855{
939{
856 struct ocelot *ocelot = port->ocelot;
857 char mac[ETH_ALEN];
858 u32 val, dst, macl, mach;
940 u32 val, dst, macl, mach;
941 char mac[ETH_ALEN];
859
860 /* Set row and column to read from */
861 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row);
862 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col);
863
864 /* Issue a read command */
865 ocelot_write(ocelot,
866 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ),

--- 6 unchanged lines hidden (view full) ---

873 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
874 if (!(val & ANA_TABLES_MACACCESS_VALID))
875 return -EINVAL;
876
877 /* If the entry read has another port configured as its destination,
878 * do not report it.
879 */
880 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3;
942
943 /* Set row and column to read from */
944 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row);
945 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col);
946
947 /* Issue a read command */
948 ocelot_write(ocelot,
949 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ),

--- 6 unchanged lines hidden (view full) ---

956 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
957 if (!(val & ANA_TABLES_MACACCESS_VALID))
958 return -EINVAL;
959
960 /* If the entry read has another port configured as its destination,
961 * do not report it.
962 */
963 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3;
881 if (dst != port->chip_port)
964 if (dst != port)
882 return -EINVAL;
883
884 /* Get the entry's MAC address and VLAN id */
885 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA);
886 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA);
887
888 mac[0] = (mach >> 8) & 0xff;
889 mac[1] = (mach >> 0) & 0xff;
890 mac[2] = (macl >> 24) & 0xff;
891 mac[3] = (macl >> 16) & 0xff;
892 mac[4] = (macl >> 8) & 0xff;
893 mac[5] = (macl >> 0) & 0xff;
894
895 entry->vid = (mach >> 16) & 0xfff;
896 ether_addr_copy(entry->mac, mac);
897
898 return 0;
899}
900
965 return -EINVAL;
966
967 /* Get the entry's MAC address and VLAN id */
968 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA);
969 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA);
970
971 mac[0] = (mach >> 8) & 0xff;
972 mac[1] = (mach >> 0) & 0xff;
973 mac[2] = (macl >> 24) & 0xff;
974 mac[3] = (macl >> 16) & 0xff;
975 mac[4] = (macl >> 8) & 0xff;
976 mac[5] = (macl >> 0) & 0xff;
977
978 entry->vid = (mach >> 16) & 0xfff;
979 ether_addr_copy(entry->mac, mac);
980
981 return 0;
982}
983
901static int ocelot_fdb_dump(struct sk_buff *skb, struct netlink_callback *cb,
902 struct net_device *dev,
903 struct net_device *filter_dev, int *idx)
984static int ocelot_fdb_dump(struct ocelot *ocelot, int port,
985 dsa_fdb_dump_cb_t *cb, void *data)
904{
986{
905 struct ocelot_port *port = netdev_priv(dev);
906 int i, j, ret = 0;
907 struct ocelot_dump_ctx dump = {
908 .dev = dev,
909 .skb = skb,
910 .cb = cb,
911 .idx = *idx,
912 };
987 int i, j;
913
988
914 struct ocelot_mact_entry entry;
915
916 /* Loop through all the mac tables entries. There are 1024 rows of 4
917 * entries.
918 */
919 for (i = 0; i < 1024; i++) {
920 for (j = 0; j < 4; j++) {
989 /* Loop through all the mac tables entries. There are 1024 rows of 4
990 * entries.
991 */
992 for (i = 0; i < 1024; i++) {
993 for (j = 0; j < 4; j++) {
921 ret = ocelot_mact_read(port, i, j, &entry);
994 struct ocelot_mact_entry entry;
995 bool is_static;
996 int ret;
997
998 ret = ocelot_mact_read(ocelot, port, i, j, &entry);
922 /* If the entry is invalid (wrong port, invalid...),
923 * skip it.
924 */
925 if (ret == -EINVAL)
926 continue;
927 else if (ret)
999 /* If the entry is invalid (wrong port, invalid...),
1000 * skip it.
1001 */
1002 if (ret == -EINVAL)
1003 continue;
1004 else if (ret)
928 goto end;
1005 return ret;
929
1006
930 ret = ocelot_fdb_do_dump(&entry, &dump);
1007 is_static = (entry.type == ENTRYTYPE_LOCKED);
1008
1009 ret = cb(entry.mac, entry.vid, is_static, data);
931 if (ret)
1010 if (ret)
932 goto end;
1011 return ret;
933 }
934 }
935
1012 }
1013 }
1014
936end:
1015 return 0;
1016}
1017
1018static int ocelot_port_fdb_dump(struct sk_buff *skb,
1019 struct netlink_callback *cb,
1020 struct net_device *dev,
1021 struct net_device *filter_dev, int *idx)
1022{
1023 struct ocelot_port_private *priv = netdev_priv(dev);
1024 struct ocelot *ocelot = priv->port.ocelot;
1025 struct ocelot_dump_ctx dump = {
1026 .dev = dev,
1027 .skb = skb,
1028 .cb = cb,
1029 .idx = *idx,
1030 };
1031 int port = priv->chip_port;
1032 int ret;
1033
1034 ret = ocelot_fdb_dump(ocelot, port, ocelot_port_fdb_do_dump, &dump);
1035
937 *idx = dump.idx;
1036 *idx = dump.idx;
1037
938 return ret;
939}
940
941static int ocelot_vlan_rx_add_vid(struct net_device *dev, __be16 proto,
942 u16 vid)
943{
944 return ocelot_vlan_vid_add(dev, vid, false, false);
945}
946
947static int ocelot_vlan_rx_kill_vid(struct net_device *dev, __be16 proto,
948 u16 vid)
949{
950 return ocelot_vlan_vid_del(dev, vid);
951}
952
953static int ocelot_set_features(struct net_device *dev,
954 netdev_features_t features)
955{
1038 return ret;
1039}
1040
1041static int ocelot_vlan_rx_add_vid(struct net_device *dev, __be16 proto,
1042 u16 vid)
1043{
1044 return ocelot_vlan_vid_add(dev, vid, false, false);
1045}
1046
1047static int ocelot_vlan_rx_kill_vid(struct net_device *dev, __be16 proto,
1048 u16 vid)
1049{
1050 return ocelot_vlan_vid_del(dev, vid);
1051}
1052
1053static int ocelot_set_features(struct net_device *dev,
1054 netdev_features_t features)
1055{
956 struct ocelot_port *port = netdev_priv(dev);
957 netdev_features_t changed = dev->features ^ features;
1056 netdev_features_t changed = dev->features ^ features;
1057 struct ocelot_port_private *priv = netdev_priv(dev);
1058 struct ocelot *ocelot = priv->port.ocelot;
1059 int port = priv->chip_port;
958
959 if ((dev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) &&
1060
1061 if ((dev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) &&
960 port->tc.offload_cnt) {
1062 priv->tc.offload_cnt) {
961 netdev_err(dev,
962 "Cannot disable HW TC offload while offloads active\n");
963 return -EBUSY;
964 }
965
966 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER)
1063 netdev_err(dev,
1064 "Cannot disable HW TC offload while offloads active\n");
1065 return -EBUSY;
1066 }
1067
1068 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER)
967 ocelot_vlan_mode(port, features);
1069 ocelot_vlan_mode(ocelot, port, features);
968
969 return 0;
970}
971
972static int ocelot_get_port_parent_id(struct net_device *dev,
973 struct netdev_phys_item_id *ppid)
974{
1070
1071 return 0;
1072}
1073
1074static int ocelot_get_port_parent_id(struct net_device *dev,
1075 struct netdev_phys_item_id *ppid)
1076{
975 struct ocelot_port *ocelot_port = netdev_priv(dev);
976 struct ocelot *ocelot = ocelot_port->ocelot;
1077 struct ocelot_port_private *priv = netdev_priv(dev);
1078 struct ocelot *ocelot = priv->port.ocelot;
977
978 ppid->id_len = sizeof(ocelot->base_mac);
979 memcpy(&ppid->id, &ocelot->base_mac, ppid->id_len);
980
981 return 0;
982}
983
1079
1080 ppid->id_len = sizeof(ocelot->base_mac);
1081 memcpy(&ppid->id, &ocelot->base_mac, ppid->id_len);
1082
1083 return 0;
1084}
1085
984static int ocelot_hwstamp_get(struct ocelot_port *port, struct ifreq *ifr)
1086static int ocelot_hwstamp_get(struct ocelot *ocelot, int port,
1087 struct ifreq *ifr)
985{
1088{
986 struct ocelot *ocelot = port->ocelot;
987
988 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config,
989 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0;
990}
991
1089 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config,
1090 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0;
1091}
1092
992static int ocelot_hwstamp_set(struct ocelot_port *port, struct ifreq *ifr)
1093static int ocelot_hwstamp_set(struct ocelot *ocelot, int port,
1094 struct ifreq *ifr)
993{
1095{
994 struct ocelot *ocelot = port->ocelot;
1096 struct ocelot_port *ocelot_port = ocelot->ports[port];
995 struct hwtstamp_config cfg;
996
997 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
998 return -EFAULT;
999
1000 /* reserved for future extensions */
1001 if (cfg.flags)
1002 return -EINVAL;
1003
1004 /* Tx type sanity check */
1005 switch (cfg.tx_type) {
1006 case HWTSTAMP_TX_ON:
1097 struct hwtstamp_config cfg;
1098
1099 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1100 return -EFAULT;
1101
1102 /* reserved for future extensions */
1103 if (cfg.flags)
1104 return -EINVAL;
1105
1106 /* Tx type sanity check */
1107 switch (cfg.tx_type) {
1108 case HWTSTAMP_TX_ON:
1007 port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP;
1109 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP;
1008 break;
1009 case HWTSTAMP_TX_ONESTEP_SYNC:
1010 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we
1011 * need to update the origin time.
1012 */
1110 break;
1111 case HWTSTAMP_TX_ONESTEP_SYNC:
1112 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we
1113 * need to update the origin time.
1114 */
1013 port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP;
1115 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP;
1014 break;
1015 case HWTSTAMP_TX_OFF:
1116 break;
1117 case HWTSTAMP_TX_OFF:
1016 port->ptp_cmd = 0;
1118 ocelot_port->ptp_cmd = 0;
1017 break;
1018 default:
1019 return -ERANGE;
1020 }
1021
1022 mutex_lock(&ocelot->ptp_lock);
1023
1024 switch (cfg.rx_filter) {

--- 25 unchanged lines hidden (view full) ---

1050 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg));
1051 mutex_unlock(&ocelot->ptp_lock);
1052
1053 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1054}
1055
1056static int ocelot_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1057{
1119 break;
1120 default:
1121 return -ERANGE;
1122 }
1123
1124 mutex_lock(&ocelot->ptp_lock);
1125
1126 switch (cfg.rx_filter) {

--- 25 unchanged lines hidden (view full) ---

1152 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg));
1153 mutex_unlock(&ocelot->ptp_lock);
1154
1155 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1156}
1157
1158static int ocelot_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1159{
1058 struct ocelot_port *port = netdev_priv(dev);
1059 struct ocelot *ocelot = port->ocelot;
1160 struct ocelot_port_private *priv = netdev_priv(dev);
1161 struct ocelot *ocelot = priv->port.ocelot;
1162 int port = priv->chip_port;
1060
1061 /* The function is only used for PTP operations for now */
1062 if (!ocelot->ptp)
1063 return -EOPNOTSUPP;
1064
1065 switch (cmd) {
1066 case SIOCSHWTSTAMP:
1163
1164 /* The function is only used for PTP operations for now */
1165 if (!ocelot->ptp)
1166 return -EOPNOTSUPP;
1167
1168 switch (cmd) {
1169 case SIOCSHWTSTAMP:
1067 return ocelot_hwstamp_set(port, ifr);
1170 return ocelot_hwstamp_set(ocelot, port, ifr);
1068 case SIOCGHWTSTAMP:
1171 case SIOCGHWTSTAMP:
1069 return ocelot_hwstamp_get(port, ifr);
1172 return ocelot_hwstamp_get(ocelot, port, ifr);
1070 default:
1071 return -EOPNOTSUPP;
1072 }
1073}
1074
1075static const struct net_device_ops ocelot_port_netdev_ops = {
1076 .ndo_open = ocelot_port_open,
1077 .ndo_stop = ocelot_port_stop,
1078 .ndo_start_xmit = ocelot_port_xmit,
1079 .ndo_set_rx_mode = ocelot_set_rx_mode,
1080 .ndo_get_phys_port_name = ocelot_port_get_phys_port_name,
1081 .ndo_set_mac_address = ocelot_port_set_mac_address,
1082 .ndo_get_stats64 = ocelot_get_stats64,
1173 default:
1174 return -EOPNOTSUPP;
1175 }
1176}
1177
1178static const struct net_device_ops ocelot_port_netdev_ops = {
1179 .ndo_open = ocelot_port_open,
1180 .ndo_stop = ocelot_port_stop,
1181 .ndo_start_xmit = ocelot_port_xmit,
1182 .ndo_set_rx_mode = ocelot_set_rx_mode,
1183 .ndo_get_phys_port_name = ocelot_port_get_phys_port_name,
1184 .ndo_set_mac_address = ocelot_port_set_mac_address,
1185 .ndo_get_stats64 = ocelot_get_stats64,
1083 .ndo_fdb_add = ocelot_fdb_add,
1084 .ndo_fdb_del = ocelot_fdb_del,
1085 .ndo_fdb_dump = ocelot_fdb_dump,
1186 .ndo_fdb_add = ocelot_port_fdb_add,
1187 .ndo_fdb_del = ocelot_port_fdb_del,
1188 .ndo_fdb_dump = ocelot_port_fdb_dump,
1086 .ndo_vlan_rx_add_vid = ocelot_vlan_rx_add_vid,
1087 .ndo_vlan_rx_kill_vid = ocelot_vlan_rx_kill_vid,
1088 .ndo_set_features = ocelot_set_features,
1089 .ndo_get_port_parent_id = ocelot_get_port_parent_id,
1090 .ndo_setup_tc = ocelot_setup_tc,
1091 .ndo_do_ioctl = ocelot_ioctl,
1092};
1093
1189 .ndo_vlan_rx_add_vid = ocelot_vlan_rx_add_vid,
1190 .ndo_vlan_rx_kill_vid = ocelot_vlan_rx_kill_vid,
1191 .ndo_set_features = ocelot_set_features,
1192 .ndo_get_port_parent_id = ocelot_get_port_parent_id,
1193 .ndo_setup_tc = ocelot_setup_tc,
1194 .ndo_do_ioctl = ocelot_ioctl,
1195};
1196
1094static void ocelot_get_strings(struct net_device *netdev, u32 sset, u8 *data)
1197static void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset,
1198 u8 *data)
1095{
1199{
1096 struct ocelot_port *port = netdev_priv(netdev);
1097 struct ocelot *ocelot = port->ocelot;
1098 int i;
1099
1100 if (sset != ETH_SS_STATS)
1101 return;
1102
1103 for (i = 0; i < ocelot->num_stats; i++)
1104 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name,
1105 ETH_GSTRING_LEN);
1106}
1107
1200 int i;
1201
1202 if (sset != ETH_SS_STATS)
1203 return;
1204
1205 for (i = 0; i < ocelot->num_stats; i++)
1206 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name,
1207 ETH_GSTRING_LEN);
1208}
1209
1210static void ocelot_port_get_strings(struct net_device *netdev, u32 sset,
1211 u8 *data)
1212{
1213 struct ocelot_port_private *priv = netdev_priv(netdev);
1214 struct ocelot *ocelot = priv->port.ocelot;
1215 int port = priv->chip_port;
1216
1217 ocelot_get_strings(ocelot, port, sset, data);
1218}
1219
1108static void ocelot_update_stats(struct ocelot *ocelot)
1109{
1110 int i, j;
1111
1112 mutex_lock(&ocelot->stats_lock);
1113
1114 for (i = 0; i < ocelot->num_phys_ports; i++) {
1115 /* Configure the port to read the stats from */

--- 24 unchanged lines hidden (view full) ---

1140 stats_work);
1141
1142 ocelot_update_stats(ocelot);
1143
1144 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
1145 OCELOT_STATS_CHECK_DELAY);
1146}
1147
1220static void ocelot_update_stats(struct ocelot *ocelot)
1221{
1222 int i, j;
1223
1224 mutex_lock(&ocelot->stats_lock);
1225
1226 for (i = 0; i < ocelot->num_phys_ports; i++) {
1227 /* Configure the port to read the stats from */

--- 24 unchanged lines hidden (view full) ---

1252 stats_work);
1253
1254 ocelot_update_stats(ocelot);
1255
1256 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
1257 OCELOT_STATS_CHECK_DELAY);
1258}
1259
1148static void ocelot_get_ethtool_stats(struct net_device *dev,
1149 struct ethtool_stats *stats, u64 *data)
1260static void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data)
1150{
1261{
1151 struct ocelot_port *port = netdev_priv(dev);
1152 struct ocelot *ocelot = port->ocelot;
1153 int i;
1154
1155 /* check and update now */
1156 ocelot_update_stats(ocelot);
1157
1158 /* Copy all counters */
1159 for (i = 0; i < ocelot->num_stats; i++)
1262 int i;
1263
1264 /* check and update now */
1265 ocelot_update_stats(ocelot);
1266
1267 /* Copy all counters */
1268 for (i = 0; i < ocelot->num_stats; i++)
1160 *data++ = ocelot->stats[port->chip_port * ocelot->num_stats + i];
1269 *data++ = ocelot->stats[port * ocelot->num_stats + i];
1161}
1162
1270}
1271
1163static int ocelot_get_sset_count(struct net_device *dev, int sset)
1272static void ocelot_port_get_ethtool_stats(struct net_device *dev,
1273 struct ethtool_stats *stats,
1274 u64 *data)
1164{
1275{
1165 struct ocelot_port *port = netdev_priv(dev);
1166 struct ocelot *ocelot = port->ocelot;
1276 struct ocelot_port_private *priv = netdev_priv(dev);
1277 struct ocelot *ocelot = priv->port.ocelot;
1278 int port = priv->chip_port;
1167
1279
1280 ocelot_get_ethtool_stats(ocelot, port, data);
1281}
1282
1283static int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset)
1284{
1168 if (sset != ETH_SS_STATS)
1169 return -EOPNOTSUPP;
1285 if (sset != ETH_SS_STATS)
1286 return -EOPNOTSUPP;
1287
1170 return ocelot->num_stats;
1171}
1172
1288 return ocelot->num_stats;
1289}
1290
1173static int ocelot_get_ts_info(struct net_device *dev,
1174 struct ethtool_ts_info *info)
1291static int ocelot_port_get_sset_count(struct net_device *dev, int sset)
1175{
1292{
1176 struct ocelot_port *ocelot_port = netdev_priv(dev);
1177 struct ocelot *ocelot = ocelot_port->ocelot;
1293 struct ocelot_port_private *priv = netdev_priv(dev);
1294 struct ocelot *ocelot = priv->port.ocelot;
1295 int port = priv->chip_port;
1178
1296
1179 if (!ocelot->ptp)
1180 return ethtool_op_get_ts_info(dev, info);
1297 return ocelot_get_sset_count(ocelot, port, sset);
1298}
1181
1299
1300static int ocelot_get_ts_info(struct ocelot *ocelot, int port,
1301 struct ethtool_ts_info *info)
1302{
1182 info->phc_index = ocelot->ptp_clock ?
1183 ptp_clock_index(ocelot->ptp_clock) : -1;
1184 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE |
1185 SOF_TIMESTAMPING_RX_SOFTWARE |
1186 SOF_TIMESTAMPING_SOFTWARE |
1187 SOF_TIMESTAMPING_TX_HARDWARE |
1188 SOF_TIMESTAMPING_RX_HARDWARE |
1189 SOF_TIMESTAMPING_RAW_HARDWARE;
1190 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) |
1191 BIT(HWTSTAMP_TX_ONESTEP_SYNC);
1192 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL);
1193
1194 return 0;
1195}
1196
1303 info->phc_index = ocelot->ptp_clock ?
1304 ptp_clock_index(ocelot->ptp_clock) : -1;
1305 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE |
1306 SOF_TIMESTAMPING_RX_SOFTWARE |
1307 SOF_TIMESTAMPING_SOFTWARE |
1308 SOF_TIMESTAMPING_TX_HARDWARE |
1309 SOF_TIMESTAMPING_RX_HARDWARE |
1310 SOF_TIMESTAMPING_RAW_HARDWARE;
1311 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) |
1312 BIT(HWTSTAMP_TX_ONESTEP_SYNC);
1313 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL);
1314
1315 return 0;
1316}
1317
1318static int ocelot_port_get_ts_info(struct net_device *dev,
1319 struct ethtool_ts_info *info)
1320{
1321 struct ocelot_port_private *priv = netdev_priv(dev);
1322 struct ocelot *ocelot = priv->port.ocelot;
1323 int port = priv->chip_port;
1324
1325 if (!ocelot->ptp)
1326 return ethtool_op_get_ts_info(dev, info);
1327
1328 return ocelot_get_ts_info(ocelot, port, info);
1329}
1330
1197static const struct ethtool_ops ocelot_ethtool_ops = {
1331static const struct ethtool_ops ocelot_ethtool_ops = {
1198 .get_strings = ocelot_get_strings,
1199 .get_ethtool_stats = ocelot_get_ethtool_stats,
1200 .get_sset_count = ocelot_get_sset_count,
1332 .get_strings = ocelot_port_get_strings,
1333 .get_ethtool_stats = ocelot_port_get_ethtool_stats,
1334 .get_sset_count = ocelot_port_get_sset_count,
1201 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1202 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1335 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1336 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1203 .get_ts_info = ocelot_get_ts_info,
1337 .get_ts_info = ocelot_port_get_ts_info,
1204};
1205
1338};
1339
1206static int ocelot_port_attr_stp_state_set(struct ocelot_port *ocelot_port,
1207 struct switchdev_trans *trans,
1208 u8 state)
1340static void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port,
1341 u8 state)
1209{
1342{
1210 struct ocelot *ocelot = ocelot_port->ocelot;
1211 u32 port_cfg;
1343 u32 port_cfg;
1212 int port, i;
1344 int p, i;
1213
1345
1214 if (switchdev_trans_ph_prepare(trans))
1215 return 0;
1346 if (!(BIT(port) & ocelot->bridge_mask))
1347 return;
1216
1348
1217 if (!(BIT(ocelot_port->chip_port) & ocelot->bridge_mask))
1218 return 0;
1349 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port);
1219
1350
1220 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG,
1221 ocelot_port->chip_port);
1222
1223 switch (state) {
1224 case BR_STATE_FORWARDING:
1351 switch (state) {
1352 case BR_STATE_FORWARDING:
1225 ocelot->bridge_fwd_mask |= BIT(ocelot_port->chip_port);
1353 ocelot->bridge_fwd_mask |= BIT(port);
1226 /* Fallthrough */
1227 case BR_STATE_LEARNING:
1228 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA;
1229 break;
1230
1231 default:
1232 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA;
1354 /* Fallthrough */
1355 case BR_STATE_LEARNING:
1356 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA;
1357 break;
1358
1359 default:
1360 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA;
1233 ocelot->bridge_fwd_mask &= ~BIT(ocelot_port->chip_port);
1361 ocelot->bridge_fwd_mask &= ~BIT(port);
1234 break;
1235 }
1236
1362 break;
1363 }
1364
1237 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG,
1238 ocelot_port->chip_port);
1365 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG, port);
1239
1240 /* Apply FWD mask. The loop is needed to add/remove the current port as
1241 * a source for the other ports.
1242 */
1366
1367 /* Apply FWD mask. The loop is needed to add/remove the current port as
1368 * a source for the other ports.
1369 */
1243 for (port = 0; port < ocelot->num_phys_ports; port++) {
1244 if (ocelot->bridge_fwd_mask & BIT(port)) {
1245 unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(port);
1370 for (p = 0; p < ocelot->num_phys_ports; p++) {
1371 if (p == ocelot->cpu || (ocelot->bridge_fwd_mask & BIT(p))) {
1372 unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(p);
1246
1247 for (i = 0; i < ocelot->num_phys_ports; i++) {
1248 unsigned long bond_mask = ocelot->lags[i];
1249
1250 if (!bond_mask)
1251 continue;
1252
1373
1374 for (i = 0; i < ocelot->num_phys_ports; i++) {
1375 unsigned long bond_mask = ocelot->lags[i];
1376
1377 if (!bond_mask)
1378 continue;
1379
1253 if (bond_mask & BIT(port)) {
1380 if (bond_mask & BIT(p)) {
1254 mask &= ~bond_mask;
1255 break;
1256 }
1257 }
1258
1381 mask &= ~bond_mask;
1382 break;
1383 }
1384 }
1385
1259 ocelot_write_rix(ocelot,
1260 BIT(ocelot->num_phys_ports) | mask,
1261 ANA_PGID_PGID, PGID_SRC + port);
1386 /* Avoid the NPI port from looping back to itself */
1387 if (p != ocelot->cpu)
1388 mask |= BIT(ocelot->cpu);
1389
1390 ocelot_write_rix(ocelot, mask,
1391 ANA_PGID_PGID, PGID_SRC + p);
1262 } else {
1263 /* Only the CPU port, this is compatible with link
1264 * aggregation.
1265 */
1266 ocelot_write_rix(ocelot,
1392 } else {
1393 /* Only the CPU port, this is compatible with link
1394 * aggregation.
1395 */
1396 ocelot_write_rix(ocelot,
1267 BIT(ocelot->num_phys_ports),
1268 ANA_PGID_PGID, PGID_SRC + port);
1397 BIT(ocelot->cpu),
1398 ANA_PGID_PGID, PGID_SRC + p);
1269 }
1270 }
1399 }
1400 }
1401}
1271
1402
1272 return 0;
1403static void ocelot_port_attr_stp_state_set(struct ocelot *ocelot, int port,
1404 struct switchdev_trans *trans,
1405 u8 state)
1406{
1407 if (switchdev_trans_ph_prepare(trans))
1408 return;
1409
1410 ocelot_bridge_stp_state_set(ocelot, port, state);
1273}
1274
1411}
1412
1275static void ocelot_port_attr_ageing_set(struct ocelot_port *ocelot_port,
1413static void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs)
1414{
1415 ocelot_write(ocelot, ANA_AUTOAGE_AGE_PERIOD(msecs / 2),
1416 ANA_AUTOAGE);
1417}
1418
1419static void ocelot_port_attr_ageing_set(struct ocelot *ocelot, int port,
1276 unsigned long ageing_clock_t)
1277{
1420 unsigned long ageing_clock_t)
1421{
1278 struct ocelot *ocelot = ocelot_port->ocelot;
1279 unsigned long ageing_jiffies = clock_t_to_jiffies(ageing_clock_t);
1280 u32 ageing_time = jiffies_to_msecs(ageing_jiffies) / 1000;
1281
1422 unsigned long ageing_jiffies = clock_t_to_jiffies(ageing_clock_t);
1423 u32 ageing_time = jiffies_to_msecs(ageing_jiffies) / 1000;
1424
1282 ocelot_write(ocelot, ANA_AUTOAGE_AGE_PERIOD(ageing_time / 2),
1283 ANA_AUTOAGE);
1425 ocelot_set_ageing_time(ocelot, ageing_time);
1284}
1285
1426}
1427
1286static void ocelot_port_attr_mc_set(struct ocelot_port *port, bool mc)
1428static void ocelot_port_attr_mc_set(struct ocelot *ocelot, int port, bool mc)
1287{
1429{
1288 struct ocelot *ocelot = port->ocelot;
1289 u32 val = ocelot_read_gix(ocelot, ANA_PORT_CPU_FWD_CFG,
1290 port->chip_port);
1430 u32 cpu_fwd_mcast = ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA |
1431 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA |
1432 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA;
1433 u32 val = 0;
1291
1292 if (mc)
1434
1435 if (mc)
1293 val |= ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA |
1294 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA |
1295 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA;
1296 else
1297 val &= ~(ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA |
1298 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA |
1299 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA);
1436 val = cpu_fwd_mcast;
1300
1437
1301 ocelot_write_gix(ocelot, val, ANA_PORT_CPU_FWD_CFG, port->chip_port);
1438 ocelot_rmw_gix(ocelot, val, cpu_fwd_mcast,
1439 ANA_PORT_CPU_FWD_CFG, port);
1302}
1303
1304static int ocelot_port_attr_set(struct net_device *dev,
1305 const struct switchdev_attr *attr,
1306 struct switchdev_trans *trans)
1307{
1440}
1441
1442static int ocelot_port_attr_set(struct net_device *dev,
1443 const struct switchdev_attr *attr,
1444 struct switchdev_trans *trans)
1445{
1308 struct ocelot_port *ocelot_port = netdev_priv(dev);
1446 struct ocelot_port_private *priv = netdev_priv(dev);
1447 struct ocelot *ocelot = priv->port.ocelot;
1448 int port = priv->chip_port;
1309 int err = 0;
1310
1311 switch (attr->id) {
1312 case SWITCHDEV_ATTR_ID_PORT_STP_STATE:
1449 int err = 0;
1450
1451 switch (attr->id) {
1452 case SWITCHDEV_ATTR_ID_PORT_STP_STATE:
1313 ocelot_port_attr_stp_state_set(ocelot_port, trans,
1453 ocelot_port_attr_stp_state_set(ocelot, port, trans,
1314 attr->u.stp_state);
1315 break;
1316 case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME:
1454 attr->u.stp_state);
1455 break;
1456 case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME:
1317 ocelot_port_attr_ageing_set(ocelot_port, attr->u.ageing_time);
1457 ocelot_port_attr_ageing_set(ocelot, port, attr->u.ageing_time);
1318 break;
1319 case SWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING:
1458 break;
1459 case SWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING:
1320 ocelot_port->vlan_aware = attr->u.vlan_filtering;
1321 ocelot_vlan_port_apply(ocelot_port->ocelot, ocelot_port);
1460 priv->vlan_aware = attr->u.vlan_filtering;
1461 ocelot_port_vlan_filtering(ocelot, port, priv->vlan_aware);
1322 break;
1323 case SWITCHDEV_ATTR_ID_BRIDGE_MC_DISABLED:
1462 break;
1463 case SWITCHDEV_ATTR_ID_BRIDGE_MC_DISABLED:
1324 ocelot_port_attr_mc_set(ocelot_port, !attr->u.mc_disabled);
1464 ocelot_port_attr_mc_set(ocelot, port, !attr->u.mc_disabled);
1325 break;
1326 default:
1327 err = -EOPNOTSUPP;
1328 break;
1329 }
1330
1331 return err;
1332}

--- 45 unchanged lines hidden (view full) ---

1378
1379 return NULL;
1380}
1381
1382static int ocelot_port_obj_add_mdb(struct net_device *dev,
1383 const struct switchdev_obj_port_mdb *mdb,
1384 struct switchdev_trans *trans)
1385{
1465 break;
1466 default:
1467 err = -EOPNOTSUPP;
1468 break;
1469 }
1470
1471 return err;
1472}

--- 45 unchanged lines hidden (view full) ---

1518
1519 return NULL;
1520}
1521
1522static int ocelot_port_obj_add_mdb(struct net_device *dev,
1523 const struct switchdev_obj_port_mdb *mdb,
1524 struct switchdev_trans *trans)
1525{
1386 struct ocelot_port *port = netdev_priv(dev);
1387 struct ocelot *ocelot = port->ocelot;
1388 struct ocelot_multicast *mc;
1526 struct ocelot_port_private *priv = netdev_priv(dev);
1527 struct ocelot_port *ocelot_port = &priv->port;
1528 struct ocelot *ocelot = ocelot_port->ocelot;
1389 unsigned char addr[ETH_ALEN];
1529 unsigned char addr[ETH_ALEN];
1530 struct ocelot_multicast *mc;
1531 int port = priv->chip_port;
1390 u16 vid = mdb->vid;
1391 bool new = false;
1392
1393 if (!vid)
1532 u16 vid = mdb->vid;
1533 bool new = false;
1534
1535 if (!vid)
1394 vid = port->pvid;
1536 vid = ocelot_port->pvid;
1395
1396 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1397 if (!mc) {
1398 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL);
1399 if (!mc)
1400 return -ENOMEM;
1401
1402 memcpy(mc->addr, mdb->addr, ETH_ALEN);

--- 7 unchanged lines hidden (view full) ---

1410 addr[0] = 0;
1411
1412 if (!new) {
1413 addr[2] = mc->ports << 0;
1414 addr[1] = mc->ports << 8;
1415 ocelot_mact_forget(ocelot, addr, vid);
1416 }
1417
1537
1538 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1539 if (!mc) {
1540 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL);
1541 if (!mc)
1542 return -ENOMEM;
1543
1544 memcpy(mc->addr, mdb->addr, ETH_ALEN);

--- 7 unchanged lines hidden (view full) ---

1552 addr[0] = 0;
1553
1554 if (!new) {
1555 addr[2] = mc->ports << 0;
1556 addr[1] = mc->ports << 8;
1557 ocelot_mact_forget(ocelot, addr, vid);
1558 }
1559
1418 mc->ports |= BIT(port->chip_port);
1560 mc->ports |= BIT(port);
1419 addr[2] = mc->ports << 0;
1420 addr[1] = mc->ports << 8;
1421
1422 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4);
1423}
1424
1425static int ocelot_port_obj_del_mdb(struct net_device *dev,
1426 const struct switchdev_obj_port_mdb *mdb)
1427{
1561 addr[2] = mc->ports << 0;
1562 addr[1] = mc->ports << 8;
1563
1564 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4);
1565}
1566
1567static int ocelot_port_obj_del_mdb(struct net_device *dev,
1568 const struct switchdev_obj_port_mdb *mdb)
1569{
1428 struct ocelot_port *port = netdev_priv(dev);
1429 struct ocelot *ocelot = port->ocelot;
1430 struct ocelot_multicast *mc;
1570 struct ocelot_port_private *priv = netdev_priv(dev);
1571 struct ocelot_port *ocelot_port = &priv->port;
1572 struct ocelot *ocelot = ocelot_port->ocelot;
1431 unsigned char addr[ETH_ALEN];
1573 unsigned char addr[ETH_ALEN];
1574 struct ocelot_multicast *mc;
1575 int port = priv->chip_port;
1432 u16 vid = mdb->vid;
1433
1434 if (!vid)
1576 u16 vid = mdb->vid;
1577
1578 if (!vid)
1435 vid = port->pvid;
1579 vid = ocelot_port->pvid;
1436
1437 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1438 if (!mc)
1439 return -ENOENT;
1440
1441 memcpy(addr, mc->addr, ETH_ALEN);
1442 addr[2] = mc->ports << 0;
1443 addr[1] = mc->ports << 8;
1444 addr[0] = 0;
1445 ocelot_mact_forget(ocelot, addr, vid);
1446
1580
1581 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1582 if (!mc)
1583 return -ENOENT;
1584
1585 memcpy(addr, mc->addr, ETH_ALEN);
1586 addr[2] = mc->ports << 0;
1587 addr[1] = mc->ports << 8;
1588 addr[0] = 0;
1589 ocelot_mact_forget(ocelot, addr, vid);
1590
1447 mc->ports &= ~BIT(port->chip_port);
1591 mc->ports &= ~BIT(port);
1448 if (!mc->ports) {
1449 list_del(&mc->list);
1450 devm_kfree(ocelot->dev, mc);
1451 return 0;
1452 }
1453
1454 addr[2] = mc->ports << 0;
1455 addr[1] = mc->ports << 8;

--- 40 unchanged lines hidden (view full) ---

1496 break;
1497 default:
1498 return -EOPNOTSUPP;
1499 }
1500
1501 return ret;
1502}
1503
1592 if (!mc->ports) {
1593 list_del(&mc->list);
1594 devm_kfree(ocelot->dev, mc);
1595 return 0;
1596 }
1597
1598 addr[2] = mc->ports << 0;
1599 addr[1] = mc->ports << 8;

--- 40 unchanged lines hidden (view full) ---

1640 break;
1641 default:
1642 return -EOPNOTSUPP;
1643 }
1644
1645 return ret;
1646}
1647
1504static int ocelot_port_bridge_join(struct ocelot_port *ocelot_port,
1648static int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
1505 struct net_device *bridge)
1506{
1649 struct net_device *bridge)
1650{
1507 struct ocelot *ocelot = ocelot_port->ocelot;
1508
1509 if (!ocelot->bridge_mask) {
1510 ocelot->hw_bridge_dev = bridge;
1511 } else {
1512 if (ocelot->hw_bridge_dev != bridge)
1513 /* This is adding the port to a second bridge, this is
1514 * unsupported */
1515 return -ENODEV;
1516 }
1517
1651 if (!ocelot->bridge_mask) {
1652 ocelot->hw_bridge_dev = bridge;
1653 } else {
1654 if (ocelot->hw_bridge_dev != bridge)
1655 /* This is adding the port to a second bridge, this is
1656 * unsupported */
1657 return -ENODEV;
1658 }
1659
1518 ocelot->bridge_mask |= BIT(ocelot_port->chip_port);
1660 ocelot->bridge_mask |= BIT(port);
1519
1520 return 0;
1521}
1522
1661
1662 return 0;
1663}
1664
1523static void ocelot_port_bridge_leave(struct ocelot_port *ocelot_port,
1524 struct net_device *bridge)
1665static int ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
1666 struct net_device *bridge)
1525{
1667{
1526 struct ocelot *ocelot = ocelot_port->ocelot;
1668 ocelot->bridge_mask &= ~BIT(port);
1527
1669
1528 ocelot->bridge_mask &= ~BIT(ocelot_port->chip_port);
1529
1530 if (!ocelot->bridge_mask)
1531 ocelot->hw_bridge_dev = NULL;
1532
1670 if (!ocelot->bridge_mask)
1671 ocelot->hw_bridge_dev = NULL;
1672
1533 /* Clear bridge vlan settings before calling ocelot_vlan_port_apply */
1534 ocelot_port->vlan_aware = 0;
1535 ocelot_port->pvid = 0;
1536 ocelot_port->vid = 0;
1673 ocelot_port_vlan_filtering(ocelot, port, 0);
1674 ocelot_port_set_pvid(ocelot, port, 0);
1675 return ocelot_port_set_native_vlan(ocelot, port, 0);
1537}
1538
1539static void ocelot_set_aggr_pgids(struct ocelot *ocelot)
1540{
1541 int i, port, lag;
1542
1543 /* Reset destination and aggregation PGIDS */
1544 for (port = 0; port < ocelot->num_phys_ports; port++)

--- 44 unchanged lines hidden (view full) ---

1589
1590 /* Use lag port as logical port for port i */
1591 ocelot_write_gix(ocelot, port_cfg |
1592 ANA_PORT_PORT_CFG_PORTID_VAL(lag),
1593 ANA_PORT_PORT_CFG, p);
1594 }
1595}
1596
1676}
1677
1678static void ocelot_set_aggr_pgids(struct ocelot *ocelot)
1679{
1680 int i, port, lag;
1681
1682 /* Reset destination and aggregation PGIDS */
1683 for (port = 0; port < ocelot->num_phys_ports; port++)

--- 44 unchanged lines hidden (view full) ---

1728
1729 /* Use lag port as logical port for port i */
1730 ocelot_write_gix(ocelot, port_cfg |
1731 ANA_PORT_PORT_CFG_PORTID_VAL(lag),
1732 ANA_PORT_PORT_CFG, p);
1733 }
1734}
1735
1597static int ocelot_port_lag_join(struct ocelot_port *ocelot_port,
1736static int ocelot_port_lag_join(struct ocelot *ocelot, int port,
1598 struct net_device *bond)
1599{
1737 struct net_device *bond)
1738{
1600 struct ocelot *ocelot = ocelot_port->ocelot;
1601 int p = ocelot_port->chip_port;
1602 int lag, lp;
1603 struct net_device *ndev;
1604 u32 bond_mask = 0;
1739 struct net_device *ndev;
1740 u32 bond_mask = 0;
1741 int lag, lp;
1605
1606 rcu_read_lock();
1607 for_each_netdev_in_bond_rcu(bond, ndev) {
1742
1743 rcu_read_lock();
1744 for_each_netdev_in_bond_rcu(bond, ndev) {
1608 struct ocelot_port *port = netdev_priv(ndev);
1745 struct ocelot_port_private *priv = netdev_priv(ndev);
1609
1746
1610 bond_mask |= BIT(port->chip_port);
1747 bond_mask |= BIT(priv->chip_port);
1611 }
1612 rcu_read_unlock();
1613
1614 lp = __ffs(bond_mask);
1615
1616 /* If the new port is the lowest one, use it as the logical port from
1617 * now on
1618 */
1748 }
1749 rcu_read_unlock();
1750
1751 lp = __ffs(bond_mask);
1752
1753 /* If the new port is the lowest one, use it as the logical port from
1754 * now on
1755 */
1619 if (p == lp) {
1620 lag = p;
1621 ocelot->lags[p] = bond_mask;
1622 bond_mask &= ~BIT(p);
1756 if (port == lp) {
1757 lag = port;
1758 ocelot->lags[port] = bond_mask;
1759 bond_mask &= ~BIT(port);
1623 if (bond_mask) {
1624 lp = __ffs(bond_mask);
1625 ocelot->lags[lp] = 0;
1626 }
1627 } else {
1628 lag = lp;
1760 if (bond_mask) {
1761 lp = __ffs(bond_mask);
1762 ocelot->lags[lp] = 0;
1763 }
1764 } else {
1765 lag = lp;
1629 ocelot->lags[lp] |= BIT(p);
1766 ocelot->lags[lp] |= BIT(port);
1630 }
1631
1632 ocelot_setup_lag(ocelot, lag);
1633 ocelot_set_aggr_pgids(ocelot);
1634
1635 return 0;
1636}
1637
1767 }
1768
1769 ocelot_setup_lag(ocelot, lag);
1770 ocelot_set_aggr_pgids(ocelot);
1771
1772 return 0;
1773}
1774
1638static void ocelot_port_lag_leave(struct ocelot_port *ocelot_port,
1775static void ocelot_port_lag_leave(struct ocelot *ocelot, int port,
1639 struct net_device *bond)
1640{
1776 struct net_device *bond)
1777{
1641 struct ocelot *ocelot = ocelot_port->ocelot;
1642 int p = ocelot_port->chip_port;
1643 u32 port_cfg;
1644 int i;
1645
1646 /* Remove port from any lag */
1647 for (i = 0; i < ocelot->num_phys_ports; i++)
1778 u32 port_cfg;
1779 int i;
1780
1781 /* Remove port from any lag */
1782 for (i = 0; i < ocelot->num_phys_ports; i++)
1648 ocelot->lags[i] &= ~BIT(ocelot_port->chip_port);
1783 ocelot->lags[i] &= ~BIT(port);
1649
1650 /* if it was the logical port of the lag, move the lag config to the
1651 * next port
1652 */
1784
1785 /* if it was the logical port of the lag, move the lag config to the
1786 * next port
1787 */
1653 if (ocelot->lags[p]) {
1654 int n = __ffs(ocelot->lags[p]);
1788 if (ocelot->lags[port]) {
1789 int n = __ffs(ocelot->lags[port]);
1655
1790
1656 ocelot->lags[n] = ocelot->lags[p];
1657 ocelot->lags[p] = 0;
1791 ocelot->lags[n] = ocelot->lags[port];
1792 ocelot->lags[port] = 0;
1658
1659 ocelot_setup_lag(ocelot, n);
1660 }
1661
1793
1794 ocelot_setup_lag(ocelot, n);
1795 }
1796
1662 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p);
1797 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port);
1663 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M;
1798 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M;
1664 ocelot_write_gix(ocelot, port_cfg | ANA_PORT_PORT_CFG_PORTID_VAL(p),
1665 ANA_PORT_PORT_CFG, p);
1799 ocelot_write_gix(ocelot, port_cfg | ANA_PORT_PORT_CFG_PORTID_VAL(port),
1800 ANA_PORT_PORT_CFG, port);
1666
1667 ocelot_set_aggr_pgids(ocelot);
1668}
1669
1670/* Checks if the net_device instance given to us originate from our driver. */
1671static bool ocelot_netdevice_dev_check(const struct net_device *dev)
1672{
1673 return dev->netdev_ops == &ocelot_port_netdev_ops;
1674}
1675
1676static int ocelot_netdevice_port_event(struct net_device *dev,
1677 unsigned long event,
1678 struct netdev_notifier_changeupper_info *info)
1679{
1801
1802 ocelot_set_aggr_pgids(ocelot);
1803}
1804
1805/* Checks if the net_device instance given to us originate from our driver. */
1806static bool ocelot_netdevice_dev_check(const struct net_device *dev)
1807{
1808 return dev->netdev_ops == &ocelot_port_netdev_ops;
1809}
1810
1811static int ocelot_netdevice_port_event(struct net_device *dev,
1812 unsigned long event,
1813 struct netdev_notifier_changeupper_info *info)
1814{
1680 struct ocelot_port *ocelot_port = netdev_priv(dev);
1815 struct ocelot_port_private *priv = netdev_priv(dev);
1816 struct ocelot_port *ocelot_port = &priv->port;
1817 struct ocelot *ocelot = ocelot_port->ocelot;
1818 int port = priv->chip_port;
1681 int err = 0;
1682
1683 switch (event) {
1684 case NETDEV_CHANGEUPPER:
1685 if (netif_is_bridge_master(info->upper_dev)) {
1819 int err = 0;
1820
1821 switch (event) {
1822 case NETDEV_CHANGEUPPER:
1823 if (netif_is_bridge_master(info->upper_dev)) {
1686 if (info->linking)
1687 err = ocelot_port_bridge_join(ocelot_port,
1824 if (info->linking) {
1825 err = ocelot_port_bridge_join(ocelot, port,
1688 info->upper_dev);
1826 info->upper_dev);
1689 else
1690 ocelot_port_bridge_leave(ocelot_port,
1691 info->upper_dev);
1692
1693 ocelot_vlan_port_apply(ocelot_port->ocelot,
1694 ocelot_port);
1827 } else {
1828 err = ocelot_port_bridge_leave(ocelot, port,
1829 info->upper_dev);
1830 priv->vlan_aware = false;
1831 }
1695 }
1696 if (netif_is_lag_master(info->upper_dev)) {
1697 if (info->linking)
1832 }
1833 if (netif_is_lag_master(info->upper_dev)) {
1834 if (info->linking)
1698 err = ocelot_port_lag_join(ocelot_port,
1835 err = ocelot_port_lag_join(ocelot, port,
1699 info->upper_dev);
1700 else
1836 info->upper_dev);
1837 else
1701 ocelot_port_lag_leave(ocelot_port,
1838 ocelot_port_lag_leave(ocelot, port,
1702 info->upper_dev);
1703 }
1704 break;
1705 default:
1706 break;
1707 }
1708
1709 return err;

--- 286 unchanged lines hidden (view full) ---

1996 /* There is no device reconfiguration, PTP Rx stamping is always
1997 * enabled.
1998 */
1999 ocelot->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
2000
2001 return 0;
2002}
2003
1839 info->upper_dev);
1840 }
1841 break;
1842 default:
1843 break;
1844 }
1845
1846 return err;

--- 286 unchanged lines hidden (view full) ---

2133 /* There is no device reconfiguration, PTP Rx stamping is always
2134 * enabled.
2135 */
2136 ocelot->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
2137
2138 return 0;
2139}
2140
2141static void ocelot_init_port(struct ocelot *ocelot, int port)
2142{
2143 struct ocelot_port *ocelot_port = ocelot->ports[port];
2144
2145 INIT_LIST_HEAD(&ocelot_port->skbs);
2146
2147 /* Basic L2 initialization */
2148
2149 /* Drop frames with multicast source address */
2150 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
2151 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
2152 ANA_PORT_DROP_CFG, port);
2153
2154 /* Set default VLAN and tag type to 8021Q. */
2155 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q),
2156 REW_PORT_VLAN_CFG_PORT_TPID_M,
2157 REW_PORT_VLAN_CFG, port);
2158
2159 /* Enable vcap lookups */
2160 ocelot_vcap_enable(ocelot, port);
2161}
2162
2004int ocelot_probe_port(struct ocelot *ocelot, u8 port,
2005 void __iomem *regs,
2006 struct phy_device *phy)
2007{
2163int ocelot_probe_port(struct ocelot *ocelot, u8 port,
2164 void __iomem *regs,
2165 struct phy_device *phy)
2166{
2167 struct ocelot_port_private *priv;
2008 struct ocelot_port *ocelot_port;
2009 struct net_device *dev;
2010 int err;
2011
2168 struct ocelot_port *ocelot_port;
2169 struct net_device *dev;
2170 int err;
2171
2012 dev = alloc_etherdev(sizeof(struct ocelot_port));
2172 dev = alloc_etherdev(sizeof(struct ocelot_port_private));
2013 if (!dev)
2014 return -ENOMEM;
2015 SET_NETDEV_DEV(dev, ocelot->dev);
2173 if (!dev)
2174 return -ENOMEM;
2175 SET_NETDEV_DEV(dev, ocelot->dev);
2016 ocelot_port = netdev_priv(dev);
2017 ocelot_port->dev = dev;
2176 priv = netdev_priv(dev);
2177 priv->dev = dev;
2178 priv->phy = phy;
2179 priv->chip_port = port;
2180 ocelot_port = &priv->port;
2018 ocelot_port->ocelot = ocelot;
2019 ocelot_port->regs = regs;
2181 ocelot_port->ocelot = ocelot;
2182 ocelot_port->regs = regs;
2020 ocelot_port->chip_port = port;
2021 ocelot_port->phy = phy;
2022 ocelot->ports[port] = ocelot_port;
2023
2024 dev->netdev_ops = &ocelot_port_netdev_ops;
2025 dev->ethtool_ops = &ocelot_ethtool_ops;
2026
2027 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_RXFCS |
2028 NETIF_F_HW_TC;
2029 dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2030
2031 memcpy(dev->dev_addr, ocelot->base_mac, ETH_ALEN);
2032 dev->dev_addr[ETH_ALEN - 1] += port;
2033 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, ocelot_port->pvid,
2034 ENTRYTYPE_LOCKED);
2035
2183 ocelot->ports[port] = ocelot_port;
2184
2185 dev->netdev_ops = &ocelot_port_netdev_ops;
2186 dev->ethtool_ops = &ocelot_ethtool_ops;
2187
2188 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_RXFCS |
2189 NETIF_F_HW_TC;
2190 dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2191
2192 memcpy(dev->dev_addr, ocelot->base_mac, ETH_ALEN);
2193 dev->dev_addr[ETH_ALEN - 1] += port;
2194 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, ocelot_port->pvid,
2195 ENTRYTYPE_LOCKED);
2196
2036 INIT_LIST_HEAD(&ocelot_port->skbs);
2197 ocelot_init_port(ocelot, port);
2037
2038 err = register_netdev(dev);
2039 if (err) {
2040 dev_err(ocelot->dev, "register_netdev failed\n");
2198
2199 err = register_netdev(dev);
2200 if (err) {
2201 dev_err(ocelot->dev, "register_netdev failed\n");
2041 goto err_register_netdev;
2202 free_netdev(dev);
2042 }
2043
2203 }
2204
2044 /* Basic L2 initialization */
2045 ocelot_vlan_port_apply(ocelot, ocelot_port);
2205 return err;
2206}
2207EXPORT_SYMBOL(ocelot_probe_port);
2046
2208
2047 /* Enable vcap lookups */
2048 ocelot_vcap_enable(ocelot, ocelot_port);
2209void ocelot_set_cpu_port(struct ocelot *ocelot, int cpu,
2210 enum ocelot_tag_prefix injection,
2211 enum ocelot_tag_prefix extraction)
2212{
2213 /* Configure and enable the CPU port. */
2214 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu);
2215 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU);
2216 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA |
2217 ANA_PORT_PORT_CFG_PORTID_VAL(cpu),
2218 ANA_PORT_PORT_CFG, cpu);
2049
2219
2050 return 0;
2220 /* If the CPU port is a physical port, set up the port in Node
2221 * Processor Interface (NPI) mode. This is the mode through which
2222 * frames can be injected from and extracted to an external CPU.
2223 * Only one port can be an NPI at the same time.
2224 */
2225 if (cpu < ocelot->num_phys_ports) {
2226 ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M |
2227 QSYS_EXT_CPU_CFG_EXT_CPU_PORT(cpu),
2228 QSYS_EXT_CPU_CFG);
2229 }
2051
2230
2052err_register_netdev:
2053 free_netdev(dev);
2054 return err;
2231 /* CPU port Injection/Extraction configuration */
2232 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |
2233 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
2234 QSYS_SWITCH_PORT_MODE_PORT_ENA,
2235 QSYS_SWITCH_PORT_MODE, cpu);
2236 ocelot_write_rix(ocelot, SYS_PORT_MODE_INCL_XTR_HDR(extraction) |
2237 SYS_PORT_MODE_INCL_INJ_HDR(injection),
2238 SYS_PORT_MODE, cpu);
2239
2240 /* Configure the CPU port to be VLAN aware */
2241 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) |
2242 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
2243 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1),
2244 ANA_PORT_VLAN_CFG, cpu);
2245
2246 ocelot->cpu = cpu;
2055}
2247}
2056EXPORT_SYMBOL(ocelot_probe_port);
2248EXPORT_SYMBOL(ocelot_set_cpu_port);
2057
2058int ocelot_init(struct ocelot *ocelot)
2059{
2249
2250int ocelot_init(struct ocelot *ocelot)
2251{
2060 u32 port;
2061 int i, ret, cpu = ocelot->num_phys_ports;
2062 char queue_name[32];
2252 char queue_name[32];
2253 int i, ret;
2254 u32 port;
2063
2064 ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports,
2065 sizeof(u32), GFP_KERNEL);
2066 if (!ocelot->lags)
2067 return -ENOMEM;
2068
2069 ocelot->stats = devm_kcalloc(ocelot->dev,
2070 ocelot->num_phys_ports * ocelot->num_stats,

--- 5 unchanged lines hidden (view full) ---

2076 mutex_init(&ocelot->ptp_lock);
2077 spin_lock_init(&ocelot->ptp_clock_lock);
2078 snprintf(queue_name, sizeof(queue_name), "%s-stats",
2079 dev_name(ocelot->dev));
2080 ocelot->stats_queue = create_singlethread_workqueue(queue_name);
2081 if (!ocelot->stats_queue)
2082 return -ENOMEM;
2083
2255
2256 ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports,
2257 sizeof(u32), GFP_KERNEL);
2258 if (!ocelot->lags)
2259 return -ENOMEM;
2260
2261 ocelot->stats = devm_kcalloc(ocelot->dev,
2262 ocelot->num_phys_ports * ocelot->num_stats,

--- 5 unchanged lines hidden (view full) ---

2268 mutex_init(&ocelot->ptp_lock);
2269 spin_lock_init(&ocelot->ptp_clock_lock);
2270 snprintf(queue_name, sizeof(queue_name), "%s-stats",
2271 dev_name(ocelot->dev));
2272 ocelot->stats_queue = create_singlethread_workqueue(queue_name);
2273 if (!ocelot->stats_queue)
2274 return -ENOMEM;
2275
2276 INIT_LIST_HEAD(&ocelot->multicast);
2084 ocelot_mact_init(ocelot);
2085 ocelot_vlan_init(ocelot);
2086 ocelot_ace_init(ocelot);
2087
2088 for (port = 0; port < ocelot->num_phys_ports; port++) {
2089 /* Clear all counters (5 groups) */
2090 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) |
2091 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f),

--- 41 unchanged lines hidden (view full) ---

2133 ocelot_write_gix(ocelot,
2134 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff),
2135 ANA_PORT_CPU_FWD_BPDU_CFG,
2136 port);
2137 /* Ensure bridging is disabled */
2138 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port);
2139 }
2140
2277 ocelot_mact_init(ocelot);
2278 ocelot_vlan_init(ocelot);
2279 ocelot_ace_init(ocelot);
2280
2281 for (port = 0; port < ocelot->num_phys_ports; port++) {
2282 /* Clear all counters (5 groups) */
2283 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) |
2284 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f),

--- 41 unchanged lines hidden (view full) ---

2326 ocelot_write_gix(ocelot,
2327 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff),
2328 ANA_PORT_CPU_FWD_BPDU_CFG,
2329 port);
2330 /* Ensure bridging is disabled */
2331 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port);
2332 }
2333
2141 /* Configure and enable the CPU port. */
2142 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu);
2143 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU);
2144 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA |
2145 ANA_PORT_PORT_CFG_PORTID_VAL(cpu),
2146 ANA_PORT_PORT_CFG, cpu);
2147
2148 /* Allow broadcast MAC frames. */
2149 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) {
2150 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0));
2151
2152 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
2153 }
2154 ocelot_write_rix(ocelot,
2155 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)),
2156 ANA_PGID_PGID, PGID_MC);
2157 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4);
2158 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6);
2159
2334 /* Allow broadcast MAC frames. */
2335 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) {
2336 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0));
2337
2338 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
2339 }
2340 ocelot_write_rix(ocelot,
2341 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)),
2342 ANA_PGID_PGID, PGID_MC);
2343 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4);
2344 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6);
2345
2160 /* CPU port Injection/Extraction configuration */
2161 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |
2162 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
2163 QSYS_SWITCH_PORT_MODE_PORT_ENA,
2164 QSYS_SWITCH_PORT_MODE, cpu);
2165 ocelot_write_rix(ocelot, SYS_PORT_MODE_INCL_XTR_HDR(1) |
2166 SYS_PORT_MODE_INCL_INJ_HDR(1), SYS_PORT_MODE, cpu);
2167 /* Allow manual injection via DEVCPU_QS registers, and byte swap these
2168 * registers endianness.
2169 */
2170 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP |
2171 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0);
2172 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP |
2173 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0);
2174 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) |

--- 57 unchanged lines hidden --- 		2346 /* Allow manual injection via DEVCPU_QS registers, and byte swap these
2347 * registers endianness.
2348 */
2349 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP |
2350 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0);
2351 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP |
2352 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0);
2353 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) |

--- 57 unchanged lines hidden ---