ocelot.c (b360d94f1b8647bc164e7519ec900471836be14a) ocelot.c (421741ea5672cf16fa551bcde23e327075ed419e)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7#include <linux/if_bridge.h>
8#include <soc/mscc/ocelot_vcap.h>

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1033
1034 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port);
1035 }
1036}
1037EXPORT_SYMBOL(ocelot_apply_bridge_fwd_mask);
1038
1039void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state)
1040{
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7#include <linux/if_bridge.h>
8#include <soc/mscc/ocelot_vcap.h>

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1033
1034 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port);
1035 }
1036}
1037EXPORT_SYMBOL(ocelot_apply_bridge_fwd_mask);
1038
1039void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state)
1040{
1041 struct ocelot_port *ocelot_port = ocelot->ports[port];
1041 u32 port_cfg;
1042
1043 if (!(BIT(port) & ocelot->bridge_mask))
1044 return;
1045
1046 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port);
1047
1048 switch (state) {
1049 case BR_STATE_FORWARDING:
1050 ocelot->bridge_fwd_mask |= BIT(port);
1051 fallthrough;
1052 case BR_STATE_LEARNING:
1042 u32 port_cfg;
1043
1044 if (!(BIT(port) & ocelot->bridge_mask))
1045 return;
1046
1047 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port);
1048
1049 switch (state) {
1050 case BR_STATE_FORWARDING:
1051 ocelot->bridge_fwd_mask |= BIT(port);
1052 fallthrough;
1053 case BR_STATE_LEARNING:
1053 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA;
1054 if (ocelot_port->learn_ena)
1055 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA;
1054 break;
1055
1056 default:
1057 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA;
1058 ocelot->bridge_fwd_mask &= ~BIT(port);
1059 break;
1060 }
1061

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1529 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG)
1530 max_mtu -= OCELOT_LONG_PREFIX_LEN;
1531 }
1532
1533 return max_mtu;
1534}
1535EXPORT_SYMBOL(ocelot_get_max_mtu);
1536
1056 break;
1057
1058 default:
1059 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA;
1060 ocelot->bridge_fwd_mask &= ~BIT(port);
1061 break;
1062 }
1063

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1531 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG)
1532 max_mtu -= OCELOT_LONG_PREFIX_LEN;
1533 }
1534
1535 return max_mtu;
1536}
1537EXPORT_SYMBOL(ocelot_get_max_mtu);
1538
1539static void ocelot_port_set_learning(struct ocelot *ocelot, int port,
1540 bool enabled)
1541{
1542 struct ocelot_port *ocelot_port = ocelot->ports[port];
1543 u32 val = 0;
1544
1545 if (enabled)
1546 val = ANA_PORT_PORT_CFG_LEARN_ENA;
1547
1548 ocelot_rmw_gix(ocelot, val, ANA_PORT_PORT_CFG_LEARN_ENA,
1549 ANA_PORT_PORT_CFG, port);
1550
1551 ocelot_port->learn_ena = enabled;
1552}
1553
1554static void ocelot_port_set_ucast_flood(struct ocelot *ocelot, int port,
1555 bool enabled)
1556{
1557 u32 val = 0;
1558
1559 if (enabled)
1560 val = BIT(port);
1561
1562 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_UC);
1563}
1564
1565static void ocelot_port_set_mcast_flood(struct ocelot *ocelot, int port,
1566 bool enabled)
1567{
1568 u32 val = 0;
1569
1570 if (enabled)
1571 val = BIT(port);
1572
1573 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MC);
1574}
1575
1576static void ocelot_port_set_bcast_flood(struct ocelot *ocelot, int port,
1577 bool enabled)
1578{
1579 u32 val = 0;
1580
1581 if (enabled)
1582 val = BIT(port);
1583
1584 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_BC);
1585}
1586
1587int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port,
1588 struct switchdev_brport_flags flags)
1589{
1590 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
1591 BR_BCAST_FLOOD))
1592 return -EINVAL;
1593
1594 return 0;
1595}
1596EXPORT_SYMBOL(ocelot_port_pre_bridge_flags);
1597
1598void ocelot_port_bridge_flags(struct ocelot *ocelot, int port,
1599 struct switchdev_brport_flags flags)
1600{
1601 if (flags.mask & BR_LEARNING)
1602 ocelot_port_set_learning(ocelot, port,
1603 !!(flags.val & BR_LEARNING));
1604
1605 if (flags.mask & BR_FLOOD)
1606 ocelot_port_set_ucast_flood(ocelot, port,
1607 !!(flags.val & BR_FLOOD));
1608
1609 if (flags.mask & BR_MCAST_FLOOD)
1610 ocelot_port_set_mcast_flood(ocelot, port,
1611 !!(flags.val & BR_MCAST_FLOOD));
1612
1613 if (flags.mask & BR_BCAST_FLOOD)
1614 ocelot_port_set_bcast_flood(ocelot, port,
1615 !!(flags.val & BR_BCAST_FLOOD));
1616}
1617EXPORT_SYMBOL(ocelot_port_bridge_flags);
1618
1537void ocelot_init_port(struct ocelot *ocelot, int port)
1538{
1539 struct ocelot_port *ocelot_port = ocelot->ports[port];
1540
1541 skb_queue_head_init(&ocelot_port->tx_skbs);
1542 spin_lock_init(&ocelot_port->ts_id_lock);
1543
1544 /* Basic L2 initialization */

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1578 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
1579 ANA_PORT_DROP_CFG, port);
1580
1581 /* Set default VLAN and tag type to 8021Q. */
1582 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q),
1583 REW_PORT_VLAN_CFG_PORT_TPID_M,
1584 REW_PORT_VLAN_CFG, port);
1585
1619void ocelot_init_port(struct ocelot *ocelot, int port)
1620{
1621 struct ocelot_port *ocelot_port = ocelot->ports[port];
1622
1623 skb_queue_head_init(&ocelot_port->tx_skbs);
1624 spin_lock_init(&ocelot_port->ts_id_lock);
1625
1626 /* Basic L2 initialization */

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1660 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
1661 ANA_PORT_DROP_CFG, port);
1662
1663 /* Set default VLAN and tag type to 8021Q. */
1664 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q),
1665 REW_PORT_VLAN_CFG_PORT_TPID_M,
1666 REW_PORT_VLAN_CFG, port);
1667
1668 /* Disable source address learning for standalone mode */
1669 ocelot_port_set_learning(ocelot, port, false);
1670
1586 /* Enable vcap lookups */
1587 ocelot_vcap_enable(ocelot, port);
1588}
1589EXPORT_SYMBOL(ocelot_init_port);
1590
1591/* Configure and enable the CPU port module, which is a set of queues
1592 * accessible through register MMIO, frame DMA or Ethernet (in case
1593 * NPI mode is used).

--- 208 unchanged lines hidden --- 		1671 /* Enable vcap lookups */
1672 ocelot_vcap_enable(ocelot, port);
1673}
1674EXPORT_SYMBOL(ocelot_init_port);
1675
1676/* Configure and enable the CPU port module, which is a set of queues
1677 * accessible through register MMIO, frame DMA or Ethernet (in case
1678 * NPI mode is used).

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