reg.h (242e696e035fca96e972773023f20adfba124d10) reg.h (c934757d90000a9d3779d2b436a70e3d060ef693)
1/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2/* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
3
4#ifndef _MLXSW_REG_H
5#define _MLXSW_REG_H
6
7#include <linux/kernel.h>
8#include <linux/string.h>

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156 * that are available in the system (external ports).
157 *
158 * Currently, only single-ASIC configurations are supported, so we default to
159 * 1:1 mapping between system ports and local ports.
160 * Access: Index
161 */
162MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
163
1/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2/* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
3
4#ifndef _MLXSW_REG_H
5#define _MLXSW_REG_H
6
7#include <linux/kernel.h>
8#include <linux/string.h>

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156 * that are available in the system (external ports).
157 *
158 * Currently, only single-ASIC configurations are supported, so we default to
159 * 1:1 mapping between system ports and local ports.
160 * Access: Index
161 */
162MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
163
164static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port)
164static inline void mlxsw_reg_sspr_pack(char *payload, u16 local_port)
165{
166 MLXSW_REG_ZERO(sspr, payload);
167 mlxsw_reg_sspr_m_set(payload, 1);
168 mlxsw_reg_sspr_local_port_set(payload, local_port);
169 mlxsw_reg_sspr_sub_port_set(payload, 0);
170 mlxsw_reg_sspr_system_port_set(payload, local_port);
171}
172

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402 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
403 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
404}
405
406static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
407 enum mlxsw_reg_sfd_rec_policy policy,
408 const char *mac, u16 fid_vid,
409 enum mlxsw_reg_sfd_rec_action action,
165{
166 MLXSW_REG_ZERO(sspr, payload);
167 mlxsw_reg_sspr_m_set(payload, 1);
168 mlxsw_reg_sspr_local_port_set(payload, local_port);
169 mlxsw_reg_sspr_sub_port_set(payload, 0);
170 mlxsw_reg_sspr_system_port_set(payload, local_port);
171}
172

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402 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
403 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
404}
405
406static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
407 enum mlxsw_reg_sfd_rec_policy policy,
408 const char *mac, u16 fid_vid,
409 enum mlxsw_reg_sfd_rec_action action,
410 u8 local_port)
410 u16 local_port)
411{
412 mlxsw_reg_sfd_rec_pack(payload, rec_index,
413 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action);
414 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
415 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
416 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid);
417 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
418}

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669 * Unique port identifier for the final destination of the packet.
670 * Access: RO
671 */
672MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
673 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
674
675static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
676 char *mac, u16 *p_vid,
411{
412 mlxsw_reg_sfd_rec_pack(payload, rec_index,
413 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action);
414 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
415 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
416 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid);
417 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
418}

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669 * Unique port identifier for the final destination of the packet.
670 * Access: RO
671 */
672MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
673 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
674
675static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
676 char *mac, u16 *p_vid,
677 u8 *p_local_port)
677 u16 *p_local_port)
678{
679 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
680 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
681 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
682}
683
684/* reg_sfn_mac_lag_lag_id
685 * LAG ID (pointer into the LAG descriptor table).

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777 * 0 - Do not change spanning tree state (used only when writing).
778 * 1 - Discarding. No learning or forwarding to/from this port (default).
779 * 2 - Learning. Port is learning, but not forwarding.
780 * 3 - Forwarding. Port is learning and forwarding.
781 * Access: RW
782 */
783MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
784
678{
679 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
680 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
681 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
682}
683
684/* reg_sfn_mac_lag_lag_id
685 * LAG ID (pointer into the LAG descriptor table).

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777 * 0 - Do not change spanning tree state (used only when writing).
778 * 1 - Discarding. No learning or forwarding to/from this port (default).
779 * 2 - Learning. Port is learning, but not forwarding.
780 * 3 - Forwarding. Port is learning and forwarding.
781 * Access: RW
782 */
783MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
784
785static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port)
785static inline void mlxsw_reg_spms_pack(char *payload, u16 local_port)
786{
787 MLXSW_REG_ZERO(spms, payload);
788 mlxsw_reg_spms_local_port_set(payload, local_port);
789}
790
791static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
792 enum mlxsw_reg_spms_state state)
793{

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845MLXSW_ITEM32(reg, spvid, et_vlan, 0x04, 16, 2);
846
847/* reg_spvid_pvid
848 * Port default VID
849 * Access: RW
850 */
851MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
852
786{
787 MLXSW_REG_ZERO(spms, payload);
788 mlxsw_reg_spms_local_port_set(payload, local_port);
789}
790
791static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
792 enum mlxsw_reg_spms_state state)
793{

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845MLXSW_ITEM32(reg, spvid, et_vlan, 0x04, 16, 2);
846
847/* reg_spvid_pvid
848 * Port default VID
849 * Access: RW
850 */
851MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
852
853static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid,
853static inline void mlxsw_reg_spvid_pack(char *payload, u16 local_port, u16 pvid,
854 u8 et_vlan)
855{
856 MLXSW_REG_ZERO(spvid, payload);
857 mlxsw_reg_spvid_local_port_set(payload, local_port);
858 mlxsw_reg_spvid_pvid_set(payload, pvid);
859 mlxsw_reg_spvid_et_vlan_set(payload, et_vlan);
860}
861

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936/* reg_spvm_rec_vid
937 * Egress membership in VLAN ID.
938 * Access: Index
939 */
940MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
941 MLXSW_REG_SPVM_BASE_LEN, 0, 12,
942 MLXSW_REG_SPVM_REC_LEN, 0, false);
943
854 u8 et_vlan)
855{
856 MLXSW_REG_ZERO(spvid, payload);
857 mlxsw_reg_spvid_local_port_set(payload, local_port);
858 mlxsw_reg_spvid_pvid_set(payload, pvid);
859 mlxsw_reg_spvid_et_vlan_set(payload, et_vlan);
860}
861

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936/* reg_spvm_rec_vid
937 * Egress membership in VLAN ID.
938 * Access: Index
939 */
940MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
941 MLXSW_REG_SPVM_BASE_LEN, 0, 12,
942 MLXSW_REG_SPVM_REC_LEN, 0, false);
943
944static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port,
944static inline void mlxsw_reg_spvm_pack(char *payload, u16 local_port,
945 u16 vid_begin, u16 vid_end,
946 bool is_member, bool untagged)
947{
948 int size = vid_end - vid_begin + 1;
949 int i;
950
951 MLXSW_REG_ZERO(spvm, payload);
952 mlxsw_reg_spvm_local_port_set(payload, local_port);

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998MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
999
1000/* reg_spaft_allow_tagged
1001 * When set, tagged frames on the ingress are allowed (default).
1002 * Access: RW
1003 */
1004MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
1005
945 u16 vid_begin, u16 vid_end,
946 bool is_member, bool untagged)
947{
948 int size = vid_end - vid_begin + 1;
949 int i;
950
951 MLXSW_REG_ZERO(spvm, payload);
952 mlxsw_reg_spvm_local_port_set(payload, local_port);

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998MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
999
1000/* reg_spaft_allow_tagged
1001 * When set, tagged frames on the ingress are allowed (default).
1002 * Access: RW
1003 */
1004MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
1005
1006static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port,
1006static inline void mlxsw_reg_spaft_pack(char *payload, u16 local_port,
1007 bool allow_untagged)
1008{
1009 MLXSW_REG_ZERO(spaft, payload);
1010 mlxsw_reg_spaft_local_port_set(payload, local_port);
1011 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged);
1012 mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged);
1013 mlxsw_reg_spaft_allow_tagged_set(payload, true);
1014}

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1324
1325/* reg_sldr_system_port
1326 * System port.
1327 * Access: RW
1328 */
1329MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
1330
1331static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,
1007 bool allow_untagged)
1008{
1009 MLXSW_REG_ZERO(spaft, payload);
1010 mlxsw_reg_spaft_local_port_set(payload, local_port);
1011 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged);
1012 mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged);
1013 mlxsw_reg_spaft_allow_tagged_set(payload, true);
1014}

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1324
1325/* reg_sldr_system_port
1326 * System port.
1327 * Access: RW
1328 */
1329MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
1330
1331static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,
1332 u8 local_port)
1332 u16 local_port)
1333{
1334 MLXSW_REG_ZERO(sldr, payload);
1335 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);
1336 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1337 mlxsw_reg_sldr_num_ports_set(payload, 1);
1338 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1339}
1340
1341static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,
1333{
1334 MLXSW_REG_ZERO(sldr, payload);
1335 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);
1336 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1337 mlxsw_reg_sldr_num_ports_set(payload, 1);
1338 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1339}
1340
1341static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,
1342 u8 local_port)
1342 u16 local_port)
1343{
1344 MLXSW_REG_ZERO(sldr, payload);
1345 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);
1346 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1347 mlxsw_reg_sldr_num_ports_set(payload, 1);
1348 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1349}
1350

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1508/* reg_slcor_port_index
1509 * Port index in the LAG list. Only valid on Add Port to LAG col.
1510 * Valid range is from 0 to cap_max_lag_members-1
1511 * Access: RW
1512 */
1513MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
1514
1515static inline void mlxsw_reg_slcor_pack(char *payload,
1343{
1344 MLXSW_REG_ZERO(sldr, payload);
1345 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);
1346 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1347 mlxsw_reg_sldr_num_ports_set(payload, 1);
1348 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1349}
1350

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1508/* reg_slcor_port_index
1509 * Port index in the LAG list. Only valid on Add Port to LAG col.
1510 * Valid range is from 0 to cap_max_lag_members-1
1511 * Access: RW
1512 */
1513MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
1514
1515static inline void mlxsw_reg_slcor_pack(char *payload,
1516 u8 local_port, u16 lag_id,
1516 u16 local_port, u16 lag_id,
1517 enum mlxsw_reg_slcor_col col)
1518{
1519 MLXSW_REG_ZERO(slcor, payload);
1520 mlxsw_reg_slcor_col_set(payload, col);
1521 mlxsw_reg_slcor_local_port_set(payload, local_port);
1522 mlxsw_reg_slcor_lag_id_set(payload, lag_id);
1523}
1524
1525static inline void mlxsw_reg_slcor_port_add_pack(char *payload,
1517 enum mlxsw_reg_slcor_col col)
1518{
1519 MLXSW_REG_ZERO(slcor, payload);
1520 mlxsw_reg_slcor_col_set(payload, col);
1521 mlxsw_reg_slcor_local_port_set(payload, local_port);
1522 mlxsw_reg_slcor_lag_id_set(payload, lag_id);
1523}
1524
1525static inline void mlxsw_reg_slcor_port_add_pack(char *payload,
1526 u8 local_port, u16 lag_id,
1526 u16 local_port, u16 lag_id,
1527 u8 port_index)
1528{
1529 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1530 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);
1531 mlxsw_reg_slcor_port_index_set(payload, port_index);
1532}
1533
1534static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,
1527 u8 port_index)
1528{
1529 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1530 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);
1531 mlxsw_reg_slcor_port_index_set(payload, port_index);
1532}
1533
1534static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,
1535 u8 local_port, u16 lag_id)
1535 u16 local_port, u16 lag_id)
1536{
1537 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1538 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);
1539}
1540
1541static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,
1536{
1537 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1538 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);
1539}
1540
1541static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,
1542 u8 local_port, u16 lag_id)
1542 u16 local_port, u16 lag_id)
1543{
1544 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1545 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1546}
1547
1548static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,
1543{
1544 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1545 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1546}
1547
1548static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,
1549 u8 local_port, u16 lag_id)
1549 u16 local_port, u16 lag_id)
1550{
1551 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1552 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1553}
1554
1555/* SPMLR - Switch Port MAC Learning Register
1556 * -----------------------------------------
1557 * Controls the Switch MAC learning policy per port.

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1588 *
1589 * In security mode the switch does not learn MACs on the port, but uses the
1590 * SMAC to see if it exists on another ingress port. If so, the packet is
1591 * classified as a bad packet and is discarded unless the software registers
1592 * to receive port security error packets usign HPKT.
1593 */
1594MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
1595
1550{
1551 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1552 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1553}
1554
1555/* SPMLR - Switch Port MAC Learning Register
1556 * -----------------------------------------
1557 * Controls the Switch MAC learning policy per port.

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1588 *
1589 * In security mode the switch does not learn MACs on the port, but uses the
1590 * SMAC to see if it exists on another ingress port. If so, the packet is
1591 * classified as a bad packet and is discarded unless the software registers
1592 * to receive port security error packets usign HPKT.
1593 */
1594MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
1595
1596static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port,
1596static inline void mlxsw_reg_spmlr_pack(char *payload, u16 local_port,
1597 enum mlxsw_reg_spmlr_learn_mode mode)
1598{
1599 MLXSW_REG_ZERO(spmlr, payload);
1600 mlxsw_reg_spmlr_local_port_set(payload, local_port);
1601 mlxsw_reg_spmlr_sub_port_set(payload, 0);
1602 mlxsw_reg_spmlr_learn_mode_set(payload, mode);
1603}
1604

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1673/* reg_svfa_counter_index
1674 * Counter index for flow counters.
1675 * Access: RW
1676 *
1677 * Note: Reserved for SwitchX-2.
1678 */
1679MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1680
1597 enum mlxsw_reg_spmlr_learn_mode mode)
1598{
1599 MLXSW_REG_ZERO(spmlr, payload);
1600 mlxsw_reg_spmlr_local_port_set(payload, local_port);
1601 mlxsw_reg_spmlr_sub_port_set(payload, 0);
1602 mlxsw_reg_spmlr_learn_mode_set(payload, mode);
1603}
1604

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1673/* reg_svfa_counter_index
1674 * Counter index for flow counters.
1675 * Access: RW
1676 *
1677 * Note: Reserved for SwitchX-2.
1678 */
1679MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1680
1681static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port,
1681static inline void mlxsw_reg_svfa_pack(char *payload, u16 local_port,
1682 enum mlxsw_reg_svfa_mt mt, bool valid,
1683 u16 fid, u16 vid)
1684{
1685 MLXSW_REG_ZERO(svfa, payload);
1686 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port;
1687 mlxsw_reg_svfa_swid_set(payload, 0);
1688 mlxsw_reg_svfa_local_port_set(payload, local_port);
1689 mlxsw_reg_svfa_mapping_table_set(payload, mt);

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1780/* reg_spvtr_epvid_mode
1781 * Egress Port VLAN-ID Mode.
1782 * For Spectrum family, this affects the values of SPVM.e,u,pt.
1783 * Access: WO
1784 */
1785MLXSW_ITEM32(reg, spvtr, epvid_mode, 0x04, 0, 4);
1786
1787static inline void mlxsw_reg_spvtr_pack(char *payload, bool tport,
1682 enum mlxsw_reg_svfa_mt mt, bool valid,
1683 u16 fid, u16 vid)
1684{
1685 MLXSW_REG_ZERO(svfa, payload);
1686 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port;
1687 mlxsw_reg_svfa_swid_set(payload, 0);
1688 mlxsw_reg_svfa_local_port_set(payload, local_port);
1689 mlxsw_reg_svfa_mapping_table_set(payload, mt);

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1780/* reg_spvtr_epvid_mode
1781 * Egress Port VLAN-ID Mode.
1782 * For Spectrum family, this affects the values of SPVM.e,u,pt.
1783 * Access: WO
1784 */
1785MLXSW_ITEM32(reg, spvtr, epvid_mode, 0x04, 0, 4);
1786
1787static inline void mlxsw_reg_spvtr_pack(char *payload, bool tport,
1788 u8 local_port,
1788 u16 local_port,
1789 enum mlxsw_reg_spvtr_ipvid_mode ipvid_mode)
1790{
1791 MLXSW_REG_ZERO(spvtr, payload);
1792 mlxsw_reg_spvtr_tport_set(payload, tport);
1793 mlxsw_reg_spvtr_local_port_set(payload, local_port);
1794 mlxsw_reg_spvtr_ipvid_mode_set(payload, ipvid_mode);
1795 mlxsw_reg_spvtr_ipve_set(payload, true);
1796}

--- 18 unchanged lines hidden (view full) ---

1815/* reg_svpe_vp_en
1816 * Virtual port enable.
1817 * 0 - Disable, VLAN mode (VID to FID).
1818 * 1 - Enable, Virtual port mode ({Port, VID} to FID).
1819 * Access: RW
1820 */
1821MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1822
1789 enum mlxsw_reg_spvtr_ipvid_mode ipvid_mode)
1790{
1791 MLXSW_REG_ZERO(spvtr, payload);
1792 mlxsw_reg_spvtr_tport_set(payload, tport);
1793 mlxsw_reg_spvtr_local_port_set(payload, local_port);
1794 mlxsw_reg_spvtr_ipvid_mode_set(payload, ipvid_mode);
1795 mlxsw_reg_spvtr_ipve_set(payload, true);
1796}

--- 18 unchanged lines hidden (view full) ---

1815/* reg_svpe_vp_en
1816 * Virtual port enable.
1817 * 0 - Disable, VLAN mode (VID to FID).
1818 * 1 - Enable, Virtual port mode ({Port, VID} to FID).
1819 * Access: RW
1820 */
1821MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1822
1823static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port,
1823static inline void mlxsw_reg_svpe_pack(char *payload, u16 local_port,
1824 bool enable)
1825{
1826 MLXSW_REG_ZERO(svpe, payload);
1827 mlxsw_reg_svpe_local_port_set(payload, local_port);
1828 mlxsw_reg_svpe_vp_en_set(payload, enable);
1829}
1830
1831/* SFMR - Switch FID Management Register

--- 116 unchanged lines hidden (view full) ---

1948
1949/* reg_spvmlr_rec_vid
1950 * VLAN ID to be added/removed from port or for querying.
1951 * Access: Index
1952 */
1953MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
1954 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1955
1824 bool enable)
1825{
1826 MLXSW_REG_ZERO(svpe, payload);
1827 mlxsw_reg_svpe_local_port_set(payload, local_port);
1828 mlxsw_reg_svpe_vp_en_set(payload, enable);
1829}
1830
1831/* SFMR - Switch FID Management Register

--- 116 unchanged lines hidden (view full) ---

1948
1949/* reg_spvmlr_rec_vid
1950 * VLAN ID to be added/removed from port or for querying.
1951 * Access: Index
1952 */
1953MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
1954 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1955
1956static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port,
1956static inline void mlxsw_reg_spvmlr_pack(char *payload, u16 local_port,
1957 u16 vid_begin, u16 vid_end,
1958 bool learn_enable)
1959{
1960 int num_rec = vid_end - vid_begin + 1;
1961 int i;
1962
1963 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);
1964

--- 86 unchanged lines hidden (view full) ---

2051 * Packet is initially classified as VLAN Tag if its tag0 EtherType is
2052 * equal to ether_type0.
2053 * 0: disable
2054 * 1: enable (default)
2055 * Access: RW
2056 */
2057MLXSW_ITEM32(reg, spvc, et0, 0x08, 0, 1);
2058
1957 u16 vid_begin, u16 vid_end,
1958 bool learn_enable)
1959{
1960 int num_rec = vid_end - vid_begin + 1;
1961 int i;
1962
1963 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);
1964

--- 86 unchanged lines hidden (view full) ---

2051 * Packet is initially classified as VLAN Tag if its tag0 EtherType is
2052 * equal to ether_type0.
2053 * 0: disable
2054 * 1: enable (default)
2055 * Access: RW
2056 */
2057MLXSW_ITEM32(reg, spvc, et0, 0x08, 0, 1);
2058
2059static inline void mlxsw_reg_spvc_pack(char *payload, u8 local_port, bool et1,
2059static inline void mlxsw_reg_spvc_pack(char *payload, u16 local_port, bool et1,
2060 bool et0)
2061{
2062 MLXSW_REG_ZERO(spvc, payload);
2063 mlxsw_reg_spvc_local_port_set(payload, local_port);
2064 /* Enable inner_et1 and inner_et0 to enable identification of double
2065 * tagged packets.
2066 */
2067 mlxsw_reg_spvc_inner_et1_set(payload, 1);

--- 24 unchanged lines hidden (view full) ---

2092 * Egress EtherType VLAN to push when SPVID.egr_et_set field set for the packet:
2093 * 0: ether_type0 - (default)
2094 * 1: ether_type1
2095 * 2: ether_type2
2096 * Access: RW
2097 */
2098MLXSW_ITEM32(reg, spevet, et_vlan, 0x04, 16, 2);
2099
2060 bool et0)
2061{
2062 MLXSW_REG_ZERO(spvc, payload);
2063 mlxsw_reg_spvc_local_port_set(payload, local_port);
2064 /* Enable inner_et1 and inner_et0 to enable identification of double
2065 * tagged packets.
2066 */
2067 mlxsw_reg_spvc_inner_et1_set(payload, 1);

--- 24 unchanged lines hidden (view full) ---

2092 * Egress EtherType VLAN to push when SPVID.egr_et_set field set for the packet:
2093 * 0: ether_type0 - (default)
2094 * 1: ether_type1
2095 * 2: ether_type2
2096 * Access: RW
2097 */
2098MLXSW_ITEM32(reg, spevet, et_vlan, 0x04, 16, 2);
2099
2100static inline void mlxsw_reg_spevet_pack(char *payload, u8 local_port,
2100static inline void mlxsw_reg_spevet_pack(char *payload, u16 local_port,
2101 u8 et_vlan)
2102{
2103 MLXSW_REG_ZERO(spevet, payload);
2104 mlxsw_reg_spevet_local_port_set(payload, local_port);
2105 mlxsw_reg_spevet_et_vlan_set(payload, et_vlan);
2106}
2107
2108/* CWTP - Congetion WRED ECN TClass Profile

--- 41 unchanged lines hidden (view full) ---

2150 */
2151MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN,
2152 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
2153
2154#define MLXSW_REG_CWTP_MIN_VALUE 64
2155#define MLXSW_REG_CWTP_MAX_PROFILE 2
2156#define MLXSW_REG_CWTP_DEFAULT_PROFILE 1
2157
2101 u8 et_vlan)
2102{
2103 MLXSW_REG_ZERO(spevet, payload);
2104 mlxsw_reg_spevet_local_port_set(payload, local_port);
2105 mlxsw_reg_spevet_et_vlan_set(payload, et_vlan);
2106}
2107
2108/* CWTP - Congetion WRED ECN TClass Profile

--- 41 unchanged lines hidden (view full) ---

2150 */
2151MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN,
2152 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
2153
2154#define MLXSW_REG_CWTP_MIN_VALUE 64
2155#define MLXSW_REG_CWTP_MAX_PROFILE 2
2156#define MLXSW_REG_CWTP_DEFAULT_PROFILE 1
2157
2158static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port,
2158static inline void mlxsw_reg_cwtp_pack(char *payload, u16 local_port,
2159 u8 traffic_class)
2160{
2161 int i;
2162
2163 MLXSW_REG_ZERO(cwtp, payload);
2164 mlxsw_reg_cwtp_local_port_set(payload, local_port);
2165 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class);
2166

--- 101 unchanged lines hidden (view full) ---

2268 * Index of the profile within {port, traffic class} to use.
2269 * 0 for disabling both WRED and ECN for this type of traffic.
2270 * Access: RW
2271 */
2272MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2);
2273
2274#define MLXSW_REG_CWTPM_RESET_PROFILE 0
2275
2159 u8 traffic_class)
2160{
2161 int i;
2162
2163 MLXSW_REG_ZERO(cwtp, payload);
2164 mlxsw_reg_cwtp_local_port_set(payload, local_port);
2165 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class);
2166

--- 101 unchanged lines hidden (view full) ---

2268 * Index of the profile within {port, traffic class} to use.
2269 * 0 for disabling both WRED and ECN for this type of traffic.
2270 * Access: RW
2271 */
2272MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2);
2273
2274#define MLXSW_REG_CWTPM_RESET_PROFILE 0
2275
2276static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port,
2276static inline void mlxsw_reg_cwtpm_pack(char *payload, u16 local_port,
2277 u8 traffic_class, u8 profile,
2278 bool wred, bool ecn)
2279{
2280 MLXSW_REG_ZERO(cwtpm, payload);
2281 mlxsw_reg_cwtpm_local_port_set(payload, local_port);
2282 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class);
2283 mlxsw_reg_cwtpm_ew_set(payload, wred);
2284 mlxsw_reg_cwtpm_ee_set(payload, ecn);

--- 74 unchanged lines hidden (view full) ---

2359 * ACL/ACL group identifier. If the g bit is set, this field should hold
2360 * the acl_group_id, else it should hold the acl_id.
2361 * Access: RW
2362 */
2363MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16);
2364
2365static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e,
2366 enum mlxsw_reg_pxbt_op op,
2277 u8 traffic_class, u8 profile,
2278 bool wred, bool ecn)
2279{
2280 MLXSW_REG_ZERO(cwtpm, payload);
2281 mlxsw_reg_cwtpm_local_port_set(payload, local_port);
2282 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class);
2283 mlxsw_reg_cwtpm_ew_set(payload, wred);
2284 mlxsw_reg_cwtpm_ee_set(payload, ecn);

--- 74 unchanged lines hidden (view full) ---

2359 * ACL/ACL group identifier. If the g bit is set, this field should hold
2360 * the acl_group_id, else it should hold the acl_id.
2361 * Access: RW
2362 */
2363MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16);
2364
2365static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e,
2366 enum mlxsw_reg_pxbt_op op,
2367 u8 local_port, u16 acl_info)
2367 u16 local_port, u16 acl_info)
2368{
2369 MLXSW_REG_ZERO(ppbt, payload);
2370 mlxsw_reg_ppbt_e_set(payload, e);
2371 mlxsw_reg_ppbt_op_set(payload, op);
2372 mlxsw_reg_ppbt_local_port_set(payload, local_port);
2373 mlxsw_reg_ppbt_g_set(payload, true);
2374 mlxsw_reg_ppbt_acl_info_set(payload, acl_info);
2375}

--- 1127 unchanged lines hidden (view full) ---

3503};
3504
3505/* reg_qpts_trust_state
3506 * Trust state for a given port.
3507 * Access: RW
3508 */
3509MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3);
3510
2368{
2369 MLXSW_REG_ZERO(ppbt, payload);
2370 mlxsw_reg_ppbt_e_set(payload, e);
2371 mlxsw_reg_ppbt_op_set(payload, op);
2372 mlxsw_reg_ppbt_local_port_set(payload, local_port);
2373 mlxsw_reg_ppbt_g_set(payload, true);
2374 mlxsw_reg_ppbt_acl_info_set(payload, acl_info);
2375}

--- 1127 unchanged lines hidden (view full) ---

3503};
3504
3505/* reg_qpts_trust_state
3506 * Trust state for a given port.
3507 * Access: RW
3508 */
3509MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3);
3510
3511static inline void mlxsw_reg_qpts_pack(char *payload, u8 local_port,
3511static inline void mlxsw_reg_qpts_pack(char *payload, u16 local_port,
3512 enum mlxsw_reg_qpts_trust_state ts)
3513{
3514 MLXSW_REG_ZERO(qpts, payload);
3515
3516 mlxsw_reg_qpts_local_port_set(payload, local_port);
3517 mlxsw_reg_qpts_trust_state_set(payload, ts);
3518}
3519

--- 199 unchanged lines hidden (view full) ---

3719 * Default values:
3720 * switch_prio 0 : tclass 1
3721 * switch_prio 1 : tclass 0
3722 * switch_prio i : tclass i, for i > 1
3723 * Access: RW
3724 */
3725MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4);
3726
3512 enum mlxsw_reg_qpts_trust_state ts)
3513{
3514 MLXSW_REG_ZERO(qpts, payload);
3515
3516 mlxsw_reg_qpts_local_port_set(payload, local_port);
3517 mlxsw_reg_qpts_trust_state_set(payload, ts);
3518}
3519

--- 199 unchanged lines hidden (view full) ---

3719 * Default values:
3720 * switch_prio 0 : tclass 1
3721 * switch_prio 1 : tclass 0
3722 * switch_prio i : tclass i, for i > 1
3723 * Access: RW
3724 */
3725MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4);
3726
3727static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port,
3727static inline void mlxsw_reg_qtct_pack(char *payload, u16 local_port,
3728 u8 switch_prio, u8 tclass)
3729{
3730 MLXSW_REG_ZERO(qtct, payload);
3731 mlxsw_reg_qtct_local_port_set(payload, local_port);
3732 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio);
3733 mlxsw_reg_qtct_tclass_set(payload, tclass);
3734}
3735

--- 150 unchanged lines hidden (view full) ---

3886 */
3887MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6);
3888
3889#define MLXSW_REG_QEEC_HIGHEST_SHAPER_BS 25
3890#define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1 5
3891#define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2 11
3892#define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3 11
3893
3728 u8 switch_prio, u8 tclass)
3729{
3730 MLXSW_REG_ZERO(qtct, payload);
3731 mlxsw_reg_qtct_local_port_set(payload, local_port);
3732 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio);
3733 mlxsw_reg_qtct_tclass_set(payload, tclass);
3734}
3735

--- 150 unchanged lines hidden (view full) ---

3886 */
3887MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6);
3888
3889#define MLXSW_REG_QEEC_HIGHEST_SHAPER_BS 25
3890#define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1 5
3891#define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2 11
3892#define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3 11
3893
3894static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port,
3894static inline void mlxsw_reg_qeec_pack(char *payload, u16 local_port,
3895 enum mlxsw_reg_qeec_hr hr, u8 index,
3896 u8 next_index)
3897{
3898 MLXSW_REG_ZERO(qeec, payload);
3899 mlxsw_reg_qeec_local_port_set(payload, local_port);
3900 mlxsw_reg_qeec_element_hierarchy_set(payload, hr);
3901 mlxsw_reg_qeec_element_index_set(payload, index);
3902 mlxsw_reg_qeec_next_element_index_set(payload, next_index);
3903}
3904
3895 enum mlxsw_reg_qeec_hr hr, u8 index,
3896 u8 next_index)
3897{
3898 MLXSW_REG_ZERO(qeec, payload);
3899 mlxsw_reg_qeec_local_port_set(payload, local_port);
3900 mlxsw_reg_qeec_element_hierarchy_set(payload, hr);
3901 mlxsw_reg_qeec_element_index_set(payload, index);
3902 mlxsw_reg_qeec_next_element_index_set(payload, next_index);
3903}
3904
3905static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u8 local_port,
3905static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u16 local_port,
3906 bool ptps)
3907{
3908 MLXSW_REG_ZERO(qeec, payload);
3909 mlxsw_reg_qeec_local_port_set(payload, local_port);
3910 mlxsw_reg_qeec_element_hierarchy_set(payload, MLXSW_REG_QEEC_HR_PORT);
3911 mlxsw_reg_qeec_ptps_set(payload, ptps);
3912}
3913

--- 21 unchanged lines hidden (view full) ---

3935MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1);
3936
3937/* reg_qrwe_pcp
3938 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite).
3939 * Access: RW
3940 */
3941MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1);
3942
3906 bool ptps)
3907{
3908 MLXSW_REG_ZERO(qeec, payload);
3909 mlxsw_reg_qeec_local_port_set(payload, local_port);
3910 mlxsw_reg_qeec_element_hierarchy_set(payload, MLXSW_REG_QEEC_HR_PORT);
3911 mlxsw_reg_qeec_ptps_set(payload, ptps);
3912}
3913

--- 21 unchanged lines hidden (view full) ---

3935MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1);
3936
3937/* reg_qrwe_pcp
3938 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite).
3939 * Access: RW
3940 */
3941MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1);
3942
3943static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port,
3943static inline void mlxsw_reg_qrwe_pack(char *payload, u16 local_port,
3944 bool rewrite_pcp, bool rewrite_dscp)
3945{
3946 MLXSW_REG_ZERO(qrwe, payload);
3947 mlxsw_reg_qrwe_local_port_set(payload, local_port);
3948 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp);
3949 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp);
3950}
3951

--- 63 unchanged lines hidden (view full) ---

4015 * DSCP field in the outer label of the packet for color 2 and a given port.
4016 * Reserved when e=0.
4017 * Access: RW
4018 */
4019MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp,
4020 MLXSW_REG_QPDSM_BASE_LEN, 8, 6,
4021 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4022
3944 bool rewrite_pcp, bool rewrite_dscp)
3945{
3946 MLXSW_REG_ZERO(qrwe, payload);
3947 mlxsw_reg_qrwe_local_port_set(payload, local_port);
3948 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp);
3949 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp);
3950}
3951

--- 63 unchanged lines hidden (view full) ---

4015 * DSCP field in the outer label of the packet for color 2 and a given port.
4016 * Reserved when e=0.
4017 * Access: RW
4018 */
4019MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp,
4020 MLXSW_REG_QPDSM_BASE_LEN, 8, 6,
4021 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4022
4023static inline void mlxsw_reg_qpdsm_pack(char *payload, u8 local_port)
4023static inline void mlxsw_reg_qpdsm_pack(char *payload, u16 local_port)
4024{
4025 MLXSW_REG_ZERO(qpdsm, payload);
4026 mlxsw_reg_qpdsm_local_port_set(payload, local_port);
4027}
4028
4029static inline void
4030mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp)
4031{

--- 24 unchanged lines hidden (view full) ---

4056MLXSW_ITEM32_LP(reg, qpdp, 0x00, 16, 0x00, 12);
4057
4058/* reg_qpdp_switch_prio
4059 * Default port Switch Priority (default 0)
4060 * Access: RW
4061 */
4062MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4);
4063
4024{
4025 MLXSW_REG_ZERO(qpdsm, payload);
4026 mlxsw_reg_qpdsm_local_port_set(payload, local_port);
4027}
4028
4029static inline void
4030mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp)
4031{

--- 24 unchanged lines hidden (view full) ---

4056MLXSW_ITEM32_LP(reg, qpdp, 0x00, 16, 0x00, 12);
4057
4058/* reg_qpdp_switch_prio
4059 * Default port Switch Priority (default 0)
4060 * Access: RW
4061 */
4062MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4);
4063
4064static inline void mlxsw_reg_qpdp_pack(char *payload, u8 local_port,
4064static inline void mlxsw_reg_qpdp_pack(char *payload, u16 local_port,
4065 u8 switch_prio)
4066{
4067 MLXSW_REG_ZERO(qpdp, payload);
4068 mlxsw_reg_qpdp_local_port_set(payload, local_port);
4069 mlxsw_reg_qpdp_switch_prio_set(payload, switch_prio);
4070}
4071
4072/* QPDPM - QoS Port DSCP to Priority Mapping Register

--- 29 unchanged lines hidden (view full) ---

4102/* reg_qpdpm_dscp_prio
4103 * The new Switch Priority value for the relevant DSCP value.
4104 * Access: RW
4105 */
4106MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio,
4107 MLXSW_REG_QPDPM_BASE_LEN, 0, 4,
4108 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
4109
4065 u8 switch_prio)
4066{
4067 MLXSW_REG_ZERO(qpdp, payload);
4068 mlxsw_reg_qpdp_local_port_set(payload, local_port);
4069 mlxsw_reg_qpdp_switch_prio_set(payload, switch_prio);
4070}
4071
4072/* QPDPM - QoS Port DSCP to Priority Mapping Register

--- 29 unchanged lines hidden (view full) ---

4102/* reg_qpdpm_dscp_prio
4103 * The new Switch Priority value for the relevant DSCP value.
4104 * Access: RW
4105 */
4106MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio,
4107 MLXSW_REG_QPDPM_BASE_LEN, 0, 4,
4108 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
4109
4110static inline void mlxsw_reg_qpdpm_pack(char *payload, u8 local_port)
4110static inline void mlxsw_reg_qpdpm_pack(char *payload, u16 local_port)
4111{
4112 MLXSW_REG_ZERO(qpdpm, payload);
4113 mlxsw_reg_qpdpm_local_port_set(payload, local_port);
4114}
4115
4116static inline void
4117mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio)
4118{

--- 25 unchanged lines hidden (view full) ---

4144/* reg_qtctm_mc
4145 * Multicast Mode
4146 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet
4147 * indication (default is 0, not based on Multicast packet indication).
4148 */
4149MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1);
4150
4151static inline void
4111{
4112 MLXSW_REG_ZERO(qpdpm, payload);
4113 mlxsw_reg_qpdpm_local_port_set(payload, local_port);
4114}
4115
4116static inline void
4117mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio)
4118{

--- 25 unchanged lines hidden (view full) ---

4144/* reg_qtctm_mc
4145 * Multicast Mode
4146 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet
4147 * indication (default is 0, not based on Multicast packet indication).
4148 */
4149MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1);
4150
4151static inline void
4152mlxsw_reg_qtctm_pack(char *payload, u8 local_port, bool mc)
4152mlxsw_reg_qtctm_pack(char *payload, u16 local_port, bool mc)
4153{
4154 MLXSW_REG_ZERO(qtctm, payload);
4155 mlxsw_reg_qtctm_local_port_set(payload, local_port);
4156 mlxsw_reg_qtctm_mc_set(payload, mc);
4157}
4158
4159/* QPSC - QoS PTP Shaper Configuration Register
4160 * --------------------------------------------

--- 147 unchanged lines hidden (view full) ---

4308
4309/* reg_pmlp_rx_lane
4310 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is
4311 * equal to Tx lane.
4312 * Access: RW
4313 */
4314MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false);
4315
4153{
4154 MLXSW_REG_ZERO(qtctm, payload);
4155 mlxsw_reg_qtctm_local_port_set(payload, local_port);
4156 mlxsw_reg_qtctm_mc_set(payload, mc);
4157}
4158
4159/* QPSC - QoS PTP Shaper Configuration Register
4160 * --------------------------------------------

--- 147 unchanged lines hidden (view full) ---

4308
4309/* reg_pmlp_rx_lane
4310 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is
4311 * equal to Tx lane.
4312 * Access: RW
4313 */
4314MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false);
4315
4316static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)
4316static inline void mlxsw_reg_pmlp_pack(char *payload, u16 local_port)
4317{
4318 MLXSW_REG_ZERO(pmlp, payload);
4319 mlxsw_reg_pmlp_local_port_set(payload, local_port);
4320}
4321
4322/* PMTU - Port MTU Register
4323 * ------------------------
4324 * Configures and reports the port MTU.

--- 30 unchanged lines hidden (view full) ---

4355 * The actual MTU configured on the port. Packets exceeding this size
4356 * will be dropped.
4357 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband
4358 * oper_mtu might be smaller than admin_mtu.
4359 * Access: RO
4360 */
4361MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
4362
4317{
4318 MLXSW_REG_ZERO(pmlp, payload);
4319 mlxsw_reg_pmlp_local_port_set(payload, local_port);
4320}
4321
4322/* PMTU - Port MTU Register
4323 * ------------------------
4324 * Configures and reports the port MTU.

--- 30 unchanged lines hidden (view full) ---

4355 * The actual MTU configured on the port. Packets exceeding this size
4356 * will be dropped.
4357 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband
4358 * oper_mtu might be smaller than admin_mtu.
4359 * Access: RO
4360 */
4361MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
4362
4363static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port,
4363static inline void mlxsw_reg_pmtu_pack(char *payload, u16 local_port,
4364 u16 new_mtu)
4365{
4366 MLXSW_REG_ZERO(pmtu, payload);
4367 mlxsw_reg_pmtu_local_port_set(payload, local_port);
4368 mlxsw_reg_pmtu_max_mtu_set(payload, 0);
4369 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
4370 mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
4371}

--- 177 unchanged lines hidden (view full) ---

4549};
4550
4551/* reg_ptys_connector_type
4552 * Connector type indication.
4553 * Access: RO
4554 */
4555MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4);
4556
4364 u16 new_mtu)
4365{
4366 MLXSW_REG_ZERO(pmtu, payload);
4367 mlxsw_reg_pmtu_local_port_set(payload, local_port);
4368 mlxsw_reg_pmtu_max_mtu_set(payload, 0);
4369 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
4370 mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
4371}

--- 177 unchanged lines hidden (view full) ---

4549};
4550
4551/* reg_ptys_connector_type
4552 * Connector type indication.
4553 * Access: RO
4554 */
4555MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4);
4556
4557static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port,
4557static inline void mlxsw_reg_ptys_eth_pack(char *payload, u16 local_port,
4558 u32 proto_admin, bool autoneg)
4559{
4560 MLXSW_REG_ZERO(ptys, payload);
4561 mlxsw_reg_ptys_local_port_set(payload, local_port);
4562 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
4563 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
4564 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
4565}
4566
4558 u32 proto_admin, bool autoneg)
4559{
4560 MLXSW_REG_ZERO(ptys, payload);
4561 mlxsw_reg_ptys_local_port_set(payload, local_port);
4562 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
4563 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
4564 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
4565}
4566
4567static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u8 local_port,
4567static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u16 local_port,
4568 u32 proto_admin, bool autoneg)
4569{
4570 MLXSW_REG_ZERO(ptys, payload);
4571 mlxsw_reg_ptys_local_port_set(payload, local_port);
4572 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
4573 mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin);
4574 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
4575}

--- 25 unchanged lines hidden (view full) ---

4601 if (p_eth_proto_admin)
4602 *p_eth_proto_admin =
4603 mlxsw_reg_ptys_ext_eth_proto_admin_get(payload);
4604 if (p_eth_proto_oper)
4605 *p_eth_proto_oper =
4606 mlxsw_reg_ptys_ext_eth_proto_oper_get(payload);
4607}
4608
4568 u32 proto_admin, bool autoneg)
4569{
4570 MLXSW_REG_ZERO(ptys, payload);
4571 mlxsw_reg_ptys_local_port_set(payload, local_port);
4572 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
4573 mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin);
4574 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
4575}

--- 25 unchanged lines hidden (view full) ---

4601 if (p_eth_proto_admin)
4602 *p_eth_proto_admin =
4603 mlxsw_reg_ptys_ext_eth_proto_admin_get(payload);
4604 if (p_eth_proto_oper)
4605 *p_eth_proto_oper =
4606 mlxsw_reg_ptys_ext_eth_proto_oper_get(payload);
4607}
4608
4609static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port,
4609static inline void mlxsw_reg_ptys_ib_pack(char *payload, u16 local_port,
4610 u16 proto_admin, u16 link_width)
4611{
4612 MLXSW_REG_ZERO(ptys, payload);
4613 mlxsw_reg_ptys_local_port_set(payload, local_port);
4614 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB);
4615 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin);
4616 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width);
4617}

--- 41 unchanged lines hidden (view full) ---

4659/* reg_ppad_mac
4660 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved.
4661 * If single_base_mac = 1 - the per port MAC address
4662 * Access: RW
4663 */
4664MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
4665
4666static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
4610 u16 proto_admin, u16 link_width)
4611{
4612 MLXSW_REG_ZERO(ptys, payload);
4613 mlxsw_reg_ptys_local_port_set(payload, local_port);
4614 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB);
4615 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin);
4616 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width);
4617}

--- 41 unchanged lines hidden (view full) ---

4659/* reg_ppad_mac
4660 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved.
4661 * If single_base_mac = 1 - the per port MAC address
4662 * Access: RW
4663 */
4664MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
4665
4666static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
4667 u8 local_port)
4667 u16 local_port)
4668{
4669 MLXSW_REG_ZERO(ppad, payload);
4670 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
4671 mlxsw_reg_ppad_local_port_set(payload, local_port);
4672}
4673
4674/* PAOS - Ports Administrative and Operational Status Register
4675 * -----------------------------------------------------------

--- 57 unchanged lines hidden (view full) ---

4733 * Event generation on operational state change:
4734 * 0 - Do not generate event.
4735 * 1 - Generate Event.
4736 * 2 - Generate Single Event.
4737 * Access: RW
4738 */
4739MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
4740
4668{
4669 MLXSW_REG_ZERO(ppad, payload);
4670 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
4671 mlxsw_reg_ppad_local_port_set(payload, local_port);
4672}
4673
4674/* PAOS - Ports Administrative and Operational Status Register
4675 * -----------------------------------------------------------

--- 57 unchanged lines hidden (view full) ---

4733 * Event generation on operational state change:
4734 * 0 - Do not generate event.
4735 * 1 - Generate Event.
4736 * 2 - Generate Single Event.
4737 * Access: RW
4738 */
4739MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
4740
4741static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port,
4741static inline void mlxsw_reg_paos_pack(char *payload, u16 local_port,
4742 enum mlxsw_port_admin_status status)
4743{
4744 MLXSW_REG_ZERO(paos, payload);
4745 mlxsw_reg_paos_swid_set(payload, 0);
4746 mlxsw_reg_paos_local_port_set(payload, local_port);
4747 mlxsw_reg_paos_admin_status_set(payload, status);
4748 mlxsw_reg_paos_oper_status_set(payload, 0);
4749 mlxsw_reg_paos_ase_set(payload, 1);

--- 126 unchanged lines hidden (view full) ---

4876static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en)
4877{
4878 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4879 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4880 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en);
4881 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en);
4882}
4883
4742 enum mlxsw_port_admin_status status)
4743{
4744 MLXSW_REG_ZERO(paos, payload);
4745 mlxsw_reg_paos_swid_set(payload, 0);
4746 mlxsw_reg_paos_local_port_set(payload, local_port);
4747 mlxsw_reg_paos_admin_status_set(payload, status);
4748 mlxsw_reg_paos_oper_status_set(payload, 0);
4749 mlxsw_reg_paos_ase_set(payload, 1);

--- 126 unchanged lines hidden (view full) ---

4876static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en)
4877{
4878 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4879 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4880 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en);
4881 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en);
4882}
4883
4884static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port)
4884static inline void mlxsw_reg_pfcc_pack(char *payload, u16 local_port)
4885{
4886 MLXSW_REG_ZERO(pfcc, payload);
4887 mlxsw_reg_pfcc_local_port_set(payload, local_port);
4888}
4889
4890/* PPCNT - Ports Performance Counters Register
4891 * -------------------------------------------
4892 * The PPCNT register retrieves per port performance counters.

--- 494 unchanged lines hidden (view full) ---

5387 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5388
5389/* reg_ppcnt_ecn_marked_tc
5390 * Access: RO
5391 */
5392MLXSW_ITEM64(reg, ppcnt, ecn_marked_tc,
5393 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5394
4885{
4886 MLXSW_REG_ZERO(pfcc, payload);
4887 mlxsw_reg_pfcc_local_port_set(payload, local_port);
4888}
4889
4890/* PPCNT - Ports Performance Counters Register
4891 * -------------------------------------------
4892 * The PPCNT register retrieves per port performance counters.

--- 494 unchanged lines hidden (view full) ---

5387 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5388
5389/* reg_ppcnt_ecn_marked_tc
5390 * Access: RO
5391 */
5392MLXSW_ITEM64(reg, ppcnt, ecn_marked_tc,
5393 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5394
5395static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port,
5395static inline void mlxsw_reg_ppcnt_pack(char *payload, u16 local_port,
5396 enum mlxsw_reg_ppcnt_grp grp,
5397 u8 prio_tc)
5398{
5399 MLXSW_REG_ZERO(ppcnt, payload);
5400 mlxsw_reg_ppcnt_swid_set(payload, 0);
5401 mlxsw_reg_ppcnt_local_port_set(payload, local_port);
5402 mlxsw_reg_ppcnt_pnat_set(payload, 0);
5403 mlxsw_reg_ppcnt_grp_set(payload, grp);

--- 95 unchanged lines hidden (view full) ---

5499 * Mapping of switch priority <i+8> to one of the allocated receive port
5500 * buffers.
5501 * Access: RW
5502 */
5503MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4);
5504
5505#define MLXSW_REG_PPTB_ALL_PRIO 0xFF
5506
5396 enum mlxsw_reg_ppcnt_grp grp,
5397 u8 prio_tc)
5398{
5399 MLXSW_REG_ZERO(ppcnt, payload);
5400 mlxsw_reg_ppcnt_swid_set(payload, 0);
5401 mlxsw_reg_ppcnt_local_port_set(payload, local_port);
5402 mlxsw_reg_ppcnt_pnat_set(payload, 0);
5403 mlxsw_reg_ppcnt_grp_set(payload, grp);

--- 95 unchanged lines hidden (view full) ---

5499 * Mapping of switch priority <i+8> to one of the allocated receive port
5500 * buffers.
5501 * Access: RW
5502 */
5503MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4);
5504
5505#define MLXSW_REG_PPTB_ALL_PRIO 0xFF
5506
5507static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port)
5507static inline void mlxsw_reg_pptb_pack(char *payload, u16 local_port)
5508{
5509 MLXSW_REG_ZERO(pptb, payload);
5510 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM);
5511 mlxsw_reg_pptb_local_port_set(payload, local_port);
5512 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
5513 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
5514}
5515

--- 80 unchanged lines hidden (view full) ---

5596 * buffer.
5597 * Access: RW
5598 *
5599 * Note: In Spectrum, reserved for buffer[9].
5600 */
5601MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16,
5602 0x08, 0x04, false);
5603
5508{
5509 MLXSW_REG_ZERO(pptb, payload);
5510 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM);
5511 mlxsw_reg_pptb_local_port_set(payload, local_port);
5512 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
5513 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
5514}
5515

--- 80 unchanged lines hidden (view full) ---

5596 * buffer.
5597 * Access: RW
5598 *
5599 * Note: In Spectrum, reserved for buffer[9].
5600 */
5601MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16,
5602 0x08, 0x04, false);
5603
5604static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port,
5604static inline void mlxsw_reg_pbmc_pack(char *payload, u16 local_port,
5605 u16 xoff_timer_value, u16 xoff_refresh)
5606{
5607 MLXSW_REG_ZERO(pbmc, payload);
5608 mlxsw_reg_pbmc_local_port_set(payload, local_port);
5609 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);
5610 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);
5611}
5612

--- 41 unchanged lines hidden (view full) ---

5654
5655/* reg_pspa_sub_port
5656 * Virtual port within the local port. Set to 0 when virtual ports are
5657 * disabled on the local port.
5658 * Access: Index
5659 */
5660MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
5661
5605 u16 xoff_timer_value, u16 xoff_refresh)
5606{
5607 MLXSW_REG_ZERO(pbmc, payload);
5608 mlxsw_reg_pbmc_local_port_set(payload, local_port);
5609 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);
5610 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);
5611}
5612

--- 41 unchanged lines hidden (view full) ---

5654
5655/* reg_pspa_sub_port
5656 * Virtual port within the local port. Set to 0 when virtual ports are
5657 * disabled on the local port.
5658 * Access: Index
5659 */
5660MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
5661
5662static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port)
5662static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u16 local_port)
5663{
5664 MLXSW_REG_ZERO(pspa, payload);
5665 mlxsw_reg_pspa_swid_set(payload, swid);
5666 mlxsw_reg_pspa_local_port_set(payload, local_port);
5667 mlxsw_reg_pspa_sub_port_set(payload, 0);
5668}
5669
5670/* PMAOS - Ports Module Administrative and Operational Status

--- 98 unchanged lines hidden (view full) ---

5769#define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1)
5770
5771/* reg_pplr_lb_en
5772 * Loopback enable.
5773 * Access: RW
5774 */
5775MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8);
5776
5663{
5664 MLXSW_REG_ZERO(pspa, payload);
5665 mlxsw_reg_pspa_swid_set(payload, swid);
5666 mlxsw_reg_pspa_local_port_set(payload, local_port);
5667 mlxsw_reg_pspa_sub_port_set(payload, 0);
5668}
5669
5670/* PMAOS - Ports Module Administrative and Operational Status

--- 98 unchanged lines hidden (view full) ---

5769#define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1)
5770
5771/* reg_pplr_lb_en
5772 * Loopback enable.
5773 * Access: RW
5774 */
5775MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8);
5776
5777static inline void mlxsw_reg_pplr_pack(char *payload, u8 local_port,
5777static inline void mlxsw_reg_pplr_pack(char *payload, u16 local_port,
5778 bool phy_local)
5779{
5780 MLXSW_REG_ZERO(pplr, payload);
5781 mlxsw_reg_pplr_local_port_set(payload, local_port);
5782 mlxsw_reg_pplr_lb_en_set(payload,
5783 phy_local ?
5784 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0);
5785}

--- 142 unchanged lines hidden (view full) ---

5928MLXSW_ITEM32(reg, pddr, trblsh_group_opcode, 0x08, 0, 16);
5929
5930/* reg_pddr_status_opcode
5931 * Group selector.
5932 * Access: RO
5933 */
5934MLXSW_ITEM32(reg, pddr, trblsh_status_opcode, 0x0C, 0, 16);
5935
5778 bool phy_local)
5779{
5780 MLXSW_REG_ZERO(pplr, payload);
5781 mlxsw_reg_pplr_local_port_set(payload, local_port);
5782 mlxsw_reg_pplr_lb_en_set(payload,
5783 phy_local ?
5784 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0);
5785}

--- 142 unchanged lines hidden (view full) ---

5928MLXSW_ITEM32(reg, pddr, trblsh_group_opcode, 0x08, 0, 16);
5929
5930/* reg_pddr_status_opcode
5931 * Group selector.
5932 * Access: RO
5933 */
5934MLXSW_ITEM32(reg, pddr, trblsh_status_opcode, 0x0C, 0, 16);
5935
5936static inline void mlxsw_reg_pddr_pack(char *payload, u8 local_port,
5936static inline void mlxsw_reg_pddr_pack(char *payload, u16 local_port,
5937 u8 page_select)
5938{
5939 MLXSW_REG_ZERO(pddr, payload);
5940 mlxsw_reg_pddr_local_port_set(payload, local_port);
5941 mlxsw_reg_pddr_page_select_set(payload, page_select);
5942}
5943
5944/* PMMP - Port Module Memory Map Properties Register

--- 73 unchanged lines hidden (view full) ---

6018MLXSW_ITEM32(reg, pllp, split_num, 0x04, 0, 4);
6019
6020/* reg_pllp_slot_index
6021 * Slot index (0: Main board).
6022 * Access: RO
6023 */
6024MLXSW_ITEM32(reg, pllp, slot_index, 0x08, 0, 4);
6025
5937 u8 page_select)
5938{
5939 MLXSW_REG_ZERO(pddr, payload);
5940 mlxsw_reg_pddr_local_port_set(payload, local_port);
5941 mlxsw_reg_pddr_page_select_set(payload, page_select);
5942}
5943
5944/* PMMP - Port Module Memory Map Properties Register

--- 73 unchanged lines hidden (view full) ---

6018MLXSW_ITEM32(reg, pllp, split_num, 0x04, 0, 4);
6019
6020/* reg_pllp_slot_index
6021 * Slot index (0: Main board).
6022 * Access: RO
6023 */
6024MLXSW_ITEM32(reg, pllp, slot_index, 0x08, 0, 4);
6025
6026static inline void mlxsw_reg_pllp_pack(char *payload, u8 local_port)
6026static inline void mlxsw_reg_pllp_pack(char *payload, u16 local_port)
6027{
6028 MLXSW_REG_ZERO(pllp, payload);
6029 mlxsw_reg_pllp_local_port_set(payload, local_port);
6030}
6031
6032static inline void mlxsw_reg_pllp_unpack(char *payload, u8 *label_port,
6033 u8 *split_num, u8 *slot_index)
6034{

--- 4231 unchanged lines hidden (view full) ---

10266 * Sampling rate.
10267 * Valid values are: 1 to 3.5*10^9
10268 * Value of 1 means "sample all". Default is 1.
10269 * Reserved when Spectrum-1.
10270 * Access: RW
10271 */
10272MLXSW_ITEM32(reg, mpar, probability_rate, 0x08, 0, 32);
10273
6027{
6028 MLXSW_REG_ZERO(pllp, payload);
6029 mlxsw_reg_pllp_local_port_set(payload, local_port);
6030}
6031
6032static inline void mlxsw_reg_pllp_unpack(char *payload, u8 *label_port,
6033 u8 *split_num, u8 *slot_index)
6034{

--- 4231 unchanged lines hidden (view full) ---

10266 * Sampling rate.
10267 * Valid values are: 1 to 3.5*10^9
10268 * Value of 1 means "sample all". Default is 1.
10269 * Reserved when Spectrum-1.
10270 * Access: RW
10271 */
10272MLXSW_ITEM32(reg, mpar, probability_rate, 0x08, 0, 32);
10273
10274static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port,
10274static inline void mlxsw_reg_mpar_pack(char *payload, u16 local_port,
10275 enum mlxsw_reg_mpar_i_e i_e,
10276 bool enable, u8 pa_id,
10277 u32 probability_rate)
10278{
10279 MLXSW_REG_ZERO(mpar, payload);
10280 mlxsw_reg_mpar_local_port_set(payload, local_port);
10281 mlxsw_reg_mpar_enable_set(payload, enable);
10282 mlxsw_reg_mpar_i_e_set(payload, i_e);

--- 106 unchanged lines hidden (view full) ---

10389
10390/* reg_mlcr_beacon_remain
10391 * Remaining duration of the beacon, in seconds.
10392 * 0xFFFF indicates an infinite amount of time.
10393 * Access: RO
10394 */
10395MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16);
10396
10275 enum mlxsw_reg_mpar_i_e i_e,
10276 bool enable, u8 pa_id,
10277 u32 probability_rate)
10278{
10279 MLXSW_REG_ZERO(mpar, payload);
10280 mlxsw_reg_mpar_local_port_set(payload, local_port);
10281 mlxsw_reg_mpar_enable_set(payload, enable);
10282 mlxsw_reg_mpar_i_e_set(payload, i_e);

--- 106 unchanged lines hidden (view full) ---

10389
10390/* reg_mlcr_beacon_remain
10391 * Remaining duration of the beacon, in seconds.
10392 * 0xFFFF indicates an infinite amount of time.
10393 * Access: RO
10394 */
10395MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16);
10396
10397static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port,
10397static inline void mlxsw_reg_mlcr_pack(char *payload, u16 local_port,
10398 bool active)
10399{
10400 MLXSW_REG_ZERO(mlcr, payload);
10401 mlxsw_reg_mlcr_local_port_set(payload, local_port);
10402 mlxsw_reg_mlcr_beacon_duration_set(payload, active ?
10403 MLXSW_REG_MLCR_DURATION_MAX : 0);
10404}
10405

--- 373 unchanged lines hidden (view full) ---

10779
10780/* reg_mpsc_rate
10781 * Sampling rate = 1 out of rate packets (with randomization around
10782 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX
10783 * Access: RW
10784 */
10785MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32);
10786
10398 bool active)
10399{
10400 MLXSW_REG_ZERO(mlcr, payload);
10401 mlxsw_reg_mlcr_local_port_set(payload, local_port);
10402 mlxsw_reg_mlcr_beacon_duration_set(payload, active ?
10403 MLXSW_REG_MLCR_DURATION_MAX : 0);
10404}
10405

--- 373 unchanged lines hidden (view full) ---

10779
10780/* reg_mpsc_rate
10781 * Sampling rate = 1 out of rate packets (with randomization around
10782 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX
10783 * Access: RW
10784 */
10785MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32);
10786
10787static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e,
10787static inline void mlxsw_reg_mpsc_pack(char *payload, u16 local_port, bool e,
10788 u32 rate)
10789{
10790 MLXSW_REG_ZERO(mpsc, payload);
10791 mlxsw_reg_mpsc_local_port_set(payload, local_port);
10792 mlxsw_reg_mpsc_e_set(payload, e);
10793 mlxsw_reg_mpsc_rate_set(payload, rate);
10794}
10795

--- 218 unchanged lines hidden (view full) ---

11014/* reg_momte_tclass_en
11015 * TClass/PG mirror enable. Each bit represents corresponding tclass.
11016 * 0: disable (default)
11017 * 1: enable
11018 * Access: RW
11019 */
11020MLXSW_ITEM_BIT_ARRAY(reg, momte, tclass_en, 0x08, 0x08, 1);
11021
10788 u32 rate)
10789{
10790 MLXSW_REG_ZERO(mpsc, payload);
10791 mlxsw_reg_mpsc_local_port_set(payload, local_port);
10792 mlxsw_reg_mpsc_e_set(payload, e);
10793 mlxsw_reg_mpsc_rate_set(payload, rate);
10794}
10795

--- 218 unchanged lines hidden (view full) ---

11014/* reg_momte_tclass_en
11015 * TClass/PG mirror enable. Each bit represents corresponding tclass.
11016 * 0: disable (default)
11017 * 1: enable
11018 * Access: RW
11019 */
11020MLXSW_ITEM_BIT_ARRAY(reg, momte, tclass_en, 0x08, 0x08, 1);
11021
11022static inline void mlxsw_reg_momte_pack(char *payload, u8 local_port,
11022static inline void mlxsw_reg_momte_pack(char *payload, u16 local_port,
11023 enum mlxsw_reg_momte_type type)
11024{
11025 MLXSW_REG_ZERO(momte, payload);
11026 mlxsw_reg_momte_local_port_set(payload, local_port);
11027 mlxsw_reg_momte_type_set(payload, type);
11028}
11029
11030/* MTPPPC - Time Precision Packet Port Configuration

--- 653 unchanged lines hidden (view full) ---

11684MLXSW_ITEM32_LP(reg, tnqdr, 0x00, 16, 0x00, 12);
11685
11686/* reg_tnqdr_dscp
11687 * For encapsulation, the default DSCP.
11688 * Access: RW
11689 */
11690MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6);
11691
11023 enum mlxsw_reg_momte_type type)
11024{
11025 MLXSW_REG_ZERO(momte, payload);
11026 mlxsw_reg_momte_local_port_set(payload, local_port);
11027 mlxsw_reg_momte_type_set(payload, type);
11028}
11029
11030/* MTPPPC - Time Precision Packet Port Configuration

--- 653 unchanged lines hidden (view full) ---

11684MLXSW_ITEM32_LP(reg, tnqdr, 0x00, 16, 0x00, 12);
11685
11686/* reg_tnqdr_dscp
11687 * For encapsulation, the default DSCP.
11688 * Access: RW
11689 */
11690MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6);
11691
11692static inline void mlxsw_reg_tnqdr_pack(char *payload, u8 local_port)
11692static inline void mlxsw_reg_tnqdr_pack(char *payload, u16 local_port)
11693{
11694 MLXSW_REG_ZERO(tnqdr, payload);
11695 mlxsw_reg_tnqdr_local_port_set(payload, local_port);
11696 mlxsw_reg_tnqdr_dscp_set(payload, 0);
11697}
11698
11699/* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register
11700 * --------------------------------------------------------

--- 365 unchanged lines hidden (view full) ---

12066MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
12067
12068/* reg_sbcm_pool
12069 * Association of the port-priority to a pool.
12070 * Access: RW
12071 */
12072MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
12073
11693{
11694 MLXSW_REG_ZERO(tnqdr, payload);
11695 mlxsw_reg_tnqdr_local_port_set(payload, local_port);
11696 mlxsw_reg_tnqdr_dscp_set(payload, 0);
11697}
11698
11699/* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register
11700 * --------------------------------------------------------

--- 365 unchanged lines hidden (view full) ---

12066MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
12067
12068/* reg_sbcm_pool
12069 * Association of the port-priority to a pool.
12070 * Access: RW
12071 */
12072MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
12073
12074static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff,
12074static inline void mlxsw_reg_sbcm_pack(char *payload, u16 local_port, u8 pg_buff,
12075 enum mlxsw_reg_sbxx_dir dir,
12076 u32 min_buff, u32 max_buff,
12077 bool infi_max, u8 pool)
12078{
12079 MLXSW_REG_ZERO(sbcm, payload);
12080 mlxsw_reg_sbcm_local_port_set(payload, local_port);
12081 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);
12082 mlxsw_reg_sbcm_dir_set(payload, dir);

--- 69 unchanged lines hidden (view full) ---

12152 * the following values:
12153 * 0: 0
12154 * i: (1/128)*2^(i-1), for i=1..14
12155 * 0xFF: Infinity
12156 * Access: RW
12157 */
12158MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
12159
12075 enum mlxsw_reg_sbxx_dir dir,
12076 u32 min_buff, u32 max_buff,
12077 bool infi_max, u8 pool)
12078{
12079 MLXSW_REG_ZERO(sbcm, payload);
12080 mlxsw_reg_sbcm_local_port_set(payload, local_port);
12081 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);
12082 mlxsw_reg_sbcm_dir_set(payload, dir);

--- 69 unchanged lines hidden (view full) ---

12152 * the following values:
12153 * 0: 0
12154 * i: (1/128)*2^(i-1), for i=1..14
12155 * 0xFF: Infinity
12156 * Access: RW
12157 */
12158MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
12159
12160static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool,
12160static inline void mlxsw_reg_sbpm_pack(char *payload, u16 local_port, u8 pool,
12161 enum mlxsw_reg_sbxx_dir dir, bool clr,
12162 u32 min_buff, u32 max_buff)
12163{
12164 MLXSW_REG_ZERO(sbpm, payload);
12165 mlxsw_reg_sbpm_local_port_set(payload, local_port);
12166 mlxsw_reg_sbpm_pool_set(payload, pool);
12167 mlxsw_reg_sbpm_dir_set(payload, dir);
12168 mlxsw_reg_sbpm_clr_set(payload, clr);

--- 178 unchanged lines hidden (view full) ---

12347/* reg_sbib_buff_size
12348 * Units represented in cells
12349 * Allowed range is 0 to (cap_max_headroom_size - 1)
12350 * Default is 0
12351 * Access: RW
12352 */
12353MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24);
12354
12161 enum mlxsw_reg_sbxx_dir dir, bool clr,
12162 u32 min_buff, u32 max_buff)
12163{
12164 MLXSW_REG_ZERO(sbpm, payload);
12165 mlxsw_reg_sbpm_local_port_set(payload, local_port);
12166 mlxsw_reg_sbpm_pool_set(payload, pool);
12167 mlxsw_reg_sbpm_dir_set(payload, dir);
12168 mlxsw_reg_sbpm_clr_set(payload, clr);

--- 178 unchanged lines hidden (view full) ---

12347/* reg_sbib_buff_size
12348 * Units represented in cells
12349 * Allowed range is 0 to (cap_max_headroom_size - 1)
12350 * Default is 0
12351 * Access: RW
12352 */
12353MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24);
12354
12355static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port,
12355static inline void mlxsw_reg_sbib_pack(char *payload, u16 local_port,
12356 u32 buff_size)
12357{
12358 MLXSW_REG_ZERO(sbib, payload);
12359 mlxsw_reg_sbib_local_port_set(payload, local_port);
12360 mlxsw_reg_sbib_buff_size_set(payload, buff_size);
12361}
12362
12363static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {

--- 208 unchanged lines hidden --- 		12356 u32 buff_size)
12357{
12358 MLXSW_REG_ZERO(sbib, payload);
12359 mlxsw_reg_sbib_local_port_set(payload, local_port);
12360 mlxsw_reg_sbib_buff_size_set(payload, buff_size);
12361}
12362
12363static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {

--- 208 unchanged lines hidden ---