cmd.c (1136fa0c07de570dc17858745af8be169d1440ba) cmd.c (3a351118dc847856c1052f2bb7c76ad3d7ffbb66)
1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file

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1989
1990 for (i = 0; i < MLX4_NUM_UP; i++)
1991 mlx4_dbg(dev, "Port %d UP %d Allocated %d VPPs\n", port, i,
1992 vpp_param[i]);
1993}
1994
1995static int mlx4_master_activate_admin_state(struct mlx4_priv *priv, int slave)
1996{
1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file

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1989
1990 for (i = 0; i < MLX4_NUM_UP; i++)
1991 mlx4_dbg(dev, "Port %d UP %d Allocated %d VPPs\n", port, i,
1992 vpp_param[i]);
1993}
1994
1995static int mlx4_master_activate_admin_state(struct mlx4_priv *priv, int slave)
1996{
1997 int port, err;
1997 int p, port, err;
1998 struct mlx4_vport_state *vp_admin;
1999 struct mlx4_vport_oper_state *vp_oper;
2000 struct mlx4_slave_state *slave_state =
2001 &priv->mfunc.master.slave_state[slave];
2002 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
2003 &priv->dev, slave);
1998 struct mlx4_vport_state *vp_admin;
1999 struct mlx4_vport_oper_state *vp_oper;
2000 struct mlx4_slave_state *slave_state =
2001 &priv->mfunc.master.slave_state[slave];
2002 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
2003 &priv->dev, slave);
2004 int min_port = find_first_bit(actv_ports.ports,
2005 priv->dev.caps.num_ports) + 1;
2006 int max_port = min_port - 1 +
2007 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
2008
2004
2009 for (port = min_port; port <= max_port; port++) {
2010 if (!test_bit(port - 1, actv_ports.ports))
2011 continue;
2005 for_each_set_bit(p, actv_ports.ports, priv->dev.caps.num_ports) {
2006 port = p + 1;
2012 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
2013 priv->mfunc.master.vf_admin[slave].enable_smi[port];
2014 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
2015 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
2016 if (vp_admin->vlan_proto != htons(ETH_P_8021AD) ||
2017 slave_state->vst_qinq_supported) {
2018 vp_oper->state.vlan_proto = vp_admin->vlan_proto;
2019 vp_oper->state.default_vlan = vp_admin->default_vlan;

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2058 vp_oper->state.mac, vp_oper->mac_idx, slave, port);
2059 }
2060 }
2061 return 0;
2062}
2063
2064static void mlx4_master_deactivate_admin_state(struct mlx4_priv *priv, int slave)
2065{
2007 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
2008 priv->mfunc.master.vf_admin[slave].enable_smi[port];
2009 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
2010 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
2011 if (vp_admin->vlan_proto != htons(ETH_P_8021AD) ||
2012 slave_state->vst_qinq_supported) {
2013 vp_oper->state.vlan_proto = vp_admin->vlan_proto;
2014 vp_oper->state.default_vlan = vp_admin->default_vlan;

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2053 vp_oper->state.mac, vp_oper->mac_idx, slave, port);
2054 }
2055 }
2056 return 0;
2057}
2058
2059static void mlx4_master_deactivate_admin_state(struct mlx4_priv *priv, int slave)
2060{
2066 int port;
2061 int p, port;
2067 struct mlx4_vport_oper_state *vp_oper;
2068 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
2069 &priv->dev, slave);
2062 struct mlx4_vport_oper_state *vp_oper;
2063 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
2064 &priv->dev, slave);
2070 int min_port = find_first_bit(actv_ports.ports,
2071 priv->dev.caps.num_ports) + 1;
2072 int max_port = min_port - 1 +
2073 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
2074
2065
2075
2076 for (port = min_port; port <= max_port; port++) {
2077 if (!test_bit(port - 1, actv_ports.ports))
2078 continue;
2066 for_each_set_bit(p, actv_ports.ports, priv->dev.caps.num_ports) {
2067 port = p + 1;
2079 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
2080 MLX4_VF_SMI_DISABLED;
2081 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
2082 if (NO_INDX != vp_oper->vlan_idx) {
2083 __mlx4_unregister_vlan(&priv->dev,
2084 port, vp_oper->state.default_vlan);
2085 vp_oper->vlan_idx = NO_INDX;
2086 }

--- 1353 unchanged lines hidden --- 		2068 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
2069 MLX4_VF_SMI_DISABLED;
2070 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
2071 if (NO_INDX != vp_oper->vlan_idx) {
2072 __mlx4_unregister_vlan(&priv->dev,
2073 port, vp_oper->state.default_vlan);
2074 vp_oper->vlan_idx = NO_INDX;
2075 }

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