korina.c (a2a12d3ae24d54c2488d06bd290e24e83eded22b) korina.c (56e2e5de441a3a6590c94e70d071a6c1790c6124)
1/*
1>/*
2 * Driver for the IDT RC32434 (Korina) on-chip ethernet controller.
3 *
4 * Copyright 2004 IDT Inc. (rischelp@idt.com)
5 * Copyright 2006 Felix Fietkau <nbd@openwrt.org>
6 * Copyright 2008 Florian Fainelli <florian@openwrt.org>
7 * Copyright 2017 Roman Yeryomin <roman@advem.lv>
8 *
9 * This program is free software; you can redistribute it and/or modify it

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318#define KORINA_TDS_MASK (KORINA_NUM_TDS - 1)
319#define RD_RING_SIZE (KORINA_NUM_RDS * sizeof(struct dma_desc))
320#define TD_RING_SIZE (KORINA_NUM_TDS * sizeof(struct dma_desc))
321
322#define TX_TIMEOUT (6000 * HZ / 1000)
323
324enum chain_status {
325 desc_filled,
2 * Driver for the IDT RC32434 (Korina) on-chip ethernet controller.
3 *
4 * Copyright 2004 IDT Inc. (rischelp@idt.com)
5 * Copyright 2006 Felix Fietkau <nbd@openwrt.org>
6 * Copyright 2008 Florian Fainelli <florian@openwrt.org>
7 * Copyright 2017 Roman Yeryomin <roman@advem.lv>
8 *
9 * This program is free software; you can redistribute it and/or modify it

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318#define KORINA_TDS_MASK (KORINA_NUM_TDS - 1)
319#define RD_RING_SIZE (KORINA_NUM_RDS * sizeof(struct dma_desc))
320#define TD_RING_SIZE (KORINA_NUM_TDS * sizeof(struct dma_desc))
321
322#define TX_TIMEOUT (6000 * HZ / 1000)
323
324enum chain_status {
325 desc_filled,
326 desc_empty
326 desc_is_empty
327};
328
329#define DMA_COUNT(count) ((count) & DMA_DESC_COUNT_MSK)
330#define IS_DMA_FINISHED(X) (((X) & (DMA_DESC_FINI)) != 0)
331#define IS_DMA_DONE(X) (((X) & (DMA_DESC_DONE)) != 0)
332#define RCVPKT_LENGTH(X) (((X) & ETH_RX_LEN) >> ETH_RX_LEN_BIT)
333
334/* Information that need to be kept for each board. */

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454
455 lp->tx_skb_dma[idx] = ca;
456 td->ca = ca;
457
458 chain_prev = (idx - 1) & KORINA_TDS_MASK;
459 chain_next = (idx + 1) & KORINA_TDS_MASK;
460
461 if (readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
327};
328
329#define DMA_COUNT(count) ((count) & DMA_DESC_COUNT_MSK)
330#define IS_DMA_FINISHED(X) (((X) & (DMA_DESC_FINI)) != 0)
331#define IS_DMA_DONE(X) (((X) & (DMA_DESC_DONE)) != 0)
332#define RCVPKT_LENGTH(X) (((X) & ETH_RX_LEN) >> ETH_RX_LEN_BIT)
333
334/* Information that need to be kept for each board. */

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454
455 lp->tx_skb_dma[idx] = ca;
456 td->ca = ca;
457
458 chain_prev = (idx - 1) & KORINA_TDS_MASK;
459 chain_next = (idx + 1) & KORINA_TDS_MASK;
460
461 if (readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
462 if (lp->tx_chain_status == desc_empty) {
462 if (lp->tx_chain_status == desc_is_empty) {
463 /* Update tail */
464 td->control = DMA_COUNT(length) |
465 DMA_DESC_COF | DMA_DESC_IOF;
466 /* Move tail */
467 lp->tx_chain_tail = chain_next;
468 /* Write to NDPTR */
469 writel(korina_tx_dma(lp, lp->tx_chain_head),
470 &lp->tx_dma_regs->dmandptr);

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481 lp->td_ring[chain_prev].link = korina_tx_dma(lp, idx);
482 /* Move tail */
483 lp->tx_chain_tail = chain_next;
484 /* Write to NDPTR */
485 writel(korina_tx_dma(lp, lp->tx_chain_head),
486 &lp->tx_dma_regs->dmandptr);
487 /* Move head to tail */
488 lp->tx_chain_head = lp->tx_chain_tail;
463 /* Update tail */
464 td->control = DMA_COUNT(length) |
465 DMA_DESC_COF | DMA_DESC_IOF;
466 /* Move tail */
467 lp->tx_chain_tail = chain_next;
468 /* Write to NDPTR */
469 writel(korina_tx_dma(lp, lp->tx_chain_head),
470 &lp->tx_dma_regs->dmandptr);

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481 lp->td_ring[chain_prev].link = korina_tx_dma(lp, idx);
482 /* Move tail */
483 lp->tx_chain_tail = chain_next;
484 /* Write to NDPTR */
485 writel(korina_tx_dma(lp, lp->tx_chain_head),
486 &lp->tx_dma_regs->dmandptr);
487 /* Move head to tail */
488 lp->tx_chain_head = lp->tx_chain_tail;
489 lp->tx_chain_status = desc_empty;
489 lp->tx_chain_status = desc_is_empty;
490 }
491 } else {
490 }
491 } else {
492 if (lp->tx_chain_status == desc_empty) {
492 if (lp->tx_chain_status == desc_is_empty) {
493 /* Update tail */
494 td->control = DMA_COUNT(length) |
495 DMA_DESC_COF | DMA_DESC_IOF;
496 /* Move tail */
497 lp->tx_chain_tail = chain_next;
498 lp->tx_chain_status = desc_filled;
499 } else {
500 /* Update tail */

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863 &lp->tx_dma_regs->dmasm);
864
865 korina_tx(dev);
866
867 if (lp->tx_chain_status == desc_filled &&
868 (readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
869 writel(korina_tx_dma(lp, lp->tx_chain_head),
870 &lp->tx_dma_regs->dmandptr);
493 /* Update tail */
494 td->control = DMA_COUNT(length) |
495 DMA_DESC_COF | DMA_DESC_IOF;
496 /* Move tail */
497 lp->tx_chain_tail = chain_next;
498 lp->tx_chain_status = desc_filled;
499 } else {
500 /* Update tail */

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863 &lp->tx_dma_regs->dmasm);
864
865 korina_tx(dev);
866
867 if (lp->tx_chain_status == desc_filled &&
868 (readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
869 writel(korina_tx_dma(lp, lp->tx_chain_head),
870 &lp->tx_dma_regs->dmandptr);
871 lp->tx_chain_status = desc_empty;
871 lp->tx_chain_status = desc_is_empty;
872 lp->tx_chain_head = lp->tx_chain_tail;
873 netif_trans_update(dev);
874 }
875 if (dmas & DMA_STAT_ERR)
876 printk(KERN_ERR "%s: DMA error\n", dev->name);
877
878 retval = IRQ_HANDLED;
879 } else

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994 for (i = 0; i < KORINA_NUM_TDS; i++) {
995 lp->td_ring[i].control = DMA_DESC_IOF;
996 lp->td_ring[i].devcs = ETH_TX_FD | ETH_TX_LD;
997 lp->td_ring[i].ca = 0;
998 lp->td_ring[i].link = 0;
999 }
1000 lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail =
1001 lp->tx_full = lp->tx_count = 0;
872 lp->tx_chain_head = lp->tx_chain_tail;
873 netif_trans_update(dev);
874 }
875 if (dmas & DMA_STAT_ERR)
876 printk(KERN_ERR "%s: DMA error\n", dev->name);
877
878 retval = IRQ_HANDLED;
879 } else

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994 for (i = 0; i < KORINA_NUM_TDS; i++) {
995 lp->td_ring[i].control = DMA_DESC_IOF;
996 lp->td_ring[i].devcs = ETH_TX_FD | ETH_TX_LD;
997 lp->td_ring[i].ca = 0;
998 lp->td_ring[i].link = 0;
999 }
1000 lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail =
1001 lp->tx_full = lp->tx_count = 0;
1002 lp->tx_chain_status = desc_empty;
1002 lp->tx_chain_status = desc_is_empty;
1003
1004 /* Initialize the receive descriptors */
1005 for (i = 0; i < KORINA_NUM_RDS; i++) {
1006 skb = netdev_alloc_skb_ip_align(dev, KORINA_RBSIZE);
1007 if (!skb)
1008 return -ENOMEM;
1009 lp->rx_skb[i] = skb;
1010 lp->rd_ring[i].control = DMA_DESC_IOD |

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1022 /* loop back receive descriptors, so the last
1023 * descriptor points to the first one */
1024 lp->rd_ring[i - 1].link = lp->rd_dma;
1025 lp->rd_ring[i - 1].control |= DMA_DESC_COD;
1026
1027 lp->rx_next_done = 0;
1028 lp->rx_chain_head = 0;
1029 lp->rx_chain_tail = 0;
1003
1004 /* Initialize the receive descriptors */
1005 for (i = 0; i < KORINA_NUM_RDS; i++) {
1006 skb = netdev_alloc_skb_ip_align(dev, KORINA_RBSIZE);
1007 if (!skb)
1008 return -ENOMEM;
1009 lp->rx_skb[i] = skb;
1010 lp->rd_ring[i].control = DMA_DESC_IOD |

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1022 /* loop back receive descriptors, so the last
1023 * descriptor points to the first one */
1024 lp->rd_ring[i - 1].link = lp->rd_dma;
1025 lp->rd_ring[i - 1].control |= DMA_DESC_COD;
1026
1027 lp->rx_next_done = 0;
1028 lp->rx_chain_head = 0;
1029 lp->rx_chain_tail = 0;
1030 lp->rx_chain_status = desc_empty;
1030 lp->rx_chain_status = desc_is_empty;
1031
1032 return 0;
1033}
1034
1035static void korina_free_ring(struct net_device *dev)
1036{
1037 struct korina_private *lp = netdev_priv(dev);
1038 int i;

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1032 return 0;
1033}
1034
1035static void korina_free_ring(struct net_device *dev)
1036{
1037 struct korina_private *lp = netdev_priv(dev);
1038 int i;

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