ixgbe.h (6f84981772535e670e4e2df051a672af229b6694) | ixgbe.h (0967bf837784a11c65d66060623a74e65211af0b) |
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1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4#ifndef _IXGBE_H_ 5#define _IXGBE_H_ 6 7#include <linux/bitops.h> 8#include <linux/types.h> --- 59 unchanged lines hidden (view full) --- 68/* Supported Rx Buffer Sizes */ 69#define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */ 70#define IXGBE_RXBUFFER_1536 1536 71#define IXGBE_RXBUFFER_2K 2048 72#define IXGBE_RXBUFFER_3K 3072 73#define IXGBE_RXBUFFER_4K 4096 74#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ 75 | 1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4#ifndef _IXGBE_H_ 5#define _IXGBE_H_ 6 7#include <linux/bitops.h> 8#include <linux/types.h> --- 59 unchanged lines hidden (view full) --- 68/* Supported Rx Buffer Sizes */ 69#define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */ 70#define IXGBE_RXBUFFER_1536 1536 71#define IXGBE_RXBUFFER_2K 2048 72#define IXGBE_RXBUFFER_3K 3072 73#define IXGBE_RXBUFFER_4K 4096 74#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ 75 |
76#define IXGBE_PKT_HDR_PAD (ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2)) 77 |
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76/* Attempt to maximize the headroom available for incoming frames. We 77 * use a 2K buffer for receives and need 1536/1534 to store the data for 78 * the frame. This leaves us with 512 bytes of room. From that we need 79 * to deduct the space needed for the shared info and the padding needed 80 * to IP align the frame. 81 * 82 * Note: For cache line sizes 256 or larger this value is going to end 83 * up negative. In these cases we should fall back to the 3K --- 1021 unchanged lines hidden --- | 78/* Attempt to maximize the headroom available for incoming frames. We 79 * use a 2K buffer for receives and need 1536/1534 to store the data for 80 * the frame. This leaves us with 512 bytes of room. From that we need 81 * to deduct the space needed for the shared info and the padding needed 82 * to IP align the frame. 83 * 84 * Note: For cache line sizes 256 or larger this value is going to end 85 * up negative. In these cases we should fall back to the 3K --- 1021 unchanged lines hidden --- |