ixgbe.h (5e24f74b6c21aba204e861a282880d6ac6cc27c0) ixgbe.h (e0d1095ae3405404d247afb00233ef837d58da83)
1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.

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49#include "ixgbe_fcoe.h"
50#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
51#ifdef CONFIG_IXGBE_DCA
52#include <linux/dca.h>
53#endif
54
55#include <net/busy_poll.h>
56
1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.

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49#include "ixgbe_fcoe.h"
50#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
51#ifdef CONFIG_IXGBE_DCA
52#include <linux/dca.h>
53#endif
54
55#include <net/busy_poll.h>
56
57#ifdef CONFIG_NET_LL_RX_POLL
57#ifdef CONFIG_NET_RX_BUSY_POLL
58#define LL_EXTENDED_STATS
59#endif
60/* common prefix used by pr_<> macros */
61#undef pr_fmt
62#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
63
64/* TX/RX descriptor defines */
65#define IXGBE_DEFAULT_TXD 512

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361 struct ixgbe_ring_container rx, tx;
362
363 struct napi_struct napi;
364 cpumask_t affinity_mask;
365 int numa_node;
366 struct rcu_head rcu; /* to avoid race with update stats on free */
367 char name[IFNAMSIZ + 9];
368
58#define LL_EXTENDED_STATS
59#endif
60/* common prefix used by pr_<> macros */
61#undef pr_fmt
62#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
63
64/* TX/RX descriptor defines */
65#define IXGBE_DEFAULT_TXD 512

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361 struct ixgbe_ring_container rx, tx;
362
363 struct napi_struct napi;
364 cpumask_t affinity_mask;
365 int numa_node;
366 struct rcu_head rcu; /* to avoid race with update stats on free */
367 char name[IFNAMSIZ + 9];
368
369#ifdef CONFIG_NET_LL_RX_POLL
369#ifdef CONFIG_NET_RX_BUSY_POLL
370 unsigned int state;
371#define IXGBE_QV_STATE_IDLE 0
372#define IXGBE_QV_STATE_NAPI 1 /* NAPI owns this QV */
373#define IXGBE_QV_STATE_POLL 2 /* poll owns this QV */
374#define IXGBE_QV_LOCKED (IXGBE_QV_STATE_NAPI | IXGBE_QV_STATE_POLL)
375#define IXGBE_QV_STATE_NAPI_YIELD 4 /* NAPI yielded this QV */
376#define IXGBE_QV_STATE_POLL_YIELD 8 /* poll yielded this QV */
377#define IXGBE_QV_YIELD (IXGBE_QV_STATE_NAPI_YIELD | IXGBE_QV_STATE_POLL_YIELD)
378#define IXGBE_QV_USER_PEND (IXGBE_QV_STATE_POLL | IXGBE_QV_STATE_POLL_YIELD)
379 spinlock_t lock;
370 unsigned int state;
371#define IXGBE_QV_STATE_IDLE 0
372#define IXGBE_QV_STATE_NAPI 1 /* NAPI owns this QV */
373#define IXGBE_QV_STATE_POLL 2 /* poll owns this QV */
374#define IXGBE_QV_LOCKED (IXGBE_QV_STATE_NAPI | IXGBE_QV_STATE_POLL)
375#define IXGBE_QV_STATE_NAPI_YIELD 4 /* NAPI yielded this QV */
376#define IXGBE_QV_STATE_POLL_YIELD 8 /* poll yielded this QV */
377#define IXGBE_QV_YIELD (IXGBE_QV_STATE_NAPI_YIELD | IXGBE_QV_STATE_POLL_YIELD)
378#define IXGBE_QV_USER_PEND (IXGBE_QV_STATE_POLL | IXGBE_QV_STATE_POLL_YIELD)
379 spinlock_t lock;
380#endif /* CONFIG_NET_LL_RX_POLL */
380#endif /* CONFIG_NET_RX_BUSY_POLL */
381
382 /* for dynamic allocation of rings associated with this q_vector */
383 struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp;
384};
381
382 /* for dynamic allocation of rings associated with this q_vector */
383 struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp;
384};
385#ifdef CONFIG_NET_LL_RX_POLL
385#ifdef CONFIG_NET_RX_BUSY_POLL
386static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector)
387{
388
389 spin_lock_init(&q_vector->lock);
390 q_vector->state = IXGBE_QV_STATE_IDLE;
391}
392
393/* called from the device poll routine to get ownership of a q_vector */

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457}
458
459/* true if a socket is polling, even if it did not get the lock */
460static inline bool ixgbe_qv_ll_polling(struct ixgbe_q_vector *q_vector)
461{
462 WARN_ON(!(q_vector->state & IXGBE_QV_LOCKED));
463 return q_vector->state & IXGBE_QV_USER_PEND;
464}
386static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector)
387{
388
389 spin_lock_init(&q_vector->lock);
390 q_vector->state = IXGBE_QV_STATE_IDLE;
391}
392
393/* called from the device poll routine to get ownership of a q_vector */

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457}
458
459/* true if a socket is polling, even if it did not get the lock */
460static inline bool ixgbe_qv_ll_polling(struct ixgbe_q_vector *q_vector)
461{
462 WARN_ON(!(q_vector->state & IXGBE_QV_LOCKED));
463 return q_vector->state & IXGBE_QV_USER_PEND;
464}
465#else /* CONFIG_NET_LL_RX_POLL */
465#else /* CONFIG_NET_RX_BUSY_POLL */
466static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector)
467{
468}
469
470static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector)
471{
472 return true;
473}

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486{
487 return false;
488}
489
490static inline bool ixgbe_qv_ll_polling(struct ixgbe_q_vector *q_vector)
491{
492 return false;
493}
466static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector)
467{
468}
469
470static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector)
471{
472 return true;
473}

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486{
487 return false;
488}
489
490static inline bool ixgbe_qv_ll_polling(struct ixgbe_q_vector *q_vector)
491{
492 return false;
493}
494#endif /* CONFIG_NET_LL_RX_POLL */
494#endif /* CONFIG_NET_RX_BUSY_POLL */
495
496#ifdef CONFIG_IXGBE_HWMON
497
498#define IXGBE_HWMON_TYPE_LOC 0
499#define IXGBE_HWMON_TYPE_TEMP 1
500#define IXGBE_HWMON_TYPE_CAUTION 2
501#define IXGBE_HWMON_TYPE_MAX 3
502

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613#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
614#define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3)
615#define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4)
616#define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5)
617#define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6)
618#define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7)
619#define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8)
620#define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9)
495
496#ifdef CONFIG_IXGBE_HWMON
497
498#define IXGBE_HWMON_TYPE_LOC 0
499#define IXGBE_HWMON_TYPE_TEMP 1
500#define IXGBE_HWMON_TYPE_CAUTION 2
501#define IXGBE_HWMON_TYPE_MAX 3
502

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613#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
614#define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3)
615#define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4)
616#define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5)
617#define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6)
618#define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7)
619#define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8)
620#define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9)
621#define IXGBE_FLAG2_PTP_PPS_ENABLED (u32)(1 << 10)
622#define IXGBE_FLAG2_BRIDGE_MODE_VEB (u32)(1 << 11)
621#define IXGBE_FLAG2_PTP_ENABLED (u32)(1 << 10)
622#define IXGBE_FLAG2_PTP_PPS_ENABLED (u32)(1 << 11)
623#define IXGBE_FLAG2_BRIDGE_MODE_VEB (u32)(1 << 12)
623
624 /* Tx fast path data */
625 int num_tx_queues;
626 u16 tx_itr_setting;
627 u16 tx_work_limit;
628
629 /* Rx fast path data */
630 int num_rx_queues;

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748};
749
750enum ixgbe_state_t {
751 __IXGBE_TESTING,
752 __IXGBE_RESETTING,
753 __IXGBE_DOWN,
754 __IXGBE_SERVICE_SCHED,
755 __IXGBE_IN_SFP_INIT,
624
625 /* Tx fast path data */
626 int num_tx_queues;
627 u16 tx_itr_setting;
628 u16 tx_work_limit;
629
630 /* Rx fast path data */
631 int num_rx_queues;

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749};
750
751enum ixgbe_state_t {
752 __IXGBE_TESTING,
753 __IXGBE_RESETTING,
754 __IXGBE_DOWN,
755 __IXGBE_SERVICE_SCHED,
756 __IXGBE_IN_SFP_INIT,
756 __IXGBE_PTP_RUNNING,
757 __IXGBE_READ_I2C,
757};
758
759struct ixgbe_cb {
760 union { /* Union defining head/tail partner */
761 struct sk_buff *head;
762 struct sk_buff *tail;
763 };
764 dma_addr_t dma;

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759
760struct ixgbe_cb {
761 union { /* Union defining head/tail partner */
762 struct sk_buff *head;
763 struct sk_buff *tail;
764 };
765 dma_addr_t dma;

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