ice.h (1758047057dbe329be712a31b79db7151b5871f8) ice.h (40319796b7321e25d23671e525e01a1f4d85f6b6)
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2018, Intel Corporation. */
3
4#ifndef _ICE_H_
5#define _ICE_H_
6
7#include <linux/types.h>
8#include <linux/errno.h>

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107/* All VF control VSIs share the same IRQ, so assign a unique ID for them */
108#define ICE_RES_VF_CTRL_VEC_ID (ICE_RES_RDMA_VEC_ID - 1)
109#define ICE_INVAL_Q_INDEX 0xffff
110#define ICE_INVAL_VFID 256
111
112#define ICE_MAX_RXQS_PER_TC 256 /* Used when setting VSI context per TC Rx queues */
113
114#define ICE_CHNL_START_TC 1
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2018, Intel Corporation. */
3
4#ifndef _ICE_H_
5#define _ICE_H_
6
7#include <linux/types.h>
8#include <linux/errno.h>

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107/* All VF control VSIs share the same IRQ, so assign a unique ID for them */
108#define ICE_RES_VF_CTRL_VEC_ID (ICE_RES_RDMA_VEC_ID - 1)
109#define ICE_INVAL_Q_INDEX 0xffff
110#define ICE_INVAL_VFID 256
111
112#define ICE_MAX_RXQS_PER_TC 256 /* Used when setting VSI context per TC Rx queues */
113
114#define ICE_CHNL_START_TC 1
115#define ICE_CHNL_MAX_TC 16
116
117#define ICE_MAX_RESET_WAIT 20
118
119#define ICE_VSIQF_HKEY_ARRAY_SIZE ((VSIQF_HKEY_MAX_INDEX + 1) * 4)
120
121#define ICE_DFLT_NETIF_M (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
122
123#define ICE_MAX_MTU (ICE_AQ_SET_MAC_FRAME_SIZE_MAX - ICE_ETH_PKT_HDR_PAD)

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196 u16 base_q;
197 u16 num_rxq;
198 u16 num_txq;
199 u16 vsi_num;
200 u8 ena_tc;
201 struct ice_aqc_vsi_props info;
202 u64 max_tx_rate;
203 u64 min_tx_rate;
115
116#define ICE_MAX_RESET_WAIT 20
117
118#define ICE_VSIQF_HKEY_ARRAY_SIZE ((VSIQF_HKEY_MAX_INDEX + 1) * 4)
119
120#define ICE_DFLT_NETIF_M (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
121
122#define ICE_MAX_MTU (ICE_AQ_SET_MAC_FRAME_SIZE_MAX - ICE_ETH_PKT_HDR_PAD)

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195 u16 base_q;
196 u16 num_rxq;
197 u16 num_txq;
198 u16 vsi_num;
199 u8 ena_tc;
200 struct ice_aqc_vsi_props info;
201 u64 max_tx_rate;
202 u64 min_tx_rate;
203 atomic_t num_sb_fltr;
204 struct ice_vsi *ch_vsi;
205};
206
207struct ice_txq_meta {
208 u32 q_teid; /* Tx-scheduler element identifier */
209 u16 q_id; /* Entry in VSI's txq_map bitmap */
210 u16 q_handle; /* Relative index of Tx queue within TC */
211 u16 vsi_idx; /* VSI index that Tx queue belongs to */

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498 u32 num_vsis;
499 u8 valid;
500};
501
502struct ice_pf {
503 struct pci_dev *pdev;
504
505 struct devlink_region *nvm_region;
204 struct ice_vsi *ch_vsi;
205};
206
207struct ice_txq_meta {
208 u32 q_teid; /* Tx-scheduler element identifier */
209 u16 q_id; /* Entry in VSI's txq_map bitmap */
210 u16 q_handle; /* Relative index of Tx queue within TC */
211 u16 vsi_idx; /* VSI index that Tx queue belongs to */

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498 u32 num_vsis;
499 u8 valid;
500};
501
502struct ice_pf {
503 struct pci_dev *pdev;
504
505 struct devlink_region *nvm_region;
506 struct devlink_region *sram_region;
506 struct devlink_region *devcaps_region;
507
508 /* devlink port data */
509 struct devlink_port devlink_port;
510
511 /* OS reserved IRQ details */
512 struct msix_entry *msix_entries;
513 struct ice_res_tracker *irq_tracker;

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547 struct ice_ptp ptp;
548 u16 num_rdma_msix; /* Total MSIX vectors for RDMA driver */
549 u16 rdma_base_vector;
550
551 /* spinlock to protect the AdminQ wait list */
552 spinlock_t aq_wait_lock;
553 struct hlist_head aq_wait_list;
554 wait_queue_head_t aq_wait_queue;
507 struct devlink_region *devcaps_region;
508
509 /* devlink port data */
510 struct devlink_port devlink_port;
511
512 /* OS reserved IRQ details */
513 struct msix_entry *msix_entries;
514 struct ice_res_tracker *irq_tracker;

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548 struct ice_ptp ptp;
549 u16 num_rdma_msix; /* Total MSIX vectors for RDMA driver */
550 u16 rdma_base_vector;
551
552 /* spinlock to protect the AdminQ wait list */
553 spinlock_t aq_wait_lock;
554 struct hlist_head aq_wait_list;
555 wait_queue_head_t aq_wait_queue;
556 bool fw_emp_reset_disabled;
555
556 wait_queue_head_t reset_wait_queue;
557
558 u32 hw_csum_rx_error;
559 u16 oicr_idx; /* Other interrupt cause MSIX vector index */
560 u16 num_avail_sw_msix; /* remaining MSIX SW vectors left unclaimed */
561 u16 max_pf_txqs; /* Total Tx queues PF wide */
562 u16 max_pf_rxqs; /* Total Rx queues PF wide */

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571 u16 pfr_count; /* PF reset count */
572
573 u8 wol_ena : 1; /* software state of WoL */
574 u32 wakeup_reason; /* last wakeup reason */
575 struct ice_hw_port_stats stats;
576 struct ice_hw_port_stats stats_prev;
577 struct ice_hw hw;
578 u8 stat_prev_loaded:1; /* has previous stats been loaded */
557
558 wait_queue_head_t reset_wait_queue;
559
560 u32 hw_csum_rx_error;
561 u16 oicr_idx; /* Other interrupt cause MSIX vector index */
562 u16 num_avail_sw_msix; /* remaining MSIX SW vectors left unclaimed */
563 u16 max_pf_txqs; /* Total Tx queues PF wide */
564 u16 max_pf_rxqs; /* Total Rx queues PF wide */

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573 u16 pfr_count; /* PF reset count */
574
575 u8 wol_ena : 1; /* software state of WoL */
576 u32 wakeup_reason; /* last wakeup reason */
577 struct ice_hw_port_stats stats;
578 struct ice_hw_port_stats stats_prev;
579 struct ice_hw hw;
580 u8 stat_prev_loaded:1; /* has previous stats been loaded */
581 u8 rdma_mode;
579 u16 dcbx_cap;
580 u32 tx_timeout_count;
581 unsigned long tx_timeout_last_recovery;
582 u32 tx_timeout_recovery_level;
583 char int_name[ICE_INT_NAME_STR_LEN];
584 struct auxiliary_device *adev;
585 int aux_idx;
586 u32 sw_int_count;

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784{
785 clear_bit(ICE_FLAG_SRIOV_CAPABLE, pf->flags);
786}
787
788#define ICE_FD_STAT_CTR_BLOCK_COUNT 256
789#define ICE_FD_STAT_PF_IDX(base_idx) \
790 ((base_idx) * ICE_FD_STAT_CTR_BLOCK_COUNT)
791#define ICE_FD_SB_STAT_IDX(base_idx) ICE_FD_STAT_PF_IDX(base_idx)
582 u16 dcbx_cap;
583 u32 tx_timeout_count;
584 unsigned long tx_timeout_last_recovery;
585 u32 tx_timeout_recovery_level;
586 char int_name[ICE_INT_NAME_STR_LEN];
587 struct auxiliary_device *adev;
588 int aux_idx;
589 u32 sw_int_count;

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787{
788 clear_bit(ICE_FLAG_SRIOV_CAPABLE, pf->flags);
789}
790
791#define ICE_FD_STAT_CTR_BLOCK_COUNT 256
792#define ICE_FD_STAT_PF_IDX(base_idx) \
793 ((base_idx) * ICE_FD_STAT_CTR_BLOCK_COUNT)
794#define ICE_FD_SB_STAT_IDX(base_idx) ICE_FD_STAT_PF_IDX(base_idx)
795#define ICE_FD_STAT_CH 1
796#define ICE_FD_CH_STAT_IDX(base_idx) \
797 (ICE_FD_STAT_PF_IDX(base_idx) + ICE_FD_STAT_CH)
792
793/**
794 * ice_is_adq_active - any active ADQs
795 * @pf: pointer to PF
796 *
797 * This function returns true if there are any ADQs configured (which is
798 * determined by looking at VSI type (which should be VSI_PF), numtc, and
799 * TC_MQPRIO flag) otherwise return false

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842int ice_set_rss_key(struct ice_vsi *vsi, u8 *seed);
843int ice_get_rss_key(struct ice_vsi *vsi, u8 *seed);
844void ice_fill_rss_lut(u8 *lut, u16 rss_table_size, u16 rss_size);
845int ice_schedule_reset(struct ice_pf *pf, enum ice_reset_req reset);
846void ice_print_link_msg(struct ice_vsi *vsi, bool isup);
847int ice_plug_aux_dev(struct ice_pf *pf);
848void ice_unplug_aux_dev(struct ice_pf *pf);
849int ice_init_rdma(struct ice_pf *pf);
798
799/**
800 * ice_is_adq_active - any active ADQs
801 * @pf: pointer to PF
802 *
803 * This function returns true if there are any ADQs configured (which is
804 * determined by looking at VSI type (which should be VSI_PF), numtc, and
805 * TC_MQPRIO flag) otherwise return false

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848int ice_set_rss_key(struct ice_vsi *vsi, u8 *seed);
849int ice_get_rss_key(struct ice_vsi *vsi, u8 *seed);
850void ice_fill_rss_lut(u8 *lut, u16 rss_table_size, u16 rss_size);
851int ice_schedule_reset(struct ice_pf *pf, enum ice_reset_req reset);
852void ice_print_link_msg(struct ice_vsi *vsi, bool isup);
853int ice_plug_aux_dev(struct ice_pf *pf);
854void ice_unplug_aux_dev(struct ice_pf *pf);
855int ice_init_rdma(struct ice_pf *pf);
850const char *ice_stat_str(enum ice_status stat_err);
851const char *ice_aq_str(enum ice_aq_err aq_err);
852bool ice_is_wol_supported(struct ice_hw *hw);
856const char *ice_aq_str(enum ice_aq_err aq_err);
857bool ice_is_wol_supported(struct ice_hw *hw);
858void ice_fdir_del_all_fltrs(struct ice_vsi *vsi);
853int
854ice_fdir_write_fltr(struct ice_pf *pf, struct ice_fdir_fltr *input, bool add,
855 bool is_tun);
856void ice_vsi_manage_fdir(struct ice_vsi *vsi, bool ena);
857int ice_add_fdir_ethtool(struct ice_vsi *vsi, struct ethtool_rxnfc *cmd);
858int ice_del_fdir_ethtool(struct ice_vsi *vsi, struct ethtool_rxnfc *cmd);
859int ice_get_ethtool_fdir_entry(struct ice_hw *hw, struct ethtool_rxnfc *cmd);
860int
861ice_get_fdir_fltr_ids(struct ice_hw *hw, struct ethtool_rxnfc *cmd,
862 u32 *rule_locs);
859int
860ice_fdir_write_fltr(struct ice_pf *pf, struct ice_fdir_fltr *input, bool add,
861 bool is_tun);
862void ice_vsi_manage_fdir(struct ice_vsi *vsi, bool ena);
863int ice_add_fdir_ethtool(struct ice_vsi *vsi, struct ethtool_rxnfc *cmd);
864int ice_del_fdir_ethtool(struct ice_vsi *vsi, struct ethtool_rxnfc *cmd);
865int ice_get_ethtool_fdir_entry(struct ice_hw *hw, struct ethtool_rxnfc *cmd);
866int
867ice_get_fdir_fltr_ids(struct ice_hw *hw, struct ethtool_rxnfc *cmd,
868 u32 *rule_locs);
869void ice_fdir_rem_adq_chnl(struct ice_hw *hw, u16 vsi_idx);
863void ice_fdir_release_flows(struct ice_hw *hw);
864void ice_fdir_replay_flows(struct ice_hw *hw);
865void ice_fdir_replay_fltrs(struct ice_pf *pf);
866int ice_fdir_create_dflt_rules(struct ice_pf *pf);
867int ice_aq_wait_for_event(struct ice_pf *pf, u16 opcode, unsigned long timeout,
868 struct ice_rq_event_info *event);
869int ice_open(struct net_device *netdev);
870int ice_open_internal(struct net_device *netdev);

--- 27 unchanged lines hidden --- 		870void ice_fdir_release_flows(struct ice_hw *hw);
871void ice_fdir_replay_flows(struct ice_hw *hw);
872void ice_fdir_replay_fltrs(struct ice_pf *pf);
873int ice_fdir_create_dflt_rules(struct ice_pf *pf);
874int ice_aq_wait_for_event(struct ice_pf *pf, u16 opcode, unsigned long timeout,
875 struct ice_rq_event_info *event);
876int ice_open(struct net_device *netdev);
877int ice_open_internal(struct net_device *netdev);

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