gianfar.h (aeb12c5ef7cb08d879af22fc0a56cab9e70689ea) gianfar.h (71ff9e3df7e1c5d3293af6b595309124e8c97412)
1/*
2 * drivers/net/ethernet/freescale/gianfar.h
3 *
4 * Gianfar Ethernet Driver
5 * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560
6 * Based on 8260_io/fcc_enet.c
7 *
8 * Author: Andy Fleming

--- 398 unchanged lines hidden (view full) ---

407#define BD_LFLAG(flags) ((flags) << 16)
408#define BD_LENGTH_MASK 0x0000ffff
409
410#define FPR_FILER_MASK 0xFFFFFFFF
411#define MAX_FILER_IDX 0xFF
412
413/* This default RIR value directly corresponds
414 * to the 3-bit hash value generated */
1/*
2 * drivers/net/ethernet/freescale/gianfar.h
3 *
4 * Gianfar Ethernet Driver
5 * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560
6 * Based on 8260_io/fcc_enet.c
7 *
8 * Author: Andy Fleming

--- 398 unchanged lines hidden (view full) ---

407#define BD_LFLAG(flags) ((flags) << 16)
408#define BD_LENGTH_MASK 0x0000ffff
409
410#define FPR_FILER_MASK 0xFFFFFFFF
411#define MAX_FILER_IDX 0xFF
412
413/* This default RIR value directly corresponds
414 * to the 3-bit hash value generated */
415#define DEFAULT_RIR0 0x05397700
415#define DEFAULT_8RXQ_RIR0 0x05397700
416/* Map even hash values to Q0, and odd ones to Q1 */
417#define DEFAULT_2RXQ_RIR0 0x04104100
416
417/* RQFCR register bits */
418#define RQFCR_GPI 0x80000000
419#define RQFCR_HASHTBL_Q 0x00000000
420#define RQFCR_HASHTBL_0 0x00020000
421#define RQFCR_HASHTBL_1 0x00040000
422#define RQFCR_HASHTBL_2 0x00060000
423#define RQFCR_HASHTBL_3 0x00080000

--- 478 unchanged lines hidden (view full) ---

902 * (Backward compatible mode)
903 * MQ_MG_MODE: Multi Queue Multi Group mode
904 */
905enum {
906 SQ_SG_MODE = 0,
907 MQ_MG_MODE
908};
909
418
419/* RQFCR register bits */
420#define RQFCR_GPI 0x80000000
421#define RQFCR_HASHTBL_Q 0x00000000
422#define RQFCR_HASHTBL_0 0x00020000
423#define RQFCR_HASHTBL_1 0x00040000
424#define RQFCR_HASHTBL_2 0x00060000
425#define RQFCR_HASHTBL_3 0x00080000

--- 478 unchanged lines hidden (view full) ---

904 * (Backward compatible mode)
905 * MQ_MG_MODE: Multi Queue Multi Group mode
906 */
907enum {
908 SQ_SG_MODE = 0,
909 MQ_MG_MODE
910};
911
912/* GFAR_SQ_POLLING: Single Queue NAPI polling mode
913 * The driver supports a single pair of RX/Tx queues
914 * per interrupt group (Rx/Tx int line). MQ_MG mode
915 * devices have 2 interrupt groups, so the device will
916 * have a total of 2 Tx and 2 Rx queues in this case.
917 * GFAR_MQ_POLLING: Multi Queue NAPI polling mode
918 * The driver supports all the 8 Rx and Tx HW queues
919 * each queue mapped by the Device Tree to one of
920 * the 2 interrupt groups. This mode implies significant
921 * processing overhead (CPU and controller level).
922 */
923enum gfar_poll_mode {
924 GFAR_SQ_POLLING = 0,
925 GFAR_MQ_POLLING
926};
927
910/*
911 * Per TX queue stats
912 */
913struct tx_q_stats {
914 unsigned long tx_packets;
915 unsigned long tx_bytes;
916};
917

--- 93 unchanged lines hidden (view full) ---

1011 * struct gfar_priv_grp - per group structure
1012 * @napi: the napi poll function
1013 * @priv: back pointer to the priv structure
1014 * @regs: the ioremapped register space for this group
1015 * @irqinfo: TX/RX/ER irq data for this group
1016 */
1017
1018struct gfar_priv_grp {
928/*
929 * Per TX queue stats
930 */
931struct tx_q_stats {
932 unsigned long tx_packets;
933 unsigned long tx_bytes;
934};
935

--- 93 unchanged lines hidden (view full) ---

1029 * struct gfar_priv_grp - per group structure
1030 * @napi: the napi poll function
1031 * @priv: back pointer to the priv structure
1032 * @regs: the ioremapped register space for this group
1033 * @irqinfo: TX/RX/ER irq data for this group
1034 */
1035
1036struct gfar_priv_grp {
1019 spinlock_t grplock __attribute__ ((aligned (SMP_CACHE_BYTES)));
1037 spinlock_t grplock __aligned(SMP_CACHE_BYTES);
1020 struct napi_struct napi_rx;
1021 struct napi_struct napi_tx;
1038 struct napi_struct napi_rx;
1039 struct napi_struct napi_tx;
1022 struct gfar_private *priv;
1023 struct gfar __iomem *regs;
1040 struct gfar __iomem *regs;
1024 unsigned int rstat;
1025 unsigned long num_rx_queues;
1026 unsigned long rx_bit_map;
1041 struct gfar_priv_tx_q *tx_queue;
1042 struct gfar_priv_rx_q *rx_queue;
1027 unsigned int tstat;
1043 unsigned int tstat;
1044 unsigned int rstat;
1045
1046 struct gfar_private *priv;
1028 unsigned long num_tx_queues;
1029 unsigned long tx_bit_map;
1047 unsigned long num_tx_queues;
1048 unsigned long tx_bit_map;
1049 unsigned long num_rx_queues;
1050 unsigned long rx_bit_map;
1030
1031 struct gfar_irqinfo *irqinfo[GFAR_NUM_IRQS];
1032};
1033
1034#define gfar_irq(grp, ID) \
1035 ((grp)->irqinfo[GFAR_##ID])
1036
1037enum gfar_errata {

--- 13 unchanged lines hidden (view full) ---

1051 * The GFAR buffer descriptors track the ring buffers. The rx_bd_base
1052 * and tx_bd_base always point to the currently available buffer.
1053 * The dirty_tx tracks the current buffer that is being sent by the
1054 * controller. The cur_tx and dirty_tx are equal under both completely
1055 * empty and completely full conditions. The empty/ready indicator in
1056 * the buffer descriptor determines the actual condition.
1057 */
1058struct gfar_private {
1051
1052 struct gfar_irqinfo *irqinfo[GFAR_NUM_IRQS];
1053};
1054
1055#define gfar_irq(grp, ID) \
1056 ((grp)->irqinfo[GFAR_##ID])
1057
1058enum gfar_errata {

--- 13 unchanged lines hidden (view full) ---

1072 * The GFAR buffer descriptors track the ring buffers. The rx_bd_base
1073 * and tx_bd_base always point to the currently available buffer.
1074 * The dirty_tx tracks the current buffer that is being sent by the
1075 * controller. The cur_tx and dirty_tx are equal under both completely
1076 * empty and completely full conditions. The empty/ready indicator in
1077 * the buffer descriptor determines the actual condition.
1078 */
1079struct gfar_private {
1059 unsigned int num_rx_queues;
1060
1061 struct device *dev;
1062 struct net_device *ndev;
1063 enum gfar_errata errata;
1064 unsigned int rx_buffer_size;
1065
1066 u16 uses_rxfcb;
1067 u16 padding;
1080 struct device *dev;
1081 struct net_device *ndev;
1082 enum gfar_errata errata;
1083 unsigned int rx_buffer_size;
1084
1085 u16 uses_rxfcb;
1086 u16 padding;
1087 u32 device_flags;
1068
1069 /* HW time stamping enabled flag */
1070 int hwts_rx_en;
1071 int hwts_tx_en;
1072
1073 struct gfar_priv_tx_q *tx_queue[MAX_TX_QS];
1074 struct gfar_priv_rx_q *rx_queue[MAX_RX_QS];
1075 struct gfar_priv_grp gfargrp[MAXGROUPS];
1076
1077 unsigned long state;
1088
1089 /* HW time stamping enabled flag */
1090 int hwts_rx_en;
1091 int hwts_tx_en;
1092
1093 struct gfar_priv_tx_q *tx_queue[MAX_TX_QS];
1094 struct gfar_priv_rx_q *rx_queue[MAX_RX_QS];
1095 struct gfar_priv_grp gfargrp[MAXGROUPS];
1096
1097 unsigned long state;
1078 u32 device_flags;
1079
1098
1080 unsigned int mode;
1099 unsigned short mode;
1100 unsigned short poll_mode;
1081 unsigned int num_tx_queues;
1101 unsigned int num_tx_queues;
1102 unsigned int num_rx_queues;
1082 unsigned int num_grps;
1083
1084 /* Network Statistics */
1085 struct gfar_extra_stats extra_stats;
1086
1087 /* PHY stuff */
1088 phy_interface_t interface;
1089 struct device_node *phy_node;

--- 164 unchanged lines hidden --- 		1103 unsigned int num_grps;
1104
1105 /* Network Statistics */
1106 struct gfar_extra_stats extra_stats;
1107
1108 /* PHY stuff */
1109 phy_interface_t interface;
1110 struct device_node *phy_node;

--- 164 unchanged lines hidden ---