gianfar.c (4d659fcb20d3d3302b429c889a73a92ff2804b9a) gianfar.c (4c4a6b0e8fa24a628cbca3931745d482c66d303e)
1/* drivers/net/ethernet/freescale/gianfar.c
2 *
3 * Gianfar Ethernet Driver
4 * This driver is designed for the non-CPM ethernet controllers
5 * on the 85xx and 83xx family of integrated processors
6 * Based on 8260_io/fcc_enet.c
7 *
8 * Author: Andy Fleming

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994 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
995
996 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
997 -EFAULT : 0;
998}
999
1000static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1001{
1/* drivers/net/ethernet/freescale/gianfar.c
2 *
3 * Gianfar Ethernet Driver
4 * This driver is designed for the non-CPM ethernet controllers
5 * on the 85xx and 83xx family of integrated processors
6 * Based on 8260_io/fcc_enet.c
7 *
8 * Author: Andy Fleming

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994 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
995
996 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
997 -EFAULT : 0;
998}
999
1000static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1001{
1002 struct gfar_private *priv = netdev_priv(dev);
1002 struct phy_device *phydev = dev->phydev;
1003
1004 if (!netif_running(dev))
1005 return -EINVAL;
1006
1007 if (cmd == SIOCSHWTSTAMP)
1008 return gfar_hwtstamp_set(dev, rq);
1009 if (cmd == SIOCGHWTSTAMP)
1010 return gfar_hwtstamp_get(dev, rq);
1011
1003
1004 if (!netif_running(dev))
1005 return -EINVAL;
1006
1007 if (cmd == SIOCSHWTSTAMP)
1008 return gfar_hwtstamp_set(dev, rq);
1009 if (cmd == SIOCGHWTSTAMP)
1010 return gfar_hwtstamp_get(dev, rq);
1011
1012 if (!priv->phydev)
1012 if (!phydev)
1013 return -ENODEV;
1014
1013 return -ENODEV;
1014
1015 return phy_mii_ioctl(priv->phydev, rq, cmd);
1015 return phy_mii_ioctl(phydev, rq, cmd);
1016}
1017
1018static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
1019 u32 class)
1020{
1021 u32 rqfpr = FPR_FILER_MASK;
1022 u32 rqfcr = 0x0;
1023

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1630 tempval |= MACCFG1_RX_EN;
1631 gfar_write(&regs->maccfg1, tempval);
1632
1633 } else if (wol & GFAR_WOL_FILER_UCAST) {
1634 gfar_filer_config_wol(priv);
1635 gfar_start_wol_filer(priv);
1636
1637 } else {
1016}
1017
1018static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
1019 u32 class)
1020{
1021 u32 rqfpr = FPR_FILER_MASK;
1022 u32 rqfcr = 0x0;
1023

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1630 tempval |= MACCFG1_RX_EN;
1631 gfar_write(&regs->maccfg1, tempval);
1632
1633 } else if (wol & GFAR_WOL_FILER_UCAST) {
1634 gfar_filer_config_wol(priv);
1635 gfar_start_wol_filer(priv);
1636
1637 } else {
1638 phy_stop(priv->phydev);
1638 phy_stop(ndev->phydev);
1639 }
1640
1641 return 0;
1642}
1643
1644static int gfar_resume(struct device *dev)
1645{
1646 struct gfar_private *priv = dev_get_drvdata(dev);

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1659 gfar_write(&regs->maccfg2, tempval);
1660
1661 } else if (wol & GFAR_WOL_FILER_UCAST) {
1662 /* need to stop rx only, tx is already down */
1663 gfar_halt(priv);
1664 gfar_filer_restore_table(priv);
1665
1666 } else {
1639 }
1640
1641 return 0;
1642}
1643
1644static int gfar_resume(struct device *dev)
1645{
1646 struct gfar_private *priv = dev_get_drvdata(dev);

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1659 gfar_write(&regs->maccfg2, tempval);
1660
1661 } else if (wol & GFAR_WOL_FILER_UCAST) {
1662 /* need to stop rx only, tx is already down */
1663 gfar_halt(priv);
1664 gfar_filer_restore_table(priv);
1665
1666 } else {
1667 phy_start(priv->phydev);
1667 phy_start(ndev->phydev);
1668 }
1669
1670 gfar_start(priv);
1671
1672 netif_device_attach(ndev);
1673 enable_napi(priv);
1674
1675 return 0;

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1693 gfar_init_tx_rx_base(priv);
1694
1695 gfar_start(priv);
1696
1697 priv->oldlink = 0;
1698 priv->oldspeed = 0;
1699 priv->oldduplex = -1;
1700
1668 }
1669
1670 gfar_start(priv);
1671
1672 netif_device_attach(ndev);
1673 enable_napi(priv);
1674
1675 return 0;

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1693 gfar_init_tx_rx_base(priv);
1694
1695 gfar_start(priv);
1696
1697 priv->oldlink = 0;
1698 priv->oldspeed = 0;
1699 priv->oldduplex = -1;
1700
1701 if (priv->phydev)
1702 phy_start(priv->phydev);
1701 if (ndev->phydev)
1702 phy_start(ndev->phydev);
1703
1704 netif_device_attach(ndev);
1705 enable_napi(priv);
1706
1707 return 0;
1708}
1709
1710static struct dev_pm_ops gfar_pm_ops = {

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1773 */
1774static int init_phy(struct net_device *dev)
1775{
1776 struct gfar_private *priv = netdev_priv(dev);
1777 uint gigabit_support =
1778 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1779 GFAR_SUPPORTED_GBIT : 0;
1780 phy_interface_t interface;
1703
1704 netif_device_attach(ndev);
1705 enable_napi(priv);
1706
1707 return 0;
1708}
1709
1710static struct dev_pm_ops gfar_pm_ops = {

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1773 */
1774static int init_phy(struct net_device *dev)
1775{
1776 struct gfar_private *priv = netdev_priv(dev);
1777 uint gigabit_support =
1778 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1779 GFAR_SUPPORTED_GBIT : 0;
1780 phy_interface_t interface;
1781 struct phy_device *phydev;
1781
1782 priv->oldlink = 0;
1783 priv->oldspeed = 0;
1784 priv->oldduplex = -1;
1785
1786 interface = gfar_get_interface(dev);
1787
1782
1783 priv->oldlink = 0;
1784 priv->oldspeed = 0;
1785 priv->oldduplex = -1;
1786
1787 interface = gfar_get_interface(dev);
1788
1788 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1789 interface);
1790 if (!priv->phydev) {
1789 phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1790 interface);
1791 if (!phydev) {
1791 dev_err(&dev->dev, "could not attach to PHY\n");
1792 return -ENODEV;
1793 }
1794
1795 if (interface == PHY_INTERFACE_MODE_SGMII)
1796 gfar_configure_serdes(dev);
1797
1798 /* Remove any features not supported by the controller */
1792 dev_err(&dev->dev, "could not attach to PHY\n");
1793 return -ENODEV;
1794 }
1795
1796 if (interface == PHY_INTERFACE_MODE_SGMII)
1797 gfar_configure_serdes(dev);
1798
1799 /* Remove any features not supported by the controller */
1799 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1800 priv->phydev->advertising = priv->phydev->supported;
1800 phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1801 phydev->advertising = phydev->supported;
1801
1802 /* Add support for flow control, but don't advertise it by default */
1802
1803 /* Add support for flow control, but don't advertise it by default */
1803 priv->phydev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause);
1804 phydev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause);
1804
1805 return 0;
1806}
1807
1808/* Initialize TBI PHY interface for communicating with the
1809 * SERDES lynx PHY on the chip. We communicate with this PHY
1810 * through the MDIO bus on each controller, treating it as a
1811 * "normal" PHY at the address found in the TBIPA register. We assume

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1939 set_bit(GFAR_DOWN, &priv->state);
1940 smp_mb__after_atomic();
1941
1942 disable_napi(priv);
1943
1944 /* disable ints and gracefully shut down Rx/Tx DMA */
1945 gfar_halt(priv);
1946
1805
1806 return 0;
1807}
1808
1809/* Initialize TBI PHY interface for communicating with the
1810 * SERDES lynx PHY on the chip. We communicate with this PHY
1811 * through the MDIO bus on each controller, treating it as a
1812 * "normal" PHY at the address found in the TBIPA register. We assume

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1940 set_bit(GFAR_DOWN, &priv->state);
1941 smp_mb__after_atomic();
1942
1943 disable_napi(priv);
1944
1945 /* disable ints and gracefully shut down Rx/Tx DMA */
1946 gfar_halt(priv);
1947
1947 phy_stop(priv->phydev);
1948 phy_stop(dev->phydev);
1948
1949 free_skb_resources(priv);
1950}
1951
1952static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1953{
1954 struct txbd8 *txbdp;
1955 struct gfar_private *priv = netdev_priv(tx_queue->dev);

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2199 /* Start Rx/Tx DMA and enable the interrupts */
2200 gfar_start(priv);
2201
2202 /* force link state update after mac reset */
2203 priv->oldlink = 0;
2204 priv->oldspeed = 0;
2205 priv->oldduplex = -1;
2206
1949
1950 free_skb_resources(priv);
1951}
1952
1953static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1954{
1955 struct txbd8 *txbdp;
1956 struct gfar_private *priv = netdev_priv(tx_queue->dev);

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2200 /* Start Rx/Tx DMA and enable the interrupts */
2201 gfar_start(priv);
2202
2203 /* force link state update after mac reset */
2204 priv->oldlink = 0;
2205 priv->oldspeed = 0;
2206 priv->oldduplex = -1;
2207
2207 phy_start(priv->phydev);
2208 phy_start(ndev->phydev);
2208
2209 enable_napi(priv);
2210
2211 netif_tx_wake_all_queues(ndev);
2212
2213 return 0;
2214}
2215

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2567static int gfar_close(struct net_device *dev)
2568{
2569 struct gfar_private *priv = netdev_priv(dev);
2570
2571 cancel_work_sync(&priv->reset_task);
2572 stop_gfar(dev);
2573
2574 /* Disconnect from the PHY */
2209
2210 enable_napi(priv);
2211
2212 netif_tx_wake_all_queues(ndev);
2213
2214 return 0;
2215}
2216

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2568static int gfar_close(struct net_device *dev)
2569{
2570 struct gfar_private *priv = netdev_priv(dev);
2571
2572 cancel_work_sync(&priv->reset_task);
2573 stop_gfar(dev);
2574
2575 /* Disconnect from the PHY */
2575 phy_disconnect(priv->phydev);
2576 priv->phydev = NULL;
2576 phy_disconnect(dev->phydev);
2577
2578 gfar_free_irq(priv);
2579
2580 return 0;
2581}
2582
2583/* Changes the mac address if the controller is not running. */
2584static int gfar_set_mac_address(struct net_device *dev)

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3374 * aware of new link state. The PHY code conveys this
3375 * information through variables in the phydev structure, and this
3376 * function converts those variables into the appropriate
3377 * register values, and can bring down the device if needed.
3378 */
3379static void adjust_link(struct net_device *dev)
3380{
3381 struct gfar_private *priv = netdev_priv(dev);
2577
2578 gfar_free_irq(priv);
2579
2580 return 0;
2581}
2582
2583/* Changes the mac address if the controller is not running. */
2584static int gfar_set_mac_address(struct net_device *dev)

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3374 * aware of new link state. The PHY code conveys this
3375 * information through variables in the phydev structure, and this
3376 * function converts those variables into the appropriate
3377 * register values, and can bring down the device if needed.
3378 */
3379static void adjust_link(struct net_device *dev)
3380{
3381 struct gfar_private *priv = netdev_priv(dev);
3382 struct phy_device *phydev = priv->phydev;
3382 struct phy_device *phydev = dev->phydev;
3383
3384 if (unlikely(phydev->link != priv->oldlink ||
3385 (phydev->link && (phydev->duplex != priv->oldduplex ||
3386 phydev->speed != priv->oldspeed))))
3387 gfar_update_link_state(priv);
3388}
3389
3390/* Update the hash table based on the current list of multicast

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3615 atomic64_inc(&priv->extra_stats.tx_babt);
3616 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3617 }
3618 return IRQ_HANDLED;
3619}
3620
3621static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3622{
3383
3384 if (unlikely(phydev->link != priv->oldlink ||
3385 (phydev->link && (phydev->duplex != priv->oldduplex ||
3386 phydev->speed != priv->oldspeed))))
3387 gfar_update_link_state(priv);
3388}
3389
3390/* Update the hash table based on the current list of multicast

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3615 atomic64_inc(&priv->extra_stats.tx_babt);
3616 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3617 }
3618 return IRQ_HANDLED;
3619}
3620
3621static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3622{
3623 struct phy_device *phydev = priv->phydev;
3623 struct net_device *ndev = priv->ndev;
3624 struct phy_device *phydev = ndev->phydev;
3624 u32 val = 0;
3625
3626 if (!phydev->duplex)
3627 return val;
3628
3629 if (!priv->pause_aneg_en) {
3630 if (priv->tx_pause_en)
3631 val |= MACCFG1_TX_FLOW;

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3655 }
3656
3657 return val;
3658}
3659
3660static noinline void gfar_update_link_state(struct gfar_private *priv)
3661{
3662 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3625 u32 val = 0;
3626
3627 if (!phydev->duplex)
3628 return val;
3629
3630 if (!priv->pause_aneg_en) {
3631 if (priv->tx_pause_en)
3632 val |= MACCFG1_TX_FLOW;

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3656 }
3657
3658 return val;
3659}
3660
3661static noinline void gfar_update_link_state(struct gfar_private *priv)
3662{
3663 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3663 struct phy_device *phydev = priv->phydev;
3664 struct net_device *ndev = priv->ndev;
3665 struct phy_device *phydev = ndev->phydev;
3664 struct gfar_priv_rx_q *rx_queue = NULL;
3665 int i;
3666
3667 if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
3668 return;
3669
3670 if (phydev->link) {
3671 u32 tempval1 = gfar_read(&regs->maccfg1);

--- 105 unchanged lines hidden --- 		3666 struct gfar_priv_rx_q *rx_queue = NULL;
3667 int i;
3668
3669 if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
3670 return;
3671
3672 if (phydev->link) {
3673 u32 tempval1 = gfar_read(&regs->maccfg1);

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